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15V Zero-Drift
Operational Amplifier with
Internal Capacitors
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FEATURES DESCRIPTIO
High Voltage Operation: 16V The LTC1150 is a high-voltage, high-performance
No External Components Required zero-drift operational amplifier. The two sample-and-hold
Maximum Offset Voltage: 10V capacitors usually required externally by other chopper
Maximum Offset Voltage Drift: 0.05V/C amplifiers are integrated on-chip. Further, LTCs propri-
Low Noise 1.8VP-P (0.1Hz to 10Hz) etary high-voltage CMOS structures allow the LTC1150 to
Minimum Voltage Gain: 135dB operate at up to 32V total supply voltage.
Minimum PSRR: 120dB The LTC1150 has an offset voltage of 0.5V, drift of
Minimum CMRR: 110dB 0.01V/C, 0.1Hz to 10Hz input noise voltage of 1.8VP-P
Low Supply Current: 0.8mA and a typical voltage gain of 180dB. The slew rate of 3V/s
Single Supply Operation: 4.75V to 32V and a gain bandwidth product of 2.5MHz are achieved with
Input Common Mode Range Includes Ground 0.8mA of supply current. Overload recovery times from
200A Supply Current with Pin 1 Grounded positive and negative saturation conditions are 3ms and
Typical Overload Recovery Time 20ms 20ms, respectively.
U For applications demanding low power consumption,
APPLICATIO S Pin 1 can be used to program the supply current. Pin 5 is
Strain Gauge Amplifiers an optional AC-coupled clock input, useful for
Electronic Scales synchronization.
Medical Instrumentation The LTC1150 is available in standard 8-lead, plastic dual-
Thermocouple Amplifiers in-line package, as well as an 8-lead SO package. The
High Resolution Data Acquisition LTC1150 can be a plug-in replacement for most standard
bipolar op amps with significant improvement in DC
performance.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
Single Supply Instrumentation Amplifier Noise Spectrum
160
1k
140
VOLTAGE NOISE DENSITY (nVHz)
1M
120
V+
V+ 100
1M 2 7
80
6 1k 2 7
LTC1150 60
3 6
VIN + LTC1150 VOUT
4 3 40
VIN + GAIN = 1000V/V
4 OUTPUT OFFSET 5mV 20
TOTAL SUPPLY CURRENT
DECREASES TO 400A 0
WHEN BOTH PIN 1s ARE 10 100 1k 10k 100k
GROUNDED LTC1150 TA01 FREQUENCY (Hz) LTC1150 TA02
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LTC1150
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ABSOLUTE AXI U RATI GS (Note 1)
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART ORDER PART
ISUPPLY 1 8 CLOCK OUT NUMBER TOP VIEW
NUMBER
IN 2 7 V+
+IN 3 6 OUT
LTC1150CN8 ISUPPLY 1 8 CLOCK OUT LTC1150CS8
V 4 5
EXT CLOCK IN 2 7 V+
IN
+IN 3 + 6 OUT
N8 PACKAGE EXT CLOCK
8-LEAD PDIP V 4 5
IN S8 PART
TJMAX = 110C, JA = 130C/W
S8 PACKAGE MARKING
8-LEAD PLASTIC SO
J8 PACKAGE
LTC1150MJ8 TJMAX = 110C, JA = 200C/W
8-LEAD CERDIP 1150
LTC1150CJ8
OBSOLETE PACKAGE
Consider the N8 or S8 Package as an Alternate Source
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating
temperature range otherwise specifications are at TA = 25C. VS = 15V, Pin 1 = Open, unless otherwise noted.
LTC1150M LTC1150C
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Input Offset Voltage (Note 3) 0.5 10 0.5 10 V
Average Input Offset Drift (Note 3) 0.01 0.05 0.01 0.05 V/C
Long Term Offset Voltage Drift 50 50 nV/mo
Input Offset Current 20 60 20 200 pA
1.5 0.5 nA
Input Bias Current 10 50 10 100 pA
2.5 1.0 nA
Input Noise Voltage RS = 100, 0.1Hz to 10Hz, TC2 1.8 1.8 VP-P
RS = 100, 0.1Hz to 1Hz, TC2 0.6 0.6
Input Noise Current f = 10Hz (Note 4) 1.8 1.8 fA/Hz
Common Mode Rejection Ratio VCM = V to 12V 110 130 110 130 dB
Power Supply Rejection Ratio VS = 2.375V to 16V 120 145 120 145 dB
Large-Signal Voltage Gain RL = 10k, VOUT = 10V 135 180 135 180 dB
Maximum Output Voltage Swing RL = 10k 13.5 14.5 13.5 14.5 V
RL = 10k 10.5/ 10.5/
13.5 13.5
RL = 100k 14.95 14.95
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LTC1150
ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. VS = 15V, Pin 1 = Open, unless otherwise noted.
LTC1150M LTC1150C
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Slew Rate RL = 10k, CL = 50pF 3 3 V/s
Gain Bandwidth Product 2.5 2.5 MHz
Supply Current No Load 0.8 1.5 0.8 1.5 mA
No Load, Pin 1 = V 0.2 0.2
No Load 2 2
Internal Sampling Frequency 550 550 Hz
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
VS = 5V, Pin 1 = Open, unless otherwise noted.
LTC1150M LTC1150C
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Input Offset Voltage (Note 3) 0.5 10 0.05 10 V
Average Input Offset Drift (Note 3) 0.01 0.05 0.01 0.05 V/C
Long Term Offset Voltage Drift 50 50 V/mo
Input Offset Current 10 60 10 60 pA
Input Bias Current 5 30 5 30 pA
Input Noise Voltage RS = 100, 0.1Hz to 10Hz, TC2 2.0 2.0 VP-P
RS = 100, 0.1Hz to 1Hz, TC2 0.7 0.7
Input Noise Current f = 10Hz (Note 4) 1.3 1.3 fA/Hz
Common Mode Rejection Ratio VCM = 0V to 2.7V 106 130 106 130 dB
Power Supply Rejection Ratio VS = 2.375V to 16V 120 145 120 145 dB
Large-Signal Voltage Gain RL = 10k, VOUT = 0.3V to 4.5V 115 180 115 180 dB
Maximum Output Voltage Swing RL = 10k 0.15 to 4.85 0.15 to 4.85 V
RL = 100k 0.02 to 4.97 0.02 to 4.97
Slew Rate RL = 10k, CL = 50pF 1.5 1.5 V/s
Gain Bandwidth Product 1.8 1.8 MHz
Supply Current No Load 0.4 1 0.4 1 mA
1.5 1.5
Internal Sampling Frequency 300 300 Hz
Note 1: Absolute Maximum Ratings are those values beyond which life of Note 3: These parameters are guaranteed by design. Thermocouple effects
the device may be impaired. preclude measurement of these voltage levels in high-speed automatic test
Note 2: Connecting any terminal to voltages greater than V + or less than systems. VOS is measured to a limit determined by test equipment
V may cause destructive latch-up. It is recommended that no sources capability.
operating from external supplies be applied prior to power-up of the Note 4: Current Noise is calculated from the formula:
LTC1150. IN = (2q Ib)
where q = 1.6 10 19 Coulomb.
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LTC1150
TEST CIRCUITS
Offset Voltage Test Circuit DC-10Hz Noise Test Circuit
1M 475k
V+ 100k
1k 2 7 0.1F
6 10
LTC1150 OUTPUT
3 158k 316k 475k
+ LTC1150
4 RL
+ LT1012 TO X-Y
V 0.1F 0.1F RECORDER
+
LTC1150 TC01
FOR 1Hz NOISE BW, INCREASE ALL THE CAPACITORS BY A FACTOR OF 10 LTC1150 TC02
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage Supply Current vs Temperature Gain/Phase vs Frequency
1000 1400 120 60
TA = 25C VS = 15V VS = 15V
900 100 CL = 100pF 80
1200
PHASE
80 100
SUPPLY CURRENT (A)
800
SUPPLY CURRENT (A)
GAIN
PHASE (DEGREES)
1000
700 GAIN (dB) 60 120
500 20 160
600
400 0 180
400
300 20 200
2 80 100
PIN 1 = V PHASE
PHASE (DEGREES)
800
0 60 120
GAIN (dB)
GAIN
3 600 40 140
6 20 160
PIN 1 = V 400
9 VOUT = V + 0 180
ISINK 200
12 PIN 1 = OPEN 20 200
15 0 40 220
4 8 12 16 20 24 28 32 36 1k 10k 100k 1M 100 1k 10k 100k 1M 10M
TOTAL SUPPLY VOLTAGE, V+ TO V (V) RSET, PIN 1 TO V () FREQUENCY (Hz)
LTC1150 TPC04 LTC1150 TPC05 LTC1150 TPC06
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LTC1150
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TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias Current vs Supply Undistorted Output Swing vs
Voltage Frequency Gain/Phase vs Frequency
12 30 120 60
TA = 25C VS = 2.5V
VCM = OV 100 CL = 100pF 80
10 25
PIN 1 = V PHASE
INPUT BIAS CURRENT (pA)
80 100
PHASE (DEGREES)
8 20
60 120
GAIN (dB)
6 15 40 140
PIN 1 = FLOATING
RL = 100k 20 160
4 10
0 180
2 5
20 200
0 0 40 220
0 2 4 6 8 10 12 14 16 100 1k 10k 100k 1M 100 1k 10k 100k 1M 10M
SUPPLY VOLTAGE (V) FREQUENCY (Hz) FREQUENCY (Hz)
LTC1150 TPC07 LTC1150 TPC08 LTC1150 TPC09
20
IB 100 5
10
0 0
IB +IB
10
+IB 10 5
20
10
30
40 1 15
15 10 5 0 5 10 15 50 25 0 25 50 75 100 125 0 2.5 5 7.5 10 12.5 15
INPUT COMMON MODE VOLTAGE (V) SUPPLY VOLTAGE (V)
TEMPERATURE (C)
LTC1150 TPC11 LTC1150 TPC12
LTC1150 TPC10
Offset Voltage vs
CMRR vs Frequency PSRR vs Frequency Sampling Frequency
160 160 10
POSITIVE SUPPLY, PIN 1 = OPEN VA = 15V
140 140 TA = 25C
8
120 120 PIN 1 = V
OFFSET VOLTAGE (V)
POSITIVE SUPPLY,
100 100 PIN 1 = V
CMRR (dB)
6
PSRR (dB)
80 80
60 60 4
NEGATIVE SUPPLY, PIN 1 = OPEN
PIN 1 = OPEN
40 40
2
20 20 NEGATIVE SUPPLY, PIN 1 = V
0 0 0
1 10 100 1k 10k 100k 1 10 100 1k 10k 100k 0 1k 2k 3k
FREQUENCY (Hz) FREQUENCY (Hz) SAMPLING FREQUENCY, fS (Hz)
LTC1150 TPC13 LTC1150 TPC14 LTC1150 TPC15
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LTC1150
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TYPICAL PERFOR A CE CHARACTERISTICS
Offset Voltage Drift vs Sampling 10Hz p-p Noise vs Sampling Sampling Frequency vs
Frequency Frequency Temperature
100 4 900
VS = 15V VS = 15V VS = 15V
90 TA = 25C
800
80
Small-Signal Transient Response, Overload Recovery from Negative Overload Recovery from Positive
Pin 1 = V Saturation Saturation
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LTC1150
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TYPICAL PERFOR A CE CHARACTERISTICS
0.1Hz to 10Hz Noise, V = 15V, TA = 25C, Internal Clock
2.0VP-P
1V
1.0VP-P
1V
700nVP-P
500nV
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LTC1150
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TYPICAL PERFOR A CE CHARACTERISTICS
0.1Hz to 1Hz Noise, V = 15V, TA = 25C, fS = 1800Hz
300nVP-P
500nV
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PI DESCRIPTIO S 8-Pin Packages
ISUPPLY (Pin 1): Supply Current Programming. The sup- simplified interface requirements. The amplitude of the
ply current can be programmed through Pin 1. When clock input signal needs to be greater than 2V and the
Pin 1 is left open or tied to V+, the supply current defaults voltage level has to be within the supply voltage range.
to 800A. Tying a resistor between Pin 1 and Pin 4, the Duty cycle is not critical. The internal chopping frequency
negative supply pin, will reduce the supply current. The is the external clock frequency divided by four. When
supply current, as a function of the resistor value, is frequency of the external clock falls below 100Hz (internal
shown in Typical Performance Characteristics. chopping at 25Hz), the internal oscillator takes over and
the circuit chops at 550Hz.
IN (Pin 2): Inverting Input.
OUT (Pin 6): Output.
+IN (Pin 3): Noninverting Input.
V (Pin 4): Negative Supply. V+ (Pin 7): Positive Supply.
CLOCK OUT (Pin 8): Clock Output. The signal coming out
EXT CLOCK IN (Pin 5): Optional External Clock Input. The
of this pin is at the internal oscillator frequency of about
LTC1150 has an internal oscillator to control the circuit
2.2kHz (four times the chopping frequency) and has
operation of the amplifier if Pin 5 is left open or biased at
voltage levels at VH = VS and VL = VS 4.6. If the circuit is
any DC voltage in the supply voltage range. When an
driven by an external clock, Pin 8 is pulled up to VS.
external clock is desirable, it can be applied to Pin 5. The
applied clock is AC-coupled to the internal circuitry to
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LTC1150
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APPLICATIO S I FOR ATIO
ACHIEVING PICOAMPERE/MICROVOLT number of junctions in the amplifiers input signal path.
PERFORMANCE Avoid connectors, sockets, switches, and relays where
possible. In instances where this is not possible, attempt
Picoamperes to balance the number and type of junctions so that
In order to realize the picoampere level of accuracy of the differential cancellation occurs. Doing this may involve
LTC1150, proper care must be exercised. Leakage cur- deliberately introducing junctions to offset unavoidable
rents in circuitry external to the amplifier can significantly junctions.
degrade performance. High quality insulation should be Figure 1 is an example of the introduction of an unneces-
used (e.g., Teflon, Kel-F); cleaning of all insulating sur- sary resistor to promote differential thermal balance.
faces to remove fluxes and other residues will probably Maintaining compensating junctions in close physical
be necessaryparticularly for high temperature perfor- proximity will keep them at the same temperature and
mance. Surface coating may be necessary to provide a reduce thermal EMF errors.
moisture barrier in high humidity environments.
Board leakage can be minimized by encircling the input NOMINALLY UNNECESSARY
LEAD WIRE/SOLDER
RESISTOR USED TO
connections with a guard ring operated at a potential THERMALLY BALANCE COPPER TRACE JUNCTION
OTHER INPUT RESISTOR
close to that of the inputs: in inverting configurations the +
guard ring should be tied to ground; in noninverting LTC1150 OUTPUT
connections to the inverting input. Guarding both sides
of the printed circuit board is required. Bulk leakage RESISTOR LEAD, SOLDER,
COPPER TRACE JUNCTION
reduction depends on the guard ring width.
Microvolts
Thermocouple effects must be considered if the LTC1150s
ultralow drift is to be fully utilized. Any connection of
dissimilar metals forms a thermoelectric junction produc- LTC1150 AI01
9
LTC1150
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APPLICATIO S I FOR ATIO
Table 1. Resistor Thermal EMF LEVEL SHIFTING THE CLOCK
RESISTOR TYPE THERMAL EMF/C GRADIENT Level shifting is needed if the clock output of the LTC1150
Tin Oxide ~mV/C in 15V operation must interface to regular 5V logic
Carbon Composition ~450V/C circuits. Figures 2 and 3 show some typical level shifting
Metal Film ~20V/C circuits.
WireWound When operated from single 5V or 5V supplies, the
Evenohm ~2V/C
Manganin ~2V/C
LTC1150 clock output at Pin 8 can interface to TTL or
CMOS inputs directly.
PACKAGE-INDUCED OFFSET VOLTAGE
Package-induced thermal EMF effects are another impor- LOW SUPPLY OPERATION
tant source of errors. It arises at the copper/kovar The minimum supply for proper operation of the LTC1150
junctions formed when wire or printed circuit traces is typically below 4.0V (2.0V). In single supply applica-
contact a package lead. Like all the previously mentioned tions, PSRR is guaranteed down to 4.7V (2.35V)
thermal EMF effects, it is outside the LTC1150s offset to ensure proper operation down to the minimum TTL
nulling loop and cannot be cancelled. Metal can specified voltage of 4.75V.
H packages exhibit the worst warm-up drift. The input
offset voltage specification of the LTC1150 is actually set 15V
by the package-induced warm-up drift rather than by the
circuit itself. The thermal time constant ranges from 0.5 to 10k
3 minutes, depending on package type.
2 7 5V
8
6
ALIASING 3
LTC1150
LOGIC
+ CIRCUIT
Like all sampled data systems, the LTC1150 exhibits 4 10k
aliasing behavior at input frequencies near the sampling
15V
frequency. The LTC1150 includes a high-frequency LTC1150 AI02
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LTC1150
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TYPICAL APPLICATIO S
1M 10
HP 5082-4204 V+
10k
2 7
6
IP LTC1150 OUTPUT = IP 10 9
3
+
4
LTC1150 TA03
15V 15V
1000pF
2 7
6
LTC1150 LT1010
3
+
4
SINGLE
POINT FORCED
15V 15V
SENSE GROUND
GROUND
LTC1150 TA04
APPLICATION: TO FORCE TWO GROUND POINTS IN A SYSTEM WITHIN 5V
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LTC1150
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TYPICAL APPLICATIO S
Paralleling to Improve Noise
CLK IN
10k
MEASURED NOISE
10 CLK VOS = 1.1V
FREE 10Hz = 700nVP-P
10k
LTC1150 RUN 1Hz = 200nVP-P
VOS = 10V
+ CLK
DRIVEN 10Hz = 360nVP-P
10k 1800Hz 1Hz = 160nVP-P
10
10k 25k
LTC1150
+
10k
10
LTC1150 VOUT = 10k VIN
10k
LTC1150 +
IN +
10k
10
10k
LTC1150
+
LTC1150 TA05
OPEN AT t = 0
C
+
R2 2
6
LTC1150
3
+ IR1
VOUT = t
R2C
5V 30pA R2
I ERROR +
IR1 I R1
LOAD R1
LTC1150 TA06
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LTC1150
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PACKAGE DESCRIPTIO
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
.015 .060
(0.381 1.524)
.008 .018
0 15
(0.203 0.457)
.045 .065
.125
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE (1.143 1.651)
OR TIN PLATE LEADS 3.175
.014 .026 MIN
.100
(0.360 0.660) (2.54)
BSC J8 0801
OBSOLETE PACKAGE
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LTC1150
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PACKAGE DESCRIPTIO
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
8 7 6 5
.255 .015*
(6.477 0.381)
1 2 3 4
.065
(1.651)
.008 .015 TYP
(0.203 0.381) .120
(3.048) .020
+.035 MIN (0.508)
.325 .015
.100 .018 .003 MIN
( 8.255
+0.889
0.381 ) (2.54)
BSC
(0.457 0.076)
N8 1002
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
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LTC1150
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PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 .197
.045 .005 (4.801 5.004)
.050 BSC NOTE 3
8 7 6 5
N
N
.245
MIN .160 .005
.150 .157
.228 .244
(3.810 3.988)
(5.791 6.197)
NOTE 3
1 2 3 N/2 N/2
.030 .005
TYP RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4
.010 .020
45 .053 .069
(0.254 0.508)
(1.346 1.752)
.004 .010
.008 .010
0 8 TYP (0.101 0.254)
(0.203 0.254)
.016 .050
.014 .019 .050
(0.406 1.270)
(0.355 0.483) (1.270)
NOTE: TYP BSC
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 0502
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15V
3 7
INPUT +
6
LTC1150
2
4
15V
0.01F
15V
130 68
1 15V
3 7
+ 8
6
LT1028 OUTPUT
100k 2
4
10k
15V
(A = 1000)
10
LTC1150 TA07
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