IEEE 2007 Custom Intergrated Circuits Conference (CICC)

A Low-IF CMOS Simultaneous GPS Receiver Integrated in a

Multimode Transceiver
Yang Xu, Kevin Wang, Tim Pals, Aristotele Hadjichristos, Kamal Sahota and Charles Persico

Qualcomm Inc., San Diego, CA 92121

Abstract This paper describes a GPS receiver circuit that
operates simultaneously with WCDMA/CDMA2000 transceivers.
This receiver uses a low-IF architecture to minimize the external
passive components. The RF front-end circuit dynamically
adjusts the linearity performance based on the instantaneous
transmitting power of the integrated transmitter. The receiver
measured performances are >80dB gain, 2.0dB noise figure,
>20dB image rejection, maximum out-of-band IIP3 is +6dBm.
The synthesize features -132dBc/Hz phase noise at 1MHz offset
frequency and a total integrated double sideband phase noise of
less than -30dBc in the 100Hz to 1MHz band. The receiver is
fabricated in a 0.18m RFCMOS process, and draws 36.7mA at
high linearity mode and 27.4mA at low linearity mode using
switch mode power supply.
Index Terms Low-IF architecture, GPS receiver, dynamic
switching, low noise amplifier, passive mixer.
I. INTRODUCTION
Since the FCC mandates the E911 (Enhanced 911) services,
carriers using GPS chips to help determine a user's location
need to upgrade all handsets in use to GPS-capable models.
Meanwhile, the navigation features become much desirable in
the personal communication devices such as the cellular
phones. This requires the GPS receiver works simultaneously
with placing and receiving calls in the complex
electromagnetic (EM) environment such as airport and urban
indoor environment. This put stringent requirements for GPS
receiver sensitivity and its interoperability with other cellular
systems. When the GPS receiver is embedded with the GSM
system, the GPS signal can be briefly blanked when sending
or receiving GSM signal due to its time division multiple
linearity mode. The linearity switching point is selected to
maximize the probability in the low linearity mode without
incurring extra current consumption to meet the specification.
Once the linearity mode is decided, we adjust the biasing
condition of the signal path circuits by fine tuning the DC
operating point or switching to a different path. Since the
circuit will be in high-linearity mode only a fraction of the
time in the actual cell phone operation, we expect nearly 40%
of the total current reduction by using this circuit.
We demonstrate the simultaneous GPS receiver using a
0.18m 1P4M RFCMOS process which features high density
MIM Caps and 4m-thick top metal layer for high-Q
inductors. Measurements are conducted in the complex EM
environment.
The remainder of this paper is organized as follows. The
Low-IF architecuture is briefly introduced in section 2. The
dynamic linearity mechanism is treated in section 3. We
discuss the circuit building blocks such as LNA, passive
mixer, baseband filter and PLL in section 4. We show the
experimental results in section 5, before reaching the
conclusions in section 6.
II. ARCHITECTURE
The simultaneous GPS receiver uses a low-IF architecture
due to the large guard band available around the GPS C/A
code signal spectrum [6].
DCOC SBI
DAC
1st Pole I Filter
IF I MXR

Biquad I Filter
RF I MXR

access (TDMA) nature. However, when operating with ANTENNA

LO_I

LO_Q
BBA DRV

CDMA2000/WCDMA systems, where the transmitter and Triplexer/

GPS SAW
TCXO
LNA LO_I
receiver are always turned on, the GPS receiver can be DIV by 2 &
LO Buffer LO_Q
Div by 3

significantly de-sensitized by the transmitter leakage signal Transformer

LO_I
BBA DRV

which acts as large jamming signal. RF Q MXR

1st Pole Q Filter
LO_Q

Biquad I Filter

In this paper, we describe the design and implementation of IF Q MXR

DCOC
DAC
SBI

a simultaneous GPS receiver that achieves high sensitivity and GPS- VCO

operates with existing cellular systems in different bands. The Frac - N PLL

GPS RF front-end circuit is designed to dynamically adjust the
linearity performance based on the instantaneous transmitting
power of the integrated WCDMA/CDMA2000 transmitter.
The transmitting power is calculated by reading the AGC state
and Power Amplifier (PA) state to determine whether the GPS
RF front-end should be in a high linearity mode or in a low
Figure 1: Block diagram of sGPS receiver.
The block diagram of the CMOS receiver is shown in Fig.
1. The signal path include a single-end LNA, on-chip
transformer, mixers, I/Q local oscillator (LO) driver, complex
bandpass trans-impedance amplifier (TIA), IF mixer,

1-4244-1623-X/07/$25.00 2007 IEEE 7-3-1 107

baseband low pass filter. Furthermore, an on-chip frac-N PLL
is integrated to synthesize the LO frequency for down-
conversion.
III. DYNAMIC LINEARITY SWITCHING
Unlike the stand alone GPS receiver, the sGPS receiver is
embedded in the multi-mode cellular systems with WCDMA
and CDMA2000 systems. The linearity requirements for such
sGPS receiver are much harder in a mobile terminal
environment because the large transmitter power will create
inter-modulation distortion. For example, the CDMA signal in
the AWS (1.71G) band and the external PCS band can create
in-band third-order inter-modulation distortion. To achieve the
high linearity requirement, excessive power must be
consumed in LNA, mixer and LO driver to accommodate the
jammer current.
1x Tx Power PDF
0.050
0.045
CDG Urban CDG Suburban
0.040
0.035
Probability
0.030
0.025
0.020
0.015
0.010
0.005
0.000
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
Tx Power (dBm)
Figure 2, PDF of the CDMA2000 Output Power
Nevertheless, the CDMA signal output power is not
constant. Fig. 1 shows the probability density function (PDF)
of the CDMA transmitter power under different test cases. It
reveals that the probability of transmitting the maximum
power (+24dBm) is pretty small. Since the linearity
requirement is a function of the transmitter power, we can
adjust the linearity specification based on the actual
transmitter power.
The integrated transmitter driver amplifier and the power
amplifier states are recorded in the registers and they can be
used to determine the transmitter power. Furthermore, we
choose a transmitter power switching point to determine
whether the GPS front-end is in a high linearity mode or in a
low linearity mode. Large current consumption is necessary
for the high linearity mode. However, in the low linearity
mode, we only need to consume a fraction of the current to
meet the specification, which is pretty close to the stand-alone
GPS receiver power consumption. The switching point is
carefully selected to be high enough that the circuit operates
most of its time in the low linearity mode, while low enough
that the resulting requirement can be met without extra current
consumption.
IV. BUILDING BLOCKS
The signal path of the receiver includes the LNA
transformer, RF mixers, TIA, IF mixers and bandband filter.
In the following section, each of the signal path blocks and
frequency synthesizer are presented.
A. LNA and on-chip transformer
The LNA employs a cascode common-source inductor-
degenerated topology to provide good noise performance.
Figure 3, Current tunable LNA topology
For the cascade common source LNA topology, the linearity
is determined by the overdrive voltage of the input device
[3][4]. In order to change the input device biasing without
adding any noise source at the RF input, we use a topology as
shown in Fig. 3. The cascode device source voltage is
replicated by a current mirror. An opamp is used to provide
0 5 10 15 20 25
accurate biasing for the main device even with large current
mirror ratio. Importantly, a current switch is used in the
biasing circuitry to select different biasing current, therefore,
resulting different overdrive voltage for the input devices.
Some RC low pass filter is inserted between the bias current
source and the main device. This is used to filter the noise
generated by bias circuit when large jammer signals presented.
An on-chip transformer with a high coupling coefficient is
used to convert the single-ended signal to a differential signal
in current mode. The transformer also achieves additional
current gain by adding resonant capacitors.
B. Passive mixer
Following transformer, we use a passive mixer to
downconvert the GPS signal to IF frequency. Traditional RF
passive mixers suffer the problem of high noise contribution
from the operational amplifier in the trans-impedance
amplifier (TIA) stage and the LO leakage problem. In order to
minimize the LO leakage and the mitigate the noise from the
TIA, a transonductance (gm) stage is employed between the
LNA and the mixing core. Since this gm stage need to handle
RF frequency signal, its hard to program the biasing of the
mixer gm stage.
We proposed a noise isolation passive mixer topology as
shown in Fig. 4. Common-gate devices are added between
mixing core and the output TIA stage. From mixing core
output it still sees low input impedance (1/gm), while the TIA
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sees very large output impedance (1/gds). Therefore, the noise filter uses tuned RC blocks, with both R and C tunable by
contribution from opamp of TIA stage can be mitigated means of digitally controlled circuit. The block diagram of the
significantly. baseband filter is shown in Fig. 5

D. Frequency synthesizer
LO- Ib_lo Ib_hi
In this receiver a fractional-N PLL is employed to generate
Cpar Vb the LO frequency. The output the VCO is divided by 2 to
IF-
generate the LO frequency. Due to the large jammer at
+135MHz offset, the phase noise requirement of the LO path
From LNA LO+ Ib_lo Ib_hi To TIA is very stringent in the high power mode and excessive current
is needed to reduce the noise floor. We select a different LO
IF+ path when the jammer power is low and the receiver is in the
Cpar Vb
low-linearity mode.
Figure 4, Current tunable passive mixer topology
V. EXPERIMENTAL RESULTS
More importantly, we can also remove the Gm-stage in the
RF side of the mixing core. This is due to the low input The SGPS receiver is implemented in a 0.18-m RFCMOS
impedance the CG devices provide. Large current process and a die micrograph is shown in Fig. 6. The LNA
consumption is compulsory to achieve the same gm in the RF input devices and mixer core devices are placed in the deep N-
side compared with gm in the IF side. At low frequency, we well to provide good isolation from the substrate noise
can increase device size instead of current consumption to coupling. Furthermore, guard rings are placed between
achieve same gm. Also, it is much easier to tune the mixer synthesizer and signal path circuits with dedicated ground.
current based on the different linearity requirement.

C. TIA, IF mixer and baseband filter

The receiver baseband consists of a complex TIA filter, an
IF down conversion mixer filters and a biquad. The filter
following the mixer implemented a trans-impedance transfer
function taking the current-mode signals from the mixer
output nodes and converting them to voltages at the filter
output. The complex filter characteristics help to improve the
image rejection ratio and suppress the IM2 component due to
the transmitter jammer. Then the signal is passing through an
Figure 6: sGPS receiver chip micrograph.
IF down conversion block, which consists of an IF LO
generation block, a complex passive mixer and a buffer
Figure 7 shows the measured spectrum at the baseband
amplifier, before reaching the biquad. The overall GPS signal
output when a -110dBm CW signal at the GPS L1 band is
is filtered by a third-order Chebyshev low-pass filter with a 3-
injected at the LNA input. It reveals the filter response and the
dB bandwidth of around 1MHz. Each stage of the
3-dB bandwidth is about 1MHz.
DCOC
SBI
DAC
IF I MXR

1st Pole I Filter Biquad I Filter

LO_I
BBA DRV
LO_Q

TCXO
LO_I
Div by3
LO_Q

LO_I
BBA DRV
LO_Q

1st Pole Q Filter Biquad I Filter

IF Q MXR
DCOC SBI
DAC
Figure 7: CW signal response at baseband output.
Figure 5, Baseband filter block diagram Figure 8 shows the NF and Gain changes with the AWS
band jammer power. When the jammer power is -17dBm at

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the LNA input, the gain compression is about 0.8dB, while the Teodoro Valenzuela Saquelare, Nianci Wang for their testing
NF will degrade 0.5dB from its small signal measurement support, and Cormac Conroy for his input and assistance. We
results. The maximum transmitter leakage power is -13dBm at are further indebted to Babak Motamedi of the Failure
LNA input. Analytical group for assistance with FIB support.

Gain and NF versus AWS Tx Jammer

REFERENCES
84.5 11 [1] D. Sahu et al., A 90nm CMOS Single-Chip GPS Receiver with
84 10 5dBm Out-of-Band IIP3 2.dB NF, in IEEE Int. Solid-State Circuits
83.5 9
Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005.
[2] G. Montagna et al., A 35-mW 3.6-mm2 Fully Integrated 0.18-m
83 8
Gain (dB)

CMOS GPS Radio, IEEE Journal of Solid-State Circuits., vol. 38, No.7

NF (dB)
82.5 7
pp. 1163-1171, July 2003.
82 6
[3] F. Behbahani et al., A Fully Integrated Low-IF CMOS GPS Radio
81.5 5 With On-Chip Analog Image Rejection, IEEE Journal of Solid-State
Gain NF (dB)
81 4 Circuits., vol. 37, No.12 pp. 1721-1727, December 2002.
80.5 3 [4] M. Steyaert et al., A Fully-Integrated GPS Receiver Front-End with
80 2 40mW Power Consumption, in IEEE Int. Solid-State Circuits Conf.
-60 -50 -40 -30 -20 -10 0 (ISSCC) Dig. Tech. Papers, Feb. 2002.
Jammer Power (dBm) [5] J. Crols et al., Low-IF Topologies for High-Performance Analog
Front Ends of Fully Integrated Receivers, IEEE Trans. On Circuits and
Figure 8: Gain and NF change with Tx jammer power. Systems II, vol. 45, No.3 pp. 269-282, March 1998.
[6] D. Shaeffer et al., A 115-mW, 0.5-m CMOS GPS Receiver with
Wide Dynamic-Range Active Filters, IEEE Journal of Solid-State
The measured performances for the simultaneous GPS Circuits, vol. 33, No.12 pp. 2219-2231, December 1998.
receiver are summarized in Table I.

Table I
Measured performance summary.
Signal path
Noise Figure 2.0dB
Voltage Gain >80dB
S11 -10dB
IRR -26.8dB
RSB -50.1dB
Max out-of-band Tx blocker -13dBm
Max IIP3 (out-of-band) +6dBm
2-dB Gain Compression -10dBm
LO leakage -96.5dBm
VCO leakage -58.5dBm
Synthesizer
Phase noise at 1MHz offset -132dBc/Hz
Integrated phase noise -31dBc
(100Hz 1MHz)
Full receiver
Power (using 36.7 mA @ high linearity mode
SMPS) 27.4 mA @ low linearity mode

VI. CONCLUSION
This paper describes the design and implementation of a
low-IF simultaneous GPS receiver integrated with
WCDMA/CDMA2000/GSM transceiver. The front-end
current can be dynamically adjusted based on the jammer
power to achieve difference linearity performance. Field test
reveals performance compliance in the complex EM
environment.

ACKNOWLEDGEMENT
The authors would like to thank Tim Nacita for his layout
support, Dale Carmichael, Todd DuBois, Craig Lilja and

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