VHDL/Verilog Simulation Tutorial

The following Cadence CAD tools will be used in this tutorial:

NC-Sim for simulation.
Sim Vision for visualization.

Computer Account Setup

Please revisit Unix Tutorial before doing this new tutorial.

If you use Exceed from a PC you need to take care of this extra issue. The Cadence
software has an annoying screen/refresh problem when run on a PC via Exceed. You
need to do the following in order to solve the problem:
Under Xconfig -> Performance.

1. Enable Save Unders

2. Enable Change Maximum Backing Store to Always
3. Alter Default Backing Store to When Mapped
4. Alter Minimum Backing Store to When Mapped

You have to exit Exceed for the changes to take effect.

SETTING YOUR ENVIRONMENT UP FOR CADENCE AND ADDITIONAL

TOOLS

In order to setup your environment to run Cadence applications you need to open an
xterm window and type (EVERY TIME you login and in each window you want to
run a Cadence tool)
. cadence2009

this script modifies your environment (sets PATH and exports variables). To see your
current environment type the following at the prompt:
set

Running the Cadence Simulation tools

Now you should be able to run the Cadence tools. Never run Cadence from your root
directory, it creates many extra files that will clutter your root. Instead please create a
directory (e.g. cadence) and another directory for the design (e.g. tutorial) and finally
one for the HDL files (e.g. HDL) by typing:
mkdir cadence
cd cadence
mkdir tutorial
cd tutorial
mkdir HDL

For this tutorial you will need a few extra files, please download the following files in
the HDL directory:
accu.cmd
accu.v
accu_test.v

from:
http://www.ee.virginia.edu/~mrs8n/soc/files

From the tutorial directory type:

nclaunch &

The command nclaunch & starts NCSim in the background and you should get the
NCLaunch startup window:
Please click on Multiple Step and you should now get the main NCLauch window:
The window has four areas:
 Menu Bar (top)
File Browser (left)
Library Browser (right)
Console Window (bottom)

Please try to familiarize yourself with the main window, click on the menus, etc. For
more information on the various Cadence tools I encourage you to read the
corresponding user manuals. You can get to the manuals by pressing Help ->
NCLaunch User Guide on the right of the Menu Bar. A Web Browser should pop-up.
There are also tutorials available Help -> Tutorials. Spend some time browsing the
manuals to understand what is available (a lot!). During the semester you will have to
look for information in the on-line manuals to complement the (limited) info given by
these tutorials. Actually you can think of this tutorial as a subset of the one available
under help!

Now we need to set the work directory and create a work library (to contain your
circuits) so go to File -> Set Design Directory from the File menu of the Menu Bar.
First set the design directory to thetutorial directory that you just created (this should
be automatic if you started NCLaunch from the tutorial directory as described here):
then click on Create cds.lib File and click Save (you should only need to do this once
when you run the tool for the first time)
and finally click OK to Include default libraries
Finally, making sure that worklib has appeared for Work Library click OK on the Set
Design Directory pop-up window. Please notice that the Library Browser window
(right side) of NCLaunch has become populated now.

There are 3 steps that we need to perform now (remember we chose multistep):

Compile
Elaborate
Simulate

In order to compile you first need to select the various files in the File Browser (left
side) by clicking on the mouse left button (simultaneously press on shift for multiple
selections), then click on the corresponding buttons in the Menu Bar (in this case the
VLOG button) or explicitly go to Tools -> Verilog Compiler.... Now is actually a
good time to look at these files as well, you can do that for example by clicking on the
file, then going to File -> Edit, you should see the actual file in a text editor:
Close the text editor without modifying the file. Now compile
both accu.v and accu_test.v in that order.

Caution! The order of compilation is important in case there are dependencies

among the files. In the case the testbench is the "top" file and needs to be
compiled last!

Make sure there are no errors in the Console Window (always keep an eye on that
window for errors and warnings).

In order to elaborate first click on the + in front of the worklib on the Library Browser
window in order to see it's contents:
Now select the top file under worklib (stimulus) then click on the Elaborate button in
the Menu (immediately to the right of the VLOG button), or go to Tools ->
Elaborator....
Finally we can simulate! Click on the + sign in front of the Snapshots library to
expand its contents, then select worklib.stimulus:module and click on Simulate (next
to the right of elaborate) or go to Tools -> Simulator.... This should launch the
Simvision Design Browser and Console windows:
Click on stimulus on the left window, then on the Waveform button (the one that looks
like a set of white digital waveforms on a black background, sixth from the right), this
should open a new Waveform window. Now press on the Run button on the Design
Browser window (first on the left, looks like a Play button on a CD player). This
should now display the signal waveforms that validate correct functionality for the
accumulator (increment by one for every clock cycle):

Congratulations, this is the end of the Simulation Tutorial.

 RTL Logic Synthesis Tutorial
The following Cadence CAD tools will be used in this tutorial:
RTL Compiler for logic synthesis.

Computer Account Setup

Please revisit Simulation Tutorial before doing this new tutorial.

In order to setup your environment to run Cadence applications you need to open an
xterm window and type:
. cadence2009

Running the Cadence logic synthesis tools

Now you should be able to run the Cadence tools. Never run Cadence from your root
directory, it creates many extra files that will clutter your root. Instead please create a
directory (e.g. cadence, you should have this already) and another directory for the
design (e.g. tutorial, should have it) and finally one for the synthesis files (e.g.
synthesis):
cd cadence
cd tutorial
mkdir synthesis
cd synthesis

For this tutorial you will need a few extra files, please download the following file in
the synthesis directory (this is a script that you will have to edit for other designs):
rtl.tcl

from:
http://www.ee.virginia.edu/~mrs8n/soc/files

The command rc -gui (no &) starts RTL Compiler version 8.1 (2009) in the
foreground and you should get the rc startup window:
The window has three areas:

Menu Bar (top)

File Browser (left)
Schematic Browser (right)

Unlike other GUI interfaces, the console this time is the initial window from which
you launched rc (that's why it had to be launched in the foreground). Please try to
familiarize yourself with the main window, click on the menus, etc. For more
information on the various Cadence tools I encourage you to read the corresponding
user manuals. You can get to the manuals by pressing Help -> Reference Manuals on
the right of the Menu Bar. Spend some time browsing the manuals to understand what
is available (a lot!). During the semester you will have to look for information in the
on-line manuals to complement the (limited) info given by these tutorials. Actually
you can think of this tutorial as a subset of the one available under help!

Now we need to run the script that you copied from the files directory so go to File ->
Source Script from the File menu of the Menu Bar. Click on rtl.tcl, then OK:

Your console should run for a brief time and you should get a success message:
Now your GUI window should show a netlist on the right side, and if you click on
HDL, the source code on the left side:

Try some of the menu options, for example you can see what library standard cells
were used in the synthesized netlist by going to Report -> Netlist -> Mapped
Gates...:
Another important tool is the design browser, go to Tools -> Object Browser...
Finally, you can close the GUI by going to File -> Exit and you can now analyze the
result of the synthesis in the file accu_synth.v that you can use for simulating the
netlist and for subsequent place and route using Encounter:
Congratulations, this is the end of the Logic Synthesis Tutorial.
 Backend Design Tutorial
The following Cadence CAD tools will be used in this tutorial:
SOC Encounter for backend design (floorplanning, place and route, power and
clock distribution).

Computer Account Setup

You may want to revisit Simulation Tutorial and Logic Synthesis Tutorial before
doing this new tutorial.

In order to setup your environment to run Cadence applications you need to open a
terminal window and type:
. cadence2009

Running the Cadence backend tool

Now you should be able to run the Cadence tools. Never run Cadence from your root
directory, it creates many extra files that will clutter your root. Instead please create a
directory (e.g. cadence, you should have this already) and another directory for the
design (e.g. tutorial, should have it), link the library files to your directory such that it
will be easier to navigate to them, and finally one for the encounter files (e.g.
encounter):
cd cadence
cd tutorial
ln -s var/home/hplp/osuflow/osu_stdcells/lib/tsmc018/lib .
mkdir encounter
cd encounter

For this tutorial you will need a few extra files, all the results of the previous tutorials,
make sure you have those.

From the encounter directory type:

encounter
The command encounter (no &) starts SOC Encounter in the foreground and you
should get the encounter startup window:
The window has three main areas:

Menu Bar (top)

Select Bar (right)
Display Area (middle)

Please try to familiarize yourself with the main window, click on the menus, on the
Toolbar widgets, etc. For more information on the various Cadence tools I encourage
you to read the corresponding manuals. You can get to the menu reference manual for
Encounter by pressing Help on the right of the Menu Bar. Spend some time browsing
the manuals to understand what is available (a lot!). During the semester you will
have to look for information in the on-line manuals to complement the (limited) info
given by these tutorials. Actually you can think of this tutorial as a tiny subset of the
one available under help!

Now we can start using Encounter. First we need to import the synthesized netlist (the
result of RTL synthesis with RTL Compiler). Click on Design -> Import Design and
the Design Import window should pop-up (as an aside, it seems you can also import
RTL directly, I assume this means you can do RTL synthesis in Encounter directly
without using RC, it would be interesting to try this and see how it works). Now you
need to fill in the Verilog netlist (use the browser button on the right to navigate to
your synthesized netlist, in my case accu_synth.v in ../synthesis, make sure you click
on Add, then on Close
Then click on Auto Assign for the Top Cell assignment. Then we need to specify the
physical definitions for the library, do that by clicking on the navigate button on the
right of the LEF Files entry which should pop-up the LEF Files window. Navigate to
the lib directory (that you just linked into your tutorial directory, in my case at ../lib)
then click on osu018_stdcells.lef, and finally on Add, then on Close

Then we need to specify the timing definitions for the library, do that by clicking on
the navigate button on the right of the Common Timing Libraries entry which should
pop-up the Timing Files window (note that more advanced libraries will have Max
Timing and Min Timing Libraries in order to be able to do "corner analysis", not just
nominal analysis). Navigate to the lib directory (that you just linked into your tutorial
directory, in my case at ../lib) then click on osu018_stdcells.tlf, and finally on Add,
then on Close
Normally, if this was a full chip design, we would also have to specify the I/O pad
information now by the IO Assignment File, but for now we will not use I/O pads.
Your Design Import pop-up window should look like this now
Now click on the Advanced tab and choose Power from the left window, fill vdd for
Power Nets and gnd for Ground Nets (out of curiosity you can check that indeed these
are the names of the power and gnd nets in your Verilog netlist by opening the file in a
text editor).
((Now click on the IPO/CTS tab and fill buf for Buffer Name/Footprint and inv for
Inverter Name/Footprint (out of curiosity you can check that indeed these are the
footprint names by examining the .tlf file in the lib directory). Also click on Generate
Footprint Based on Functional Equivalence.))
Finally click on OK in your Design Import pop-up window. Get familiar with some of
the widgets, for example the Design Browser widget (the 7th from the right, top row)
lets you see the design hierarchy, etc.
Now we need to specify floorplaning information. Since our design is simple and flat
there is not much that needs to be done, but in general now is the time to decide how
the big blocks that make up the design should be placed with respect to each other.
Click on Floorplan -> Specify Floorplan and leave all defaults except change to
100.00 (default is 0.00) the Core to Left, Core to Right, Core to Top and Core to
Bottom.
Click on Apply and the floorplan should change to reflect the 100 micron periphery
around the core.
Now you can also play with the aspect ratio on the Specify floorplan window, change
that to 0.5, click Apply, then to 2, click Apply again, finally back to 1 and click Apply.
Note how the number of rows in your floorplan changes from 5 (for 1) to 7 (for 2) to 3
(for 0.5). It is a good idea to save your design from time to time by Design -> Save
Design As...

The next step is to create the power and ground connections, but first you have to
specify the nets. Click on Floorplan -> Connect Global Nets and then fill the pop-up
window connecting pin vdd to global net vdd, and pin gnd to global net gnd, making
sure the button Apply All is checked (need to do this one at a time by adding to list).
Click Apply, then Check (make sure there are no warnings here), then Close to close
the pop-up.
Now we can finally create the power distribution for our design. Click Power ->
Power Planning -> Add Rings. Choose metal 5 and metal 6 with the width and
spacing of 8 and 1 and with offset of 1, then click Apply, followed by Cancel.
Click Power -> Power Planning -> Add Stripes. Choose metal 6 with the width and
spacing of 8 and 1 and with X from left of 20, then click Apply, followed by Cancel.
Then, in order to route the rest of the power distribution click Route -> Special
Route, deselect Pad pins, then click Apply, followed by Cancel.

Now your floorplan should look like this.

It is time to place our cells, go to Place -> Standard Cells, click Mode, then deselect
Run Timing Driven Placement and Reorder Scan Connection then click Apply,
followed by Cancel.
Now, if you click on the Physical View widget (on the right of the second row of
the widget menu, right to the left of All Colors) you will see your placed design.
Finally we can also route our design, go to Route -> Trial Route... and click OK

And now your design should be also routed.

Since we don't have pads in our design the tools route the primary inputs and
outputs to the periphery of the floorplan such that they can in principle be
connected in a hierarchical fashion to other blocks.

Congratulations, this is the end of the first Backend Tutorial, in future tutorials
you will learn how to do clock tree synthesis, verify your design, power analysis,
timing analysis, and signal integrity.