PROGRAMMABLE LOGIC DEVICES (INTRODUCTION)

In many applications the PLD has replaced hard-wired fixed function logic device. Advantages of PLDs
over fixed function logic;

a) many logic circuits can be stuffed into a much smaller area with PLDs

b) logic designs can be readily changed without rewiring or replacing components

c) a PLD design can be implemented faster than using fixed-function ICs

There are 3 main types of programmable logic. These are, SPLD, CPLD, & FPGA.

SPLDs (Simple programmable logic devices) are the least complex form of PLDs. It replaces the
SSI & MSI devices. A typical package has 24 to 28 pins. Categories of SPLD include PAL
(Programmable Assay Logic), PROM (Programmable Read-Only Memory).
CPLDs (Complex Programmable Logic Devices) have much higher capacity than SPLDs. Density
2 64 SPLDs. CPLDs Come in 44-pin to 160 pin package
FPGAs (Field Programmable Gate Arrays) have the greatest logic capacity. Contains 64 to
1000s logic blocks. Two basic classes of FPGA;

- course grained has large logic blocks

- fine grained has smaller logic blocks.

FPGA packages range up to 1000 pins or more.

PLD Programming

A logic circuit design for a PLD is entered using schematic entry (e.g. logic gates, flip-flops) or
text-based entry using HDC like VHDL or both.

PROGRAMMABLE LOGIC DEVICES

All PLDs consists of programmable arrays, which is essentially a grid of conductors that form
rows & columns with fusible links at cross points. Arrays can be fixed or programmable. The links
can also be made from an anti-fuse which can be melted to form a contact. The PLDs consists of
AND and OR arrays.

CLASSIFICATION OF SPLD

FIGURE 1.

PROMS primarily used as addressable memory because of limitation imposed by fixed AND
gates

PLA developed to overcome some PROM limitations (also called FPLA)

PAL overcomes disadvantages of PLA such as delays due to additional fusible links resulting
from the two programmable arrays. PAL is a one-time programmable (OTP) logic device
implemented with TTL or ECL

GAL it is reprogrammable and uses ECMOS technology instead of bipolar technology & fusible
links.

PAL OPERATION

FIGURE 2

Some PALS provide I/O pins that can be programmed as either input or output. I/O symbol

TYPES OF PAL OUTPUT LOGIC

a) Combinational output - this output is used for a 50P function & is usually available as either
active low or active high output.

b) Combinational I/O this output is used when the output function must feed to be an input to
the array or to be used to make the I/O pin an input only.

c) Programmable polarity output this output is used for selecting the output function or its
complement by programming the XOR gate. Blow fuse for inversion or leave intact for non-
inversion. (see diagram below)

FIGURE 3

GAL OPERATION

FIGURE 4

The output logic macrocells (OLMC) contain the OR array & programmable output logic. A
typical GAL has 8 or more inputs to its AND array & 8 or more I/O from its OMLC.

The programmable array is essentially a grid of conductors forming rows & columns with
ECMOS cell at each intersection rather than a fuse as in a PAL.

Example: implement SOP expression, F= B + AB + B (see figure below). Each cell is

programmed as on or off. Each cell can be electrically erased & reprogrammed. A typical
ECMOS cell can retain its programmed state for 20 years or more. Note that the ECMOS cells
are off where a variable or its complement is not used in a given product term. The final output
from the OR gate is an SOP expression
FIGURE 5

COMPLEX PROGRAMMABLE LOGIC DEVICES

A CPLD consists of multiple groups of PAL/GAL like arrays with programmable

interconnections. Each PAL/GAL group is called logic array block (LAB). Each LAB contains several
PAL/GAL like arrays called macro cells. Each LAB can be interconnected with other LAB or
other I/O, using programmable interconnect array (PLA) to form large complex logic functions.
The CPLD is based on a SOP architecture, just like the PAL or GAL.

FIGURE 6

Each LAB contains 32 to several hundred macro cells. A typical macro cell has an AND array, a
product-term select matrix in OR gate & a programmable register section (see your text book for
further details). A registered output is obtained from the register (flip-flop) output.

The PIA consists of conductors that can run through the CPLD chip & to which connections from
the macro cells in each LAB can be made. PIA connects macro cells in the same LAB, macro cells
across LABs or other I/O.

Most CPLDs, use ECMOS technology to make connections. In ECMOS, a transistor between two
lines is programmed to the on state to form a connection & in the off state for no connection.

FIGURE 7

STRUCTURE OF FPGAs

FIGURE 8

FPGA Basic block diagram

An FPGA contains an array of logic blocks in a large distributed interconnection structure that
dominates the entire chip. Its architecture is based on a LUX rather than SOP AND/OR arrays as
CPLDs are.

Each logic block consists several logic elements. Inside each element we find a LUT, associated
logic and a flip flop. The LUT performs combinational functions. Registered functions are
obtained from the flip-flop output. (Some FPGAs use multiplexers instead of LUTs)

The FPGA uses either SRAM or antifuse methods to provide interconnections between logic
blocks.

The LUT used in FPGA is a memory device that can be programmed to perform logic functions. It
replaces the AND/OR array logic in a CPLD. When any one of the product terms of a SOP
function appears on the LUT inputs, the corresponding memory cell storing a 1 is selected and a
HIGH appears on the output. For any product terms that are not part of the SOP function, the
LUT output is LOW.

Example

An 8x2 LUT programmed as a full adder.

The sum & carry out, count expressions for a full-adder are given as follows. , F= B + AB + B

= (A+B) + = B + B += B

Ccont =

FIGURE 9

LUT

COMBINATIONAL PLDs

PLA combinational 2-level AND-OR device that can be programmed to realize any SOP logic
expression. Its limitations are; no. of inputs (n), no. of outputs (m), no. of product terms (p).

An n x m PLA with p product terms contains p 2-inputs AND gates & m p-input OR gates.

FIGURE 10

Potential connections in the array are indicated by X. The device blows off connections not
required.

PAL it has a fixed OR array, AND gate inputs cant be shared (if a product term is needed by 2
Or gates, it must be generated twice), it is enabled by a dedicated programmable AND gate,
some output pins are I/O.

GENERIC ARRAY LOGIC DEVICES

It emulates the AND-OR, flip-flop 7 output structure of any of a variety of combinational or

sequential PAL devices. It can be erased electrically & reprogrammed.

FIGURE 11

Input x of XOR gate is pulled up to logic 1 but also connected to ground via a fuse. If the fuse is
intact, the output is not inverted. If the fuse is blown, the XOR inverts the output.

BIPOLAR PLD ccts

FIGURE 12
Each potential connection is made by a diode & a fusible link. By applying a special input
patterns to the device, its possible to select individual links & vaporize them by applying high
voltage (10-30v).

Applying a high voltage at floating gate accumulates a positive charge which prevents transistor
from turning on.

CMOS PLD ccts

FIGURE 13

Each potential connection is made out of an n-channel transistor with a reprogrammable

connection.

Input low transistor on

Input high transistor off

Thus an inverted AND (i.e NOR) is obtained.

FIGURE 14

Applying a high voltage at floating gate accumulates a ve charge which prevents transistors
from -------- on erasable programmable logic device (EPLG) uses UV light or electronic means to
erase links..active high AND