Вы находитесь на странице: 1из 61
A B C D E Compal Confidential Model Name : JE50-HR/SJV50-HR Compal Project Name :
A
B
C
D
E
Compal Confidential
Model Name : JE50-HR/SJV50-HR
Compal Project Name : P5WE0/P5WS0
1
1
File Name : LA-6902P
Compal Confidential
2
2
JE50-HR/SJV50-HR(P5WE0/P5WS0) M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P GS/GV
2010-10-19
3
3
REV:0.1
4
4
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2010/10/15
2010/10/15
2010/10/15
2011/10/15
2011/10/15
2011/10/15
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Cover Page
Cover Page
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
JE50-HR/SJV50-HR M/B Schematics 0.4
JE50-HR/SJV50-HR M/B Schematics 0.4
JE50-HR/SJV50-HR M/B Schematics 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Sheet
Sheet
Sheet
1
1
1
of
of
of
61
61
61
A
B
C
D
E
A B C D E Fan Control page 42 1 1 PEG(DIS) 100MHz PCI-E 2.0x16
A
B
C
D
E
Fan Control
page 42
1
1
PEG(DIS)
100MHz
PCI-E 2.0x16
5GT/s PER LANE
Intel
Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X2
Nvidia
133MHz
Dual Channel
Sandy Bridge
BANK 0, 1, 2, 3
page 11,12
N12P GS/GV
Processor
1.5V DDRIII 1066/1333
page22~30
rPGA989
page 4~10
HDMI(DIS)
CRT(DIS)
LVDS(DIS)
USB 2.0 conn x2
Bluetooth
CMOS Camera
3G connector
FDI x8
DMI x4
Conn
USB port 9,12 on 3G/B
HDMI Conn.
CRT Conn.
LVDS Conn.
USB port 0,1 on
USB/B
USB port 13
USB port 10
100MHz
100MHz
page 38
page 38
page 31
page 37
page 33
page 32
page 31
2.7GT/s
1GB/s x4
USBx14
3.3V 48MHz
2
2
LVDS(UMA/OPTIMUS)
Intel
CRT(UMA/OPTIMUS)
HD Audio
3.3V 24MHz
Cougar Point-M
TMDS(UMA/OPTIMUS)
PCH
HDA Codec
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
100MHz
989pin BGA
ALC271X/277X
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
port 2,3
port 1
100MHz
page 41
port 5
SPI
page 13~21
USB 3.0 conn x1
NEC uPD720200AF1
with USB3.0 Conn.
LAN(GbE) &
MINI Card x2
Card Reader
WLAN, WWAN
BCM57785
USB port 12,13
SPI ROM x1
Int. Speaker
Phone Jack x 2
page 37
page 35,36
page 45
page 13
port 0,1
port 2
page 41
page 41
SATA HDD
SATA CDROM
Card Reader
RJ45
Conn.
Conn.
LPC BUS
3
3
page 34
page 34
page 36
Conn. page 35,36
33MHz
ENE KB930
Sub-board
page 39
LS-6901P
RTC CKT.
USB 2.0/B 2Port
USB Port0,1
page 38
LF-6901P
page 13
Touch Pad
Int.KBD
FPC for USB3.0
page 40
page 40
LS-6904P
page 38
Power On/Off CKT.
USB 3.0 /B
1 port as USB3.0
page 40
1 port as USB2.0
page 38
BIOS ROM
page 40
DC/DC Interface CKT.
LS-6903P
page 43,44
4
4
3G/B
page 37
Power Circuit DC/DC
LS-6902P + LS-6905P
page 46~59
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
2010/10/15
2010/10/15
2010/10/15
2011/10/15
2011/10/15
2011/10/15
Title
Title
Title
PWR/B
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Block Diagrams
Block Diagrams
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
page 40
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.4
0.4
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
JE50-HR/SJV50-HR M/B Schematics
JE50-HR/SJV50-HR M/B Schematics
JE50-HR/SJV50-HR M/B Schematics
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Sheet
Sheet
Sheet
2
2
2
of
of
of
61
61
61
A
B
C
D
E
A B C D E Voltage Rails SIGNAL STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V
A
B
C
D
E
Voltage Rails
SIGNAL
STATE
SLP_S1#
SLP_S3#
SLP_S4#
SLP_S5#
+VALW
+V
+VS
Clock
Power Plane
Description
S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
Full ON
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
BATT+
Battery power supply (12.6V)
N/A
N/A
N/A
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
1
1
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
+VGA_CORE
Core voltage for GPU
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
+VGFX_CORE
Core voltage for UMA graphic
ON
OFF
OFF
+0.75VS
+0.75VP to +0.75VS switched power rail for DDR terminator
ON
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
+1.05VSDGPU
+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
ON
OFF
OFF
+1.05VS_VTT
+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
ON
OFF
OFF
Board ID / SKU ID Table for AD channel
+1.05VS_PCH
+1.05VS_VCCP to +1.05VS_PCH power for PCH
ON
OFF
OFF
+1.5V
+1.5VP to +1.5V power rail for DDRIII
ON
ON
OFF
Vcc
3.3V +/- 5%
+1.5VS
+1.5V to +1.5VS switched power rail
ON
OFF
OFF
Ra/Rc/Re
100K +/- 5%
+1.5VSDGPU
+1.5VS to +1.5VSDGPU switched power rail for GPU
ON
OFF
OFF
Board ID
Rb / Rd / Rf
V
min
V
typ
AD_BID
AD_BID
V AD_BID max
+1.8VS
(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
ON
OFF
OFF
0
0
0 V
0 V
0 V
EVT
+1.8VSDGPU
+1.8VS to +1.8VSDGPU switched power rail for GPU
ON
OFF
OFF
1
8.2K +/- 5%
0.216
V
0.250
V
0.289
V
EVT2
+3VALW
+3VALW always on power rail
ON
ON
ON*
2
18K +/- 5%
0.436
V
0.503
V
0.538
V
DVT
+3VALW_EC
+3VALW always to KBC
ON
ON
ON*
3
33K +/- 5%
0.712
V
0.819
V
0.875
V
PVT
+3V_LAN
+3VALW to +3V_LAN power rail for LAN
ON
ON
ON*
4
56K +/- 5%
1.036
V
1.185
V
1.264
V
Pre-MP
+3VALW_PCH
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
ON
ON
ON*
5
100K +/- 5%
1.453
V
1.650
V
1.759
V
2
2
+3VS
+3VALW to +3VS power rail
ON
OFF
OFF
6
200K +/- 5%
1.935
V
2.200
V
2.341
V
+5VALW
+5VALWP to +5VALW power rail
ON
ON
ON*
7
NC
2.500
V
3.300
V
3.300
V
+5VALW_PCH
+5VALW to +5VALW_PCH power rail for PCH (Short resister)
ON
ON
ON*
+5VS
+5VALW to +5VS switched power rail
ON
OFF
OFF
BOARD ID Table
BTO Option Table
+VSB
+VSBP to +VSB always on power rail for sequence control
ON
ON
ON*
BTO Item
BOM Structure
+RTCVCC
RTC power
ON
ON
ON
Board ID
PCB Revision
UMA Only
UMAO@
0
0.1
UMA with OPTIMUS
UMA@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
1
0.2
Dis with OPTIMUS
DIS@
2
EC SM Bus1 address
EC SM Bus2 address
0.3
DIS Only
DISO@
3
0.4
OPTIMUS
OPT@
Device
Address
Device
Address
4
1.0
Non-OPTIMUS
NOPT@
Smart Battery
0001 011X b
5
3G
3G@
6
Blue Tooth
BT@
7
USB2.0
USB20@
PCH SM Bus address
USB3.0
USB30@
VRAM
X76@
3
3
Device
Address
USB Port Table
Connector
CONN@
Clock Generator (9LVS3199AKLFT,
1101 0010b
Unpop
@
RTM890N-631-VB-GRT)
3 External
USB 2.0
USB 1.1
Port
LAN Chip A0 version
A0@
DDR DIMM0
1001 000Xb
USB Port
LAN Chip B0 version
B0@
DDR DIMM2
1001 010Xb
0
USB/B (Right Side)
UHCI0
N12P-GS
GS@
1
USB/B (Right Side)
3G & BT & USB30 & USB20 Config
N12P-GV
GV@
2
USB3.0 colay USB2.0 Conn.
3G SKU: 3G@
BT SKU: BT@
USB30 SKU: USB30@
USB20 SKU: USB20@
OPTMIUS SKU: OPT@
Non-OPTMIUS SKU: NOPT@
UHCI1
3
USB/B Colay USB3.0
EHCI1
4
LAN Chip A0 version: A0@
N12P-GS: GS@
UHCI2
5
LAN chip B0 Version: B0@
BOM Config
N12P-GV: GV@
6
UHCI3
7
UMA Only:
BT@/3G@/USB30@/UMA@/UMAO@/NOPT@/A0@
8
Mini Card 1(WLAN)
OPTIMUS(N12P-GS):
BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@/GS@
UHCI4
9
3G/B(WWAN)
DIS Only(N12P-GS): BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@/GS@
10
Camera
OPTIMUS(N12P-GV): BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@/GV@
EHCI2
UHCI5
11
Mini Card 2(Reserved)
DIS Only(N12P-GV):
BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@/GV@
4
4
12
3G/B(SIM Card)
VRAM P/N :
UHCI6
13
BlueTooth
64*16
Samsung : SA000035700
Hynix : SA000032400/SA0000324C0
128*16
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Samsung : SA00003MQ40
Hynix : SA00003VS00
2010/10/15
2010/10/15
2010/10/15
2011/10/15
2011/10/15
2011/10/15
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Notes List
Notes List
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.4
0.4
JE50-HR/SJV50-HR M/B Schematics
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
JE50-HR/SJV50-HR M/B Schematics
JE50-HR/SJV50-HR M/B Schematics
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Sheet
Sheet
Sheet
3
3
3
of
of
of
61
61
61
A
B
C
D
E
5 4 3 2 1 +1.05VS_VTT ZZZ ZZZ DA60000KC00 DA60000KC00 R517 R517 24.9_0402_1% 24.9_0402_1% JCPU1A
5
4
3
2
1
+1.05VS_VTT
ZZZ
ZZZ
DA60000KC00
DA60000KC00
R517 R517
24.9_0402_1% 24.9_0402_1%
JCPU1A
JCPU1A
PEG_COMP
PEG_ICOMPI and PEG_RCOMPO signals should be
shorted and routed,
max length = 500 mils,trace width=4mils
PEG_ICOMPO signals should be routed with - max
length = 500 mils,trace width=12mils
spacing =15mils
D
D
J22
PEG_ICOMPI
J21
PEG_ICOMPO
15
DMI_CRX_PTX_N0
B27
H22
DMI_RX#[0]
PEG_RCOMPO
15
DMI_CRX_PTX_N1
B25
DMI_RX#[1]
15
DMI_CRX_PTX_N2
A25
DMI_RX#[2]
PEG_GTX_C_HRX_N15
PEG_GTX_HRX_N15
15
DMI_CRX_PTX_N3
B24
C46
C46
DIS@
K33
1
2
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
DMI_RX#[3]
PEG_RX#[0]
PEG_GTX_C_HRX_N14
C49
C49
2
DIS@
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N14
1
0.22U_0402_10V6K
M35
PEG_RX#[1]
PEG_GTX_C_HRX_N13
PEG_GTX_HRX_N13
C51
C51
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
DMI_CRX_PTX_P0
1 2
B28
L34
DMI_RX[0]
PEG_RX#[2]
PEG_GTX_C_HRX_N12
PEG_GTX_HRX_N12
C53
C53
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
DMI_CRX_PTX_P1
B26
J35
DMI_RX[1]
PEG_RX#[3]
PEG_GTX_C_HRX_N11
PEG_GTX_HRX_N11
C60
C60
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
DMI_CRX_PTX_P2
A24
J32
1 2
PEG_GTX_HRX_N[0
15]
22
DMI_RX[2]
PEG_RX#[4]
PEG_GTX_C_HRX_N10
PEG_GTX_HRX_N10
C71
C71
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
DMI_CRX_PTX_P3
B23
H34
PEG_GTX_HRX_P[0
15]
22
DMI_RX[3]
PEG_RX#[5]
PEG_GTX_C_HRX_N9
PEG_GTX_HRX_N9
C75
C75
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
H31
PEG_RX#[6]
PEG_GTX_C_HRX_N8
PEG_GTX_HRX_N8
C82
C82
15
DMI_CTX_PRX_N0
G21
G33
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_HTX_C_GRX_N[0
15]
22
DMI_TX#[0]
PEG_RX#[7]
PEG_GTX_C_HRX_N7
PEG_GTX_HRX_N7
C92
C92
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
DMI_CTX_PRX_N1
E22
G30
PEG_HTX_C_GRX_P[0
15]
22
DMI_TX#[1]
PEG_RX#[8]
PEG_GTX_C_HRX_N6
PEG_GTX_HRX_N6
C93
C93
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
DMI_CTX_PRX_N2
F21
F35
DMI_TX#[2]
PEG_RX#[9]
PEG_GTX_C_HRX_N5
PEG_GTX_HRX_N5
15
DMI_CTX_PRX_N3
C102
C102
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
D21
E34
1
DMI_TX#[3]
PEG_GTX_C_HRX_N4
PEG_GTX_HRX_N4
PEG_RX#[10]
C111
C111
E32
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_C_HRX_N3
PEG_GTX_HRX_N3
PEG_RX#[11]
C113
C113
1
0.22U_0402_10V6K
0.22U_0402_10V6K
15
DMI_CTX_PRX_P0
2
DIS@
DIS@
G22
D33
PEG_GTX_C_HRX_N2
PEG_GTX_HRX_N2
DMI_TX[0]
PEG_RX#[12]
15
DMI_CTX_PRX_P1
D22
D31
C125
C125
PEG_GTX_C_HRX_N1
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_N1
DMI_TX[1]
PEG_RX#[13]
C129
C129
15
DMI_CTX_PRX_P2
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
F20
B33
PEG_GTX_C_HRX_N0
PEG_GTX_HRX_N0
DMI_TX[2]
PEG_RX#[14]
C144
C144
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
DMI_CTX_PRX_P3
C21
C32
DMI_TX[3]
PEG_RX#[15]
PEG_GTX_C_HRX_P15
PEG_GTX_HRX_P15
C47
C47
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
J33
PEG_GTX_C_HRX_P14
PEG_GTX_HRX_P14
PEG_RX[0]
C50
C50
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
L35
PEG_GTX_C_HRX_P13
PEG_GTX_HRX_P13
PEG_RX[1]
C52
C52
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
K34
PEG_GTX_C_HRX_P12
PEG_GTX_HRX_P12
PEG_RX[2]
C56
C56
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
FDI_CTX_PRX_N0
A21
H35
PEG_GTX_C_HRX_P11
PEG_GTX_HRX_P11
FDI0_TX#[0]
PEG_RX[3]
C66
C66
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
FDI_CTX_PRX_N1
H19
H32
PEG_GTX_C_HRX_P10
PEG_GTX_HRX_P10
FDI0_TX#[1]
PEG_RX[4]
15
FDI_CTX_PRX_N2
E19
G34
PEG_GTX_C_HRX_P9
C68
C68
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_GTX_HRX_P9
FDI0_TX#[2]
PEG_RX[5]
15
FDI_CTX_PRX_N3
C81
C81
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
C
F18
G31
1
2
PEG_GTX_C_HRX_P8
PEG_GTX_HRX_P8
C
FDI0_TX#[3]
PEG_RX[6]
C86
C86
1
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
FDI_CTX_PRX_N4
2
B21
F33
PEG_GTX_C_HRX_P7
PEG_GTX_HRX_P7
FDI1_TX#[0]
PEG_RX[7]
15
FDI_CTX_PRX_N5
C89
C89
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
C20
F30
PEG_GTX_C_HRX_P6
PEG_GTX_HRX_P6
FDI1_TX#[1]
PEG_RX[8]
C100
C100
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
FDI_CTX_PRX_N6
D18
E35
PEG_GTX_C_HRX_P5
PEG_GTX_HRX_P5
FDI1_TX#[2]
PEG_RX[9]
15
FDI_CTX_PRX_N7
C105
C105
0.22U_0402_10V6K
0.22U_0402_10V6K
E17
1
2
DIS@
DIS@
E33
PEG_GTX_C_HRX_P4
PEG_GTX_HRX_P4
FDI1_TX#[3]
PEG_RX[10]
C106
C106
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
F32
PEG_GTX_C_HRX_P3
PEG_GTX_HRX_P3
PEG_RX[11]
C117
C117
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
D34
PEG_GTX_C_HRX_P2
PEG_GTX_HRX_P2
PEG_RX[12]
15
FDI_CTX_PRX_P0
C119
C119
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
A22
E31
PEG_GTX_C_HRX_P1
1
2
PEG_GTX_HRX_P1
FDI0_TX[0]
PEG_RX[13]
15
FDI_CTX_PRX_P1
C135
C135
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
G19
1
2
DIS@
C33
PEG_GTX_C_HRX_P0
PEG_GTX_HRX_P0
FDI0_TX[1]
15
FDI_CTX_PRX_P2
PEG_RX[14]
C138
C138
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
E20
B32
FDI0_TX[2]
15
FDI_CTX_PRX_P3
PEG_RX[15]
G18
PEG_HTX_GRX_N15
PEG_HTX_C_GRX_N15
FDI0_TX[3]
15
FDI_CTX_PRX_P4
C516
C516
B20
PEG_HTX_GRX_N14
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
M29
PEG_HTX_C_GRX_N14
FDI1_TX[0]
C520
C520
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
FDI_CTX_PRX_P5
PEG_TX#[0]
C19
M32
PEG_HTX_GRX_N13
PEG_HTX_C_GRX_N13
FDI1_TX[1]
15
FDI_CTX_PRX_P6
PEG_TX#[1]
C529
C529
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
D19
M31
PEG_HTX_GRX_N12
PEG_HTX_C_GRX_N12
FDI1_TX[2]
15
FDI_CTX_PRX_P7
PEG_TX#[2]
F17
L32
PEG_HTX_GRX_N11
C534
C534
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_HTX_C_GRX_N11
FDI1_TX[3]
PEG_TX#[3]
C538
C538
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
+1.05VS_VTT
PEG_HTX_GRX_N10
PEG_HTX_C_GRX_N10
L29
15
FDI_FSYNC0
PEG_TX#[4]
J18
PEG_HTX_GRX_N9
PEG_HTX_C_GRX_N9
K31
C540
C540
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
15
FDI_FSYNC1
FDI0_FSYNC
1
PEG_TX#[5]
J17
PEG_HTX_GRX_N8
PEG_HTX_C_GRX_N8
K28
C542
C542
FDI1_FSYNC
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_TX#[6]
C544
C544
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_HTX_GRX_N7
PEG_HTX_C_GRX_N7
eDP_COMPIO and ICOMPO signals should
be shorted near balls,
Trace Width for EDP_COMPIO=4mils,
J30
15
FDI_INT
PEG_TX#[7]
C546
C546
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
H20
PEG_HTX_GRX_N6
PEG_HTX_C_GRX_N6
J28
FDI_INT
C548
C548
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_TX#[8]
PEG_HTX_GRX_N5
PEG_HTX_C_GRX_N5
H29
15
FDI_LSYNC0
PEG_TX#[9]
C550
C550
PEG_HTX_GRX_N4
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_HTX_C_GRX_N4
J19
G27
C552
C552
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
R145 R145
15 FDI_LSYNC1
FDI0_LSYNC
PEG_TX#[10]
PEG_HTX_GRX_N3
PEG_HTX_C_GRX_N3
H17
E29
EDP_ICOMPO=12mils,
24.9_0402_1% 24.9_0402_1%
FDI1_LSYNC
PEG_TX#[11]
C554
C554
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_HTX_GRX_N2
2
DIS@
PEG_HTX_C_GRX_N2
F27
C556
C556
1 1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_TX#[12]
and both length less than 500 mils
should not be left floating
,even if disable eDP function
PEG_HTX_GRX_N1
PEG_HTX_C_GRX_N1
D28
PEG_TX#[13]
C558
C558
PEG_HTX_GRX_N0
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_HTX_C_GRX_N0
F26
EDP_COMP
PEG_TX#[14]
C560
C560
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
E25
PEG_TX#[15]
PEG_HTX_GRX_P15
PEG_HTX_C_GRX_P15
A18
C515
C515
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
eDP_COMPIO
PEG_HTX_GRX_P14
PEG_HTX_C_GRX_P14
M28
C528
C528
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
B
A17
B
eDP_ICOMPO
PEG_TX[0]
PEG_HTX_GRX_P13
PEG_HTX_C_GRX_P13
B16
M33
C533
C533
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
eDP_HPD
PEG_TX[1]
PEG_HTX_GRX_P12
PEG_HTX_C_GRX_P12
M30
PEG_TX[2]
C536
C536
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_HTX_GRX_P11
PEG_HTX_C_GRX_P11
L31
PEG_TX[3]
PEG_HTX_GRX_P10
C539
C539
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_HTX_C_GRX_P10
C15
L28
C541
C541
PEG_TX[4]
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
eDP_AUX
PEG_HTX_GRX_P9
PEG_HTX_C_GRX_P9
D15
K30
eDP_AUX#
PEG_TX[5]
C543
C543
DIS@
0.22U_0402_10V6K
PEG_HTX_GRX_P8
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_P8
K27
C545
C545
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_TX[6]
PEG_HTX_GRX_P7
1
2
PEG_HTX_C_GRX_P7
J29
C547
C547
1
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_TX[7]
PEG_HTX_GRX_P6
PEG_HTX_C_GRX_P6
C17
J27
eDP_TX[0]
PEG_TX[8]
PEG_HTX_GRX_P5
PEG_HTX_C_GRX_P5
F16
H28
C551
C551
C549
C549
1
1 2
DIS@
2
DIS@
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
eDP_TX[1]
PEG_TX[9]
PEG_HTX_GRX_P4
PEG_HTX_C_GRX_P4
C16
G28
C553
C553
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
eDP_TX[2]
PEG_TX[10]
PEG_HTX_GRX_P3
1 PEG_HTX_C_GRX_P3
G15
E28
C555
C555
PEG_TX[11]
PEG_HTX_GRX_P2
1 PEG_HTX_C_GRX_P2
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
eDP_TX[3]
F28
C557
C557
2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
PEG_TX[12]
PEG_HTX_GRX_P1
1 PEG_HTX_C_GRX_P1
C18
D27
eDP_TX#[0]
PEG_TX[13]
PEG_HTX_GRX_P0
PEG_HTX_C_GRX_P0
E16
E26
C559
C559
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
C561
C561
2
1
1 2
DIS@
DIS@
0.22U_0402_10V6K
0.22U_0402_10V6K
eDP_TX#[1]
PEG_TX[14]
D16
D25
eDP_TX#[2]
PEG_TX[15]
F15
eDP_TX#[3]
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
A
A
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2010/10/15
2010/10/15
2010/10/15
2011/10/15
2011/10/15
2011/10/15
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
0.4
0.4
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
JE50-HR/SJV50-HR M/B Schematics
JE50-HR/SJV50-HR M/B Schematics
JE50-HR/SJV50-HR M/B Schematics
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Sheet
Sheet
Sheet
4
4
4
of
of
of
61
61
61
5
4
3
2
1
12
FDIeDP
FDIeDP
DMIIntel(R)
DMIIntel(R)
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
12
5 4 3 2 1 Buffered reset to CPU D +3VS D +3VALW +1.05VS_VTT +1.5V_CPU_VDDQ
5
4
3
2
1
Buffered reset to CPU
D
+3VS
D
+3VALW
+1.05VS_VTT
+1.5V_CPU_VDDQ
1
C162
C162
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C307 C307
2
R90
R90
0.1U_0402_16V4Z 0.1U_0402_16V4Z
75_0402_1%
75_0402_1%
R205 R205
2
@
@
U7
U7
R87 R87
U11 U11
200_0402_1% 200_0402_1%
1
R782 R782
2
1
43_0402_1% 43_0402_1%
74AHC1G09GW_TSSOP5 74AHC1G09GW_TSSOP5
NC
BUFO_CPU_RST#
BUF_CPU_RST#
0_0402_5%
0_0402_5%
4
1
2
PLT_RST#
Y
17
PLT_RST#
1
R64 R64
2
2
15 SYS_PWROK
1
A
B
PM_SYS_PWRGD_BUF
PM_DRAM_PWRGD_R
0_0402_5%
0_0402_5%
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
4
1
2
O
R204
R204
130_0402_5%
130_0402_5%
15 PM_DRAM_PWRGD
2
A
R88
R88
0_0402_5%
0_0402_5%
R203
R203
@
@
39_0402_1%
39_0402_1%
RESET#:都都都都 ok後後後後後後後後CPU做做做做reset
@
@
SNB_IVB# had changed the name to
PROC_SELCT#,function for future platform,
connect to the DF_TVS strap on the PCH
JCPU1B
JCPU1B
C
C
CLK_CPU_DMI
A28
CLK_CPU_DMI
14
BCLK
CLK_CPU_DMI#
A27
17 H_SNB_IVB#
C26
CLK_CPU_DMI#
14
SNB_IVB#
BCLK#
AN34
SKTOCC#
A16
R516
R516
2
1
1K_0402_5%
1K_0402_5%
DPLL_REF_SSCLK
R518
R518
2
1
1K_0402_5%
1K_0402_5%
A15
+1.05VS_VTT
DPLL_REF_SSCLK#
H_CATERR#
T6 T6
PAD PAD
AL33
CATERR#
@
@
R93
R93
0_0402_5%
0_0402_5%
If use External Graphic or
use integrated without eDP
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
H_PECI_ISO
Processor Pullups
SM_DRAMRST#
18,40
H_PECI
1
2
AN33
R8
SM_DRAMRST# 6
PECI
SM_DRAMRST#
+1.05VS_VTT
2
R91
R91
1
62_0402_5%
62_0402_5%
R92 R92
56_0402_5%
56_0402_5%
H_PROCHOT#
H_PROCHOT#_R
SM_RCOMP0
R231
R231
2
1
140_0402_1%
140_0402_1%
40,50
H_PROCHOT#
AL32
AK1
1
2
PROCHOT#
SM_RCOMP[0]
SM_RCOMP1
A5
R566
R566
2
1
25.5_0402_1%
25.5_0402_1%
SM_RCOMP[1]
SM_RCOMP2
R97 R97
A4
R571
R571
2
1
200_0402_1%
200_0402_1%
SM_RCOMP[2]
0_0402_5% 0_0402_5%
H_THEMTRIP#_R
DDR3 Compensation Signals
18 H_THRMTRIP#
1
2
AN32
THERMTRIP#
R03 modify
AP29
PRDY#
AP27
PREQ#
B
B
TCK
+3VS
R96 R96
AR26
@
@
TCK
TMS
PAD PAD
T66 T66
0_0402_5%
0_0402_5%
AR27
@
@
H_PM_SYNC_R
TMS
TRST#
PAD PAD
T67 T67
15 H_PM_SYNC
AM34
AP30
1
2
@
@
PM_SYNC
TRST#
PAD PAD
T68 T68
TDI
R84
R84
2
1
10K_0402_5%
10K_0402_5%
R81
R81
AR28
@
@
TDI
TDO
PAD PAD
T69 T69
R40
R40
0_0402_5%
0_0402_5%
AP26
@
@
H_CPUPWRGD_R
TDO
PAD
PAD
T70
T70
18 H_CPUPWRGD
1K_0402_5%
1K_0402_5%
1
2
AP33
UNCOREPWRGOOD
R101 R101
UNCOREPWRGOOD:非非非 非CORE外外外外外外外外外外外外OK
0_0402_5% 0_0402_5%
DBRESET#_R
XDP_DBRESET#
AL35
1
2
XDP_DBRESET# 15
PM_DRAM_PWRGD_R
DBR#
V8
SM_DRAMPWROK
AT28
SM_DRAMPWROK:DRAM power ok
BPM#[0]
AR29
BPM#[1]
AR30
BUF_CPU_RST#
BPM#[2]
AR33
AT30
RESET#
BPM#[3]
AP32
BPM#[4]
AR31
BPM#[5]
AT31
BPM#[6]
AR32
BPM#[7]
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
A
A
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
2010/10/15
2010/10/15
2010/10/15
2011/10/15
2011/10/15
2011/10/15
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
JE50-HR/SJV50-HR M/B Schematics
0.4
JE50-HR/SJV50-HR M/B Schematics
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
JE50-HR/SJV50-HR M/B Schematics
0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Sheet
Sheet
Sheet
5
5
5
of
of
of
61
61
61
5
4
3
2
1
3
5
G
P
12
12
MISCTHERMALPWR
MISCTHERMALPWR
MANAGEMENT
MANAGEMENT
JTAG & BPM
JTAG & BPM
DDR3
DDR3
CLOCKS
CLOCKS
MISC
MISC
3
5
G
P
12
12
12
5 4 3 2 1 JCPU1C JCPU1C JCPU1D JCPU1D AB6 AE2 11 DDR_A_D[0 63] SA_CLK[0]
5
4
3
2
1
JCPU1C
JCPU1C
JCPU1D
JCPU1D
AB6
AE2
11 DDR_A_D[0 63]
SA_CLK[0]
12 DDR_B_D[0 63]
SA_CLK_DDR0
11
SB_CLK[0]
12
AA6
AD2
SA_CLK_DDR#0
11
SA_CLK#[0]
SB_CLK#[0]
SB_CLK_DDR#0
12
DDR_A_D0
DDR_B_D0
SB_CLK_DDR0
C5
V9
C9
R9
DDRA_CKE0_DIMMA
11
SA_DQ[0]
SA_CKE[0]
SB_DQ[0]
SB_CKE[0]
DDRB_CKE0_DIMMB
12
DDR_A_D1
DDR_B_D1
D5
A7
SA_DQ[1]
SB_DQ[1]
DDR_A_D2
DDR_B_D2
D3
D10
DDR_A_D3
SA_DQ[2]
SB_DQ[2]
DDR_B_D3
D2
C8
DDR_A_D4
SA_DQ[3]
SB_DQ[3]
DDR_B_D4
D6
AA5
A9
AE1
11
12
D
DDR_A_D5
SA_DQ[4]
SA_CLK[1]
SA_CLK_DDR1
SB_DQ[4]
SB_CLK[1]
D
DDR_B_D5
C6
AB5
A8
AD1
SA_CLK_DDR#1
11
SB_CLK_DDR#1
12
DDR_A_D6
SA_DQ[5]
SA_CLK#[1]
SB_DQ[5]
SB_CLK#[1]
DDR_B_D6
SB_CLK_DDR1
C2
V10
D9
R10
DDRA_CKE1_DIMMA
11
SB_DQ[6]
DDRB_CKE1_DIMMB
DDR_A_D7
SB_CKE[1]
12
SA_DQ[6]
SA_CKE[1]
DDR_B_D7
C3
D8
DDR_A_D8
SA_DQ[7]
SB_DQ[7]
DDR_B_D8
F10
G4
DDR_A_D9
SA_DQ[8]
SB_DQ[8]
DDR_B_D9
F8
F4
DDR_A_D10
SA_DQ[9]
SB_DQ[9]
DDR_B_D10
G10
F1
AB4
AB2
DDR_A_D11
SA_DQ[10]
DDR_B_D11
SB_DQ[10]
SA_CLK[2]
SB_CLK[2]
G9
G1
AA4
AA2
DDR_A_D12
SA_DQ[11]
SB_DQ[11]
SA_CLK#[2]
DDR_B_D12
SB_CLK#[2]
F9
G5
W9
T9
DDR_A_D13
SA_DQ[12]
SA_CKE[2]
DDR_B_D13
SB_DQ[12]
SB_CKE[2]
F7
F5
DDR_A_D14
SA_DQ[13]
DDR_B_D14
SB_DQ[13]
G8
F2
DDR_A_D15
SA_DQ[14]
DDR_B_D15
SB_DQ[14]
G7
G2
DDR_A_D16
SA_DQ[15]
DDR_B_D16
SB_DQ[15]
K4
J7
AB3
AA1
DDR_A_D17
DDR_B_D17
SB_DQ[16]
SA_DQ[16]
SB_CLK[3]
SA_CLK[3]
J8
K5
AB1
AA3
DDR_A_D18
SB_DQ[17]
SA_DQ[17]
SB_CLK#[3]
SA_CLK#[3]
DDR_B_D18
K10
K1
T10
W10
DDR_A_D19
DDR_B_D19
SB_DQ[18]
SA_DQ[18]
SB_CKE[3]
SA_CKE[3]
K9
J1
DDR_A_D20
SA_DQ[19]
DDR_B_D20
SB_DQ[19]
J9
J5
DDR_A_D21
SB_DQ[20]
SA_DQ[20]
DDR_B_D21
J10
J4
DDR_A_D22
DDR_B_D22
SB_DQ[21]
SA_DQ[21]
K8
J2
AK3
DDRA_CS0_DIMMA#
11
AD3
DDRB_CS0_DIMMB#
12
DDR_A_D23
SA_DQ[22]
SA_CS#[0]
DDR_B_D23
SB_DQ[22]
SB_CS#[0]
K7
K2
AL3
DDRA_CS1_DIMMA#
11
AE3
DDRB_CS1_DIMMB#
12
DDR_A_D24
SA_DQ[23]
SA_CS#[1]
DDR_B_D24
SB_DQ[23]
SB_CS#[1]
M5
AD6
DDR_A_D25
M8
AG1
DDR_B_D25
SB_DQ[24]
SA_DQ[24]
SB_CS#[2]
SA_CS#[2]
N4
AE6
DDR_A_D26
N10
AH1
DDR_B_D26
SB_DQ[25]
SA_DQ[25]
SB_CS#[3]
SA_CS#[3]
N2
DDR_A_D27
N8
DDR_B_D27
SB_DQ[26]
SA_DQ[26]
N1
DDR_A_D28
N7
DDR_B_D28
SB_DQ[27]
SA_DQ[27]
M4
DDR_A_D29
M10
DDR_B_D29
SB_DQ[28]
SA_DQ[28]
AE4
DDR_A_D30
M9
AH3
SA_ODT0 11
N5
DDR_B_D30
SB_DQ[29]
SB_ODT[0]
SB_ODT0 12
SA_DQ[29]
SA_ODT[0]
AD4
DDR_A_D31
N9
AG3
SA_ODT1 11
M2
SB_ODT1 12
SA_ODT[1]
DDR_B_D31
SB_DQ[30]
SB_ODT[1]
SA_DQ[30]
M1
AD5
DDR_A_D32
M7
AG2
DDR_B_D32
SB_DQ[31]
SB_ODT[2]
SA_DQ[31]
SA_ODT[2]
AM5
DDR_A_D33
AE5
AG6
AH2
DDR_B_D33
SB_DQ[32]
SB_ODT[3]
SA_DQ[32]
SA_ODT[3]
AM6
DDR_A_D34
AG5
DDR_B_D34
SB_DQ[33]
SA_DQ[33]
AR3
DDR_A_D35
AK6
DDR_B_D35
SB_DQ[34]
SA_DQ[34]
DDR_A_D36
AP3
AK5
DDR_B_D36
SB_DQ[35]
SA_DQ[35]
C
AN3
DDR_A_D37
AH5
DDR_A_DQS#0
DDR_A_DQS#[0
7]
11
7]
12
C
DDR_B_D37
SB_DQ[36]
DDR_B_DQS#0
SA_DQ[36]
DDR_A_D38
AN2
D7
AH6
C4
DDR_A_DQS#1
SB_DQS#[0]
SA_DQS#[0]
DDR_B_D38
SB_DQ[37]
DDR_B_DQS#1
SA_DQ[37]
F3
DDR_A_D39
AN1
AJ5
G6
DDR_A_DQS#2
DDR_B_D39
SB_DQS#[1]
SA_DQ[38]
SA_DQS#[1]
SB_DQ[38]
DDR_B_DQS#2
DDR_A_D40
AP2
K6
AJ6
J3
DDR_A_DQS#3
DDR_B_D40
SB_DQ[39]
SB_DQS#[2]
DDR_B_DQS#3
SA_DQ[39]
SA_DQS#[2]
N3
DDR_A_D41
AP5
AJ8
M6
DDR_A_DQS#4
DDR_B_D41
SB_DQ[40]
SB_DQS#[3]
DDR_B_DQS#4
SA_DQ[40]
SA_DQS#[3]
AN9
AN5
DDR_A_D42
AK8
AL6
DDR_A_DQS#5
DDR_B_D42
SB_DQ[41]
SB_DQS#[4]
DDR_B_DQS#5
SA_DQ[41]
SA_DQS#[4]
AT5
AP9
DDR_A_D43
AJ9
AM8
DDR_A_DQS#6
DDR_B_D43
SB_DQ[42]
SB_DQS#[5]
DDR_B_DQS#6
SA_DQ[42]
SA_DQS#[5]
AT6
AK12
DDR_A_D44
AK9
AR12
DDR_A_DQS#7
DDR_B_D44
SB_DQ[43]
SB_DQS#[6]
DDR_B_DQS#7
SA_DQ[43]
SA_DQS#[6]
DDR_B_DQS#[0
DDR_A_D45
AP6
AP15
AH8
AM15
DDR_B_D45
SB_DQ[44]
SB_DQS#[7]
SA_DQ[44]
SA_DQS#[7]
DDR_A_D46
AN8
AH9
DDR_B_D46
SB_DQ[45]
DDR_A_D47
SA_DQ[45]
AR6
AL9
DDR_B_D47
SB_DQ[46]
SA_DQ[46]
DDR_A_D48
AR5
AL8
DDR_B_D48
SB_DQ[47]
SA_DQ[47]
DDR_A_D49
DDR_A_DQS0
DDR_A_DQS[0
7]
11
AR9
7]
12
AP11
DDR_B_D49
SB_DQ[48]
DDR_B_DQS0
SA_DQ[48]
C7
DDR_A_D50
D4
DDR_A_DQS1
AJ11
AN11
DDR_B_D50
SB_DQS[0]
SB_DQ[49]
DDR_B_DQS1
SA_DQS[0]
DDR_A_D51
SA_DQ[49]
G3
F6
DDR_A_DQS2
AT8
AL12
DDR_B_D51
SB_DQS[1]
SB_DQ[50]
DDR_B_DQS2
SA_DQS[1]
DDR_A_D52
SA_DQ[50]
J6
DDR_A_DQS3
AT9
K3
AM12
DDR_B_D52
SB_DQS[2]
SB_DQ[51]
DDR_B_DQS3
SA_DQS[2]
DDR_A_D53
SA_DQ[51]
M3
N6
DDR_A_DQS4
DDR_B_D53
AH11
AM11
SB_DQS[3]
SB_DQ[52]
DDR_B_DQS4
SA_DQS[3]
DDR_A_D54
SA_DQ[52]
AN6
AR8
AL5
DDR_A_DQS5
AL11
DDR_B_D54
SB_DQS[4]
SB_DQ[53]
DDR_B_DQS5
SA_DQS[4]
DDR_A_D55
SA_DQ[53]
AP8
DDR_A_DQS6
AJ12
AM9
DDR_B_D55
SB_DQS[5]
AP12
SB_DQ[54]
DDR_B_DQS6
DDR_A_D56
SA_DQS[5]
SA_DQ[54]
AK11
DDR_A_DQS7
AH12
AR11
DDR_B_D56
SB_DQS[6]
AN12
DDR_B_DQS7
SB_DQ[55]
DDR_A_D57
SA_DQS[6]
SA_DQ[55]
AP14
DDR_B_DQS[0
AT11
AM14
DDR_B_D57
SB_DQS[7]
AJ14
SB_DQ[56]
DDR_A_D58
SA_DQS[7]
SA_DQ[56]
AN14
DDR_B_D58
AH14
SB_DQ[57]
DDR_A_D59
SA_DQ[57]
DDR_B_D59
AR14
AL15
SB_DQ[58]
DDR_A_D60
SA_DQ[58]
DDR_B_D60
AT14
AK15
SB_DQ[59]
DDR_A_D61
SA_DQ[59]
DDR_A_MA0
DDR_A_MA[0
15]
11
DDR_B_D61
AT12
DDR_B_MA[0
15]
12
DDR_B_MA0
AL14
SB_DQ[60]
DDR_A_D62
SA_DQ[60]
AA8
DDR_A_MA1
DDR_B_D62
AN15
AD10
SB_MA[0]
AK14
SB_DQ[61]
DDR_B_MA1
DDR_A_D63
SA_MA[0]
SA_DQ[61]
T7
DDR_A_MA2
DDR_B_D63
AR15
W1
SB_MA[1]
DDR_B_MA2
AJ15
SB_DQ[62]
SA_MA[1]
SA_DQ[62]
R7
DDR_A_MA3
AT15
W2
SB_MA[2]
DDR_B_MA3
AH15
SB_DQ[63]
SA_MA[2]
SA_DQ[63]
DDR_A_MA4
T6
W7
SB_MA[3]
DDR_B_MA4
SA_MA[3]
DDR_A_MA5
T2
V3
SB_MA[4]
DDR_B_MA5
SA_MA[4]
DDR_A_MA6
T4
V2
SB_MA[5]
DDR_B_MA6
SA_MA[5]
DDR_A_MA7
T3
W3
SB_MA[6]
DDR_B_MA7
B
B
11
DDR_A_BS0
SA_MA[6]
AA9
DDR_A_MA8
12 DDR_B_BS0
R2
AE10
SB_BS[0]
W6
SB_MA[7]
DDR_B_MA8
SA_BS[0]
11
DDR_A_BS1
SA_MA[7]
AA7
DDR_A_MA9
12
DDR_B_BS1
T5
AF10
SB_BS[1]
V1
SB_MA[8]
DDR_B_MA9
SA_BS[1]
11
DDR_A_BS2
SA_MA[8]
R6
DDR_A_MA10
12
DDR_B_BS2
R3
V6
SB_BS[2]
W5
SB_MA[9]
DDR_B_MA10
SA_BS[2]
SA_MA[9]
DDR_A_MA11
AB7
AD8
SB_MA[10]
DDR_B_MA11
SA_MA[10]
DDR_A_MA12
R1
V4
SB_MA[11]
DDR_B_MA12
SA_MA[11]
DDR_A_MA13
T1
W4
SB_MA[12]
DDR_B_MA13
11
DDR_A_CAS#
SA_MA[12]
AA10
DDR_A_MA14
12
DDR_B_CAS#
AB10
AE8
SB_CAS#
AF8
SB_MA[13]
DDR_B_MA14
11
DDR_A_RAS#
SA_CAS#
SA_MA[13]
DDR_A_MA15
AB8
12
DDR_B_RAS#
R5
AD9
SB_RAS#
DDR_B_MA15
V5
SB_MA[14]
11
DDR_A_WE#
SA_RAS#
SA_MA[14]
AB9
12 DDR_B_WE#
R4
AF9
SB_WE#
V7
SB_MA[15]
SA_WE#
SA_MA[15]
D
D
G G
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
S
S
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
CONN@ CONN@
+1.5V
Follow CRB1.0
@ R184
@ R184
0_0402_5%
0_0402_5%
R217
R217
CPU通通 DIMM做reset
1
2
1K_0402_5%
1K_0402_5%
R155 R155
SM_DRAMRST#
DIMM_DRAMRST#_R
1K_0402_5%
1K_0402_5%
5 SM_DRAMRST#
DIMM_DRAMRST# 11,12
3
1
1
2
Q12
Q12
BSS138_NL_SOT23-3 BSS138_NL_SOT23-3
S0
R186 R186
A
4.99K_0402_1% 4.99K_0402_1%
RST_GATE hgih ,MOS ON
SM_DRAMRST# HIGH,DIMM_DRAMRST# HIGH
Dimm not reset
A
S3
11,12,14
RST_GATE
RST_GATE Low ,MOS OFF
SM_DRAMRST# lo,DIMM_DRAMRST# HIGH
Dimm not reset
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
1
S4,5
RST_GATE Low ,MOS OFF
2010/10/15
2010/10/15
2010/10/15
2011/10/15
2011/10/15
2011/10/15
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
C293 C293
SM_DRAMRST# lo,DIMM_DRAMRST# low
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
0.047U_0402_16V7K 0.047U_0402_16V7K
2
Dimm reset
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
JE50-HR/SJV50-HR M/B Schematics
0.4
JE50-HR/SJV50-HR M/B Schematics
0.4
JE50-HR/SJV50-HR M/B Schematics
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Sheet
Sheet
Sheet
6
6
6
of
of
of
61
61
61
5
4
3
2
1
1
2
2
12
DDR DDR SYSTEM SYSTEM MEMORY MEMORY A A
DDR DDR SYSTEM SYSTEM MEMORY MEMORY B B
5 4 3 2 1 CFG Straps for Processor CFG2 R112 R112 1K_0402_5% 1K_0402_5% D
5
4
3
2
1
CFG Straps for Processor
CFG2
R112 R112
1K_0402_5% 1K_0402_5%
D
D
JCPU1E
JCPU1E
PEG Static Lane Reversal - CFG2 is for the 16x
L7
RSVD28
CFG2
AG7
1: Normal Operation; Lane # definition matches
socket pin map definition
RSVD29
CFG0
AK28
AE7
CFG[0]
RSVD30
AK29
AK2
CFG[1]
RSVD31
CFG2
0:Lane Reversed
AL26
W8
CFG[2]
RSVD32
*
AL27
CFG[3]
CFG4
AK26
CFG[4]
CFG5
CFG4
AL29
AT26
CFG[5]
RSVD33
CFG6
AL30
AM33
CFG[6]
RSVD34
CFG7
@
@
AM31
AJ27
CFG[7]
RSVD35
AM32
CFG[8]
R109 R109
AM30
CFG[9]
AM28
1K_0402_5% 1K_0402_5%
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
T8
CFG[13]
RSVD37
AN26
J16
CFG[14]
RSVD38
AM27
H16
CFG[15]
RSVD39
AK31
G16
CFG[16]
RSVD40
AN29
CFG[17]
Display Port Presence Strap
C
C
AR35
RSVD41
CFG4
*
AJ31
AT34
: Disabled; No Physical Display Port
attached to Embedded Display Port
1
RSVD1
RSVD42
AH31
AT33
RSVD2
RSVD43
AJ33
AP35
RSVD3
RSVD44
AR34
RSVD45
: Enabled; An external Display Port device is
connected to the Embedded Display Port
0
AH33
RSVD4
AJ26
RSVD6 and RSVD7 had changed to
SA_DIMM_VREFDQ and SB_DIMMVREFDQ
RSVD5
CFG6
B34
SA_DIMM_VREFDQ
RSVD46
11 SA_DIMM_VREFDQ
B4
A33
SB_DIMM_VREFDQ
RSVD6
RSVD47
CFG5
12 SB_DIMM_VREFDQ
D1
A34
RSVD7
RSVD48
B35
RSVD49
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
For Future CPU M3 support,
Sandey bridge not supportM3,
Check list1.0&CRB say can NC
C35
RSVD50
R107
R107
R108 R108
1K_0402_5% @
1K_0402_5% @
@
@
1K_0402_5% 1K_0402_5%
F25
RSVD8
R154
R154
R164 R164
F24
1K_0402_5%
1K_0402_5%
1K_0402_5% 1K_0402_5%
RSVD9
F23
RSVD10
D24
AJ32
RSVD11
RSVD51
G25
AK32
RSVD12
RSVD52
G24
RSVD13
AH27 change to VCC_DIE_SENSE
E23
RSVD14
D23
RSVD15
C30
AH27
PAD PAD
T7 T7
RSVD16
RSVD53
A31
@
@
RSVD17
B30
RSVD18
PCIE Port Bifurcation Straps
B29
RSVD19
D30
AN35
VCCIO_SEL
RSVD20
RSVD54
B31
AM35
RSVD21
RSVD55
11: (Default) x16 - Device 1 functions 1 and 2 disabled
A30
RSVD22
RSVD54 and RSVD55 had changed to
BCLK_ITP and BCLK_ITP#
*
C29
B
B
RSVD23
R513 R513
CFG[6:5]
@
@
10K_0402_5% 10K_0402_5%
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
J20
RSVD24
B18
AT2
VCCIO_SEL
RSVD25
RSVD56
A19
AT1
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
RSVD26
RSVD57
AR1
RSVD58
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
VCCIO_SEL For 2012 CPU support
J15
RSVD27
1/NC : (Default) +1.05VS_VTT
A19
*
B1
KEY
CFG7
0: +1.0VS_VTT
R102 R102
RSVD26 had changed the name to VCCIO_SEL
Need PH +3VALW 10K at +1.05VS_VTT source
for 2012 processor +1.05V and +1.0V select
@
@
1K_0402_5% 1K_0402_5%
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@
CONN@
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training
A
A
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
2010/10/15
2010/10/15
2010/10/15
2011/10/15
2011/10/15
2011/10/15
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
JE50-HR/SJV50-HR M/B Schematics
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
JE50-HR/SJV50-HR M/B Schematics
0.4
JE50-HR/SJV50-HR M/B Schematics
0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Date:
Date:
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Sheet
Sheet
Sheet
7
7
7
of
of
of
61
61
61
5
4
3
2
1
12
12
12
RESERVED
RESERVED
12
12
12
12
12

5

4

3

2

1

POWER

POWER

C641 C641 22U_0805_6.3V6M 22U_0805_6.3V6M C291 C291 22U_0805_6.3V6M 22U_0805_6.3V6M C292 C292 22U_0805_6.3V6M
C641 C641
22U_0805_6.3V6M
22U_0805_6.3V6M
C291
C291
22U_0805_6.3V6M
22U_0805_6.3V6M
C292
C292
22U_0805_6.3V6M
22U_0805_6.3V6M
C816
C816
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
C229 C229
22U_0805_6.3V6M
22U_0805_6.3V6M
C232
C232
22U_0805_6.3V6M
22U_0805_6.3V6M
C638
C638
330U_D2_2V_Y
330U_D2_2V_Y
C288
C288
C616
C616
22U_0805_6.3V6M
22U_0805_6.3V6M
330U_D2_2V_Y
330U_D2_2V_Y
C289
C289
22U_0805_6.3V6M
22U_0805_6.3V6M
C648 C648
22U_0805_6.3V6M
22U_0805_6.3V6M
C652
C652
C649
C649
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
C647
C647
C650 C650
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
C290
C290
22U_0805_6.3V6M
22U_0805_6.3V6M
C651 C651
22U_0805_6.3V6M
22U_0805_6.3V6M
SV type CPU
JCPU1F
JCPU1F
QC
94A
DC
53A
8.5A
AG35
VCC1
+1.05VS_VTT
1
1
1
AG34
1
AH13
1
VCC2
VCCIO1
AG33
AH10
1
1
1
1
1
1
1
1
1
1
VCC3
VCCIO2
AG32
AG10
VCC4
VCCIO3
AG31
AC10
2
2
2
2
2
VCC5
VCCIO4
AG30
Y10
VCC6
VCCIO5
2
2
2
2
2
2
2
2
2
2
AG29
U10
VCC7
VCCIO6
AG28
P10
VCC8
VCCIO7
AG27
L10
VCC9
VCCIO8
AG26
J14
VCC10
VCCIO9
AF35
J13
VCC11
VCCIO10
1
1
1
1
AF34
J12
1
VCC12
VCCIO11
AF33
J11
1
1
1
1
1
1
1
VCC13
VCCIO12
R02 modify
AF32
H14
VCC14
VCCIO13
+
+
+
+
+
+
AF31
H12
2
2
2
2
VCC15
VCCIO14
2
@
@
@
@
@
@
AF30
H11
VCC16
2
2
2
2
VCCIO15
AF29
G14
VCC17
2
VCCIO16
2
2
AF28
G13
VCC18
VCCIO17
AF27
G12
VCC19
VCCIO18
@
@
AF26
F14
VCC20
VCCIO19
AD35
F13
VCC21
VCCIO20
AD34
F12
VCC22
VCCIO21
AD33
F11
VCC23
VCCIO22
AD32
E14
INTEL Recommend
VCC24
VCCIO23
AD31
E12
VCC25
VCCIO24
AD30
2*330uF,12*22uF
VCC26
1
1
1
1
1
AD29
E11
1
1
VCC27
VCCIO25
AD28
D14
VCC28
from PDDG 1.0
VCCIO26
AD27
D13
VCC29
VCCIO27
AD26
2
2
2
2
D12
2
VCC30
VCCIO28
2
2
AC35
D11
VCC31
VCCIO29
AC34
C14
VCC32
VCCIO30
AC33
C13
VCC33
VCCIO31
AC32
C12
VCC34
VCCIO32
AC31
C11
VCC35
VCCIO33
AC30
B14
VCC36
1
1
VCCIO34
1
1
1
AC29
B12
1
1
VCC37
VCCIO35
AC28
A14
VCC38
VCCIO36
AC27
A13
VCC39
VCCIO37
AC26
2
2
2
2
A12
2
VCC40
2
2
2
VCCIO38
AA35
A11
VCC41
VCCIO39
AA34
C606 C606
VCC42
AA33
J23
22U_0805_6.3V6M
22U_0805_6.3V6M
VCC43
C160 C160
VCCIO40
AA32
VCC44
22U_0805_6.3V6M 22U_0805_6.3V6M
AA31
VCC45
AA30
VCC46
AA29
VCC47
C607
C607
AA28
VCC48
C171
C171
22U_0805_6.3V6M
22U_0805_6.3V6M
AA27
VCC49
22U_0805_6.3V6M
22U_0805_6.3V6M
AA26
+1.05VS_VTT
+1.05VS_VTT
VCC50
Y35
Follow Power Suggestion ,
place 3-pin Cap for CPU_CORE
VCC51
Y34
VCC52
Y33
VCC53
C172
C172
Y32
VCC54
R447 R447
22U_0805_6.3V6M
22U_0805_6.3V6M
C608
C608
Y31
R450 R450
C202
C202
VCC55
75_0402_1% 75_0402_1%
C222
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
C222
1
1
Y30
130_0402_5% 130_0402_5%
10U_0805_10V4Z
10U_0805_10V4Z
C562
C562
1
VCC56
10U_0805_10V4Z
10U_0805_10V4Z
+
+
+ +
Y29
+
+
470U_D2_2VM_R4M
470U_D2_2VM_R4M
+ +
VCC57
+
+
Y28
VCC58
Y27
VCC59
2
2
3
3
2
3
Y26
C575 C575
2
3
R448 R448
VCC60
C203 C203
C609 C609
2
3
V35
H_CPU_SVIDALRT#
22U_0805_6.3V6M
22U_0805_6.3V6M
43_0402_1%
43_0402_1%
VCC61
VR_SVID_ALRT#
55
10U_0805_10V4Z
10U_0805_10V4Z
C207
C207
22U_0805_6.3V6M
22U_0805_6.3V6M
AJ29
V34
H_CPU_SVIDCLK
C151
C151
VIDALERT#
VCC62
1
2
10U_0805_10V4Z
10U_0805_10V4Z
VR_SVID_CLK
55
AJ30
V33
H_CPU_SVIDDAT
470U_D2_2VM_R4M
470U_D2_2VM_R4M
PAW00
VIDSCLK
VCC63
R449
R449
R446
R446
1
1
0_0402_5%
0_0402_5%
2
0_0402_5%
0_0402_5%
2
VR_SVID_DAT
55
AJ28
V32
VIDSOUT
VCC64
V31
VCC65
C635 C635
use 470uF*2
V30
C610 C610
VCC66
C218
C218
22U_0805_6.3V6M
22U_0805_6.3V6M
V29
22U_0805_6.3V6M
22U_0805_6.3V6M
VCC67
C204
C204
C626
C626
10U_0805_10V4Z
10U_0805_10V4Z
330uF*3
V28
10U_0805_10V4Z
10U_0805_10V4Z
VCC68
470U_D2_2VM_R4M
470U_D2_2VM_R4M
V27
VCC69
Place the PU
resistors close to VR
V26
VCC70
U35
VCC71
C226 C226
U34
C627 C627
VCC72
C205 C205
22U_0805_6.3V6M
22U_0805_6.3V6M
U33
C223
C223
22U_0805_6.3V6M
22U_0805_6.3V6M
C233
C233
VCC73
10U_0805_10V4Z
10U_0805_10V4Z
U32
10U_0805_10V4Z
10U_0805_10V4Z
470U_D2_2VM_R4M
470U_D2_2VM_R4M
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
C225
C225
U28
C574 C574
VCC78
22U_0805_6.3V6M
22U_0805_6.3V6M
U27
22U_0805_6.3V6M
22U_0805_6.3V6M
VCC79
+CPU_CORE
C152 C152
U26
C206
C206
C227 C227
VCC80
Place the PU
resistors close to CPU
470U_D2_2VM_R4M
470U_D2_2VM_R4M
R35
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
VCC81
R34
VCC82
R33
VCC83
R32
C224 C224
R445
R445
C622 C622
VCC84
22U_0805_6.3V6M
22U_0805_6.3V6M
R31
22U_0805_6.3V6M
22U_0805_6.3V6M
100_0402_1%
100_0402_1%
VCC85
R30
VCC86
R29
VCC87
VCCSENSE_R
R28
VCCSENSE
55
VCC88
VSSSENSE_R
R444
R444
1 2
0_0402_5%
0_0402_5%
AJ35
R27
VCC_SENSE
R443
R443
1 2
0_0402_5%
0_0402_5%
VSSSENSE 55
VCC89
AJ34
R26
VSS_SENSE
VCC90
P35
VCC91
P34
VCC92
P33
VCCIO_SENSE
53
VCC93
VSSIO_SENSE
P32
B10
VCC94
R442 R442
VCCIO_SENSE
VSSIO_SENSE
A10
P31
VSSIO_SENSE
VCC95
100_0402_1% 100_0402_1%
P30
change to
VCC96
P29
VCC97
VSS_SENSE_VCCIO
R163 R163
P28
VCC98
10_0402_5% 10_0402_5%
P27
VCC99
P26
VCC100
Should change to connect form
power cirucit & layout differential
with VCCIO_SENSE.
CORE CORE SUPPLY SUPPLY
SENSE SENSE LINES LINES
SVID SVID
PEG PEG AND AND DDR DDR
12
12
12
12
12

+CPU_CORE

+CPU_CORE

+CPU_CORE

DDR DDR 12 12 12 12 12 +CPU_CORE +CPU_CORE +CPU_CORE +1.05VS_VTT D ME interefer,not pop!! C

+1.05VS_VTT

12 12 12 12 12 +CPU_CORE +CPU_CORE +CPU_CORE +1.05VS_VTT D ME interefer,not pop!! C B Security

D

ME interefer,not pop!!

C B
C
B

Security Classification

Security Classification

Security Classification

Sandy Bridge_rPGA_Rev0p61

Sandy Bridge_rPGA_Rev0p61

Compal Secret Data

Compal Secret Data

Compal Secret Data

Compal Electronics, Inc.

A

D

INTEL Recommend

4*470uF,16*22uF and 10*10uF from PDDG 1.0

C

INTEL Recommend 4*470uF,16*22uF and 10*10uF from PDDG 1.0 C B A Issued Date Issued Date Issued

B

A

Issued Date

Issued Date

Issued Date

CONN@

CONN@

2010/10/15

2010/10/15

2010/10/15

Deciphered Date

Deciphered Date

Deciphered Date

2011/10/15

2011/10/15

2011/10/15

Title

Title

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

Size

Size

Size

Custom

Custom

Custom

Document Number

Document Number

Document Number

JE50-HR/SJV50-HR M/B Schematics

JE50-HR/SJV50-HR M/B Schematics

JE50-HR/SJV50-HR M/B Schematics

Rev

Rev

Rev

0.4 0.4

0.4

5

4

3

2

1

Date:

Date:

Date:

Wednesday, October 27, 2010

Wednesday, October 27, 2010

Wednesday, October 27, 2010

Sheet

Sheet

Sheet

8

8

8

of

of

of

61

61

61

5

4

3

2

1

D

D

5 4 3 2 1 D D INTEL Recommend 2*470uF,12*22uF POWER POWER C355 C355 330U_D2_2V_Y 330U_D2_2V_Y

INTEL Recommend

2*470uF,12*22uF

POWER

POWER

C355 C355 330U_D2_2V_Y 330U_D2_2V_Y C361 C361 C221 C221 10U_0805_10V4Z 10U_0805_10V4Z 220U_B2_2.5VM_R35
C355 C355
330U_D2_2V_Y 330U_D2_2V_Y
C361
C361
C221
C221
10U_0805_10V4Z
10U_0805_10V4Z
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
C365
C365
10U_0805_10V4Z
10U_0805_10V4Z
C213
C213
C341
C341
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0805_10V4Z 10U_0805_10V4Z
C362 C362
C219
C219
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
C364
C364
10U_0805_10V4Z
10U_0805_10V4Z
C605
C605
10U_0805_10V4Z 10U_0805_10V4Z
C214
C214
C363 C363
10U_0805_10V4Z 10U_0805_10V4Z
10U_0805_10V4Z 10U_0805_10V4Z
QC
33A
from PDDG 1.0
JCPU1G
JCPU1G
DC
26A
AT24
AK35
VCC_AXG_SENSE 55
VAXG1
VAXG_SENSE
UMA@
UMA@
UMA@
UMA@
UMA@
UMA@
UMA@
UMA@
UMA@ UMA@
UMA@ UMA@
AT23
AK34
VSS_AXG_SENSE 55
VAXG2
VSSAXG_SENSE
R151 R151
1 1
1
1
AT21
1
1
VAXG3
0_0402_5% 0_0402_5%
AT20
+1.5V_CPU_VDDQ
VAXG4
AT18
DISO@ DISO@
VAXG5
AT17
2 2
2
2
VAXG6
2
2
AR24
VAXG7
AR23
VAXG8
AR21
+V_SM_VREF should
have 20 mil trace width
R582 R582
VAXG9
AR20
100_0402_1% 100_0402_1%
VAXG10
AR18
VAXG11
AR17
VAXG12
+V_SM_VREF
AP24
AL1
VAXG13
SM_VREF
AP23
UMA@
UMA@
VAXG14
UMA@ UMA@
UMA@
UMA@
UMA@ UMA@
UMA@
UMA@
1
UMA@ UMA@
AP21
VAXG15
C688 C688
1
1
1
1 AP20
R575
R575
1
1
VAXG16
0.1U_0402_16V4Z 0.1U_0402_16V4Z
AP18
100_0402_1%
100_0402_1%
VAXG17
AP17
VAXG18
2
C653
C653
2
2 AN24
2
2
VAXG19
1U_0402_6.3V6K
1U_0402_6.3V6K
2
2
AN23
VAXG20
AN21
+1.5V_CPU_VDDQ
VAXG21
AN20
+1.5V
C654
C654
VAXG22
AN18
1U_0402_6.3V6K
1U_0402_6.3V6K
VAXG23
10A
J1
J1
C231
C231
C275 C275
C599
C599
AN17
VAXG24
22U_0805_6.3V6M
22U_0805_6.3V6M
1
22U_0805_6.3V6M
22U_0805_6.3V6M
2
22U_0805_6.3V6M
22U_0805_6.3V6M
AM24
AF7
VAXG25
VDDQ1
AM23
AF4
VAXG26
VDDQ2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
AM21
AF1
1
VAXG27
VDDQ3
1
@
@
1
1
AM20
1
1
AC7
C242 C242
C600 C600
C655
C655
VAXG28
VDDQ4
1
+
+
1
C211 C211
1
1
1 AM18
AC4
22U_0805_6.3V6M
+1.5VS
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_10V4Z
10U_0805_10V4Z
1
1
VAXG29
VDDQ5
22U_0805_6.3V6M
22U_0805_6.3V6M
AM17
+ +
AC1
@
@
+
+
VAXG30
UMA@
UMA@
VDDQ6
J2
J2
AL24
Y7
2
2
2
2
VAXG31
2
@
VDDQ7
2
@
2
1
2
@
@
2 AL23
Y4
2
UMA@
UMA@
VAXG32
VDDQ8
2
2
2
UMA@ UMA@
AL21
Y1
C273
C273
2
VAXG33
C272 C272
C271
C271
VDDQ9
C664
C664
PAD-OPEN 4x4m
PAD-OPEN 4x4m
AL20
U7
22U_0805_6.3V6M
22U_0805_6.3V6M
VAXG34
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
VDDQ10
220U_B2_2.5VM_R35
220U_B2_2.5VM_R35
@
@
AL18
U4
VAXG35
VDDQ11
AL17
U1
VAXG36
VDDQ12
AK24
P7
VAXG37
VDDQ13
Short for +1.5VS to +1.5V_1
AK23
P4
C212 C212
C274 C274
C208
C208
Vaxg
VAXG38
VDDQ14
AK21
P1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
VAXG39
22U_0805_6.3V6M
22U_0805_6.3V6M
VDDQ15
INTEL Recommend
AK20
VAXG40
AK18
C625 C625
C209 C209
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
C611 C611
C210
C210
‧‧‧‧ Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
‧‧‧‧ VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed
VAXG41
INTEL Recommend
AK17
1*330uF,6*10uF
VAXG42
AJ24
VAXG43
AJ23
1*330uF,3*10uF
from PDDG 1.0
VAXG44
AJ21
VAXG45
AJ20
from PDDG 1.0
VAXG46
AJ18
VAXG47
AJ17
+VCCSA
VAXG48
6A
AH24
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
C645
C645
VAXG49
AH23
+VCCSA
330U_D2_2V_Y
330U_D2_2V_Y
VAXG50
AH21
M27
VAXG51
VCCSA1
AH20
M26
VAXG52
VCCSA2
AH18
L26
VCCSA_SENSE
VAXG53
VCCSA3
1
1
R137
R137
1
1
2
0_0402_5%
0_0402_5%
AH17
1
J26
VAXG54
C646
C646
VCCSA4
J25
If possible,use os-con cap
1
330U_D2_2V_Y
330U_D2_2V_Y
VCCSA5
J24
@
@
VCCSA6
if not,use the D2 size
2
2
H26
2
+ +
2
VCCSA7
H25
VCCSA8
R141
R141
1
2
0_0402_5%
0_0402_5%
VSSSA_SENSE 52
2
1.2A
+1.8VS
R528 R528
0_0805_5% 0_0805_5%
+1.8VS_VCCPLL
1
2
VCCSA_SENSE
52
B6
H23
VCCPLL1
VCCSA_SENSE
A6
1
VCCPLL2
1
VCCSA
1
A2
VCCPLL3
VCCSA_VID0
+
+
1
VCCSA_VID1
VID0
VID1
Vout
2011CPU
2012CPU
C22
VCCSA_VID1
52
FC_C22
2
C24
2
VCCSA_VID1
2
FC_C22
0
0
0.9V
V
V
2
change to
R143 R143
0
1
0.8V
V
V
R138
R138
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
VCCSA_VID0
10K_0402_5% 10K_0402_5%
@ 0_0402_5%
@ 0_0402_5%
1
0
0.725V
X
V
CONN@
CONN@
1
1
0.675V
X
V
12
1.8V RAIL
1.8V RAIL
GRAPHICS
GRAPHICS
SENSE
SENSE
VREFMISC
VREFMISC
SA RAIL
SA RAIL
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
LINES
LINES
1
2
12
12
12

+VGFX_CORE

INTEL Recommend 1*330uF,1*10uF and 2*1uF(0402) from PDDG 1.0

C

C B
C
B
1*330uF,1*10uF and 2*1uF(0402) from PDDG 1.0 C C B B A A Security Classification Security Classification

B

A

A

Security Classification

Security Classification

Security Classification

Compal Secret Data

Compal Secret Data

Compal Secret Data

Compal Electronics, Inc.

Issued Date

Issued Date

Issued Date

2010/10/15

2010/10/15

2010/10/15

Deciphered Date

Deciphered Date

Deciphered Date

2011/10/15

2011/10/15

2011/10/15

Title

Title

Title

Date:

Date:

Date:

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Size

Size

Size

Custom

Custom

Custom

Document Number

Document Number

Document Number

JE50-HR/SJV50-HR M/B Schematics

JE50-HR/SJV50-HR M/B Schematics

JE50-HR/SJV50-HR M/B Schematics

Rev

Rev

Rev

0.4 0.4

0.4

3

2

1

Wednesday, October 27, 2010

Wednesday, October 27, 2010

Wednesday, October 27, 2010

Sheet

Sheet

Sheet

9

9

9

of

of

of

61

61

61

5

4

5 4 3 2 1 JCPU1H JCPU1H JCPU1I JCPU1I D D AT35 AJ22 VSS1 VSS81
5
4
3
2
1
JCPU1H
JCPU1H
JCPU1I
JCPU1I
D
D
AT35
AJ22
VSS1
VSS81
AT32
AJ19
VSS2
VSS82
AT29
AJ16
T35
F22
VSS3
VSS83
VSS161
VSS234
AT27
AJ13
T34
F19
VSS4
VSS84
VSS162
VSS235
AT25
AJ10
T33
E30
VSS5
VSS85
VSS163
VSS236
AT22
AJ7
T32
E27
VSS6
VSS86
VSS164
VSS237
AT19
AJ4
T31
E24
VSS7
VSS87
VSS165
VSS238
AT16
AJ3
T30
E21
VSS8
VSS88
VSS166
VSS239
AT13
AJ2
T29
E18
VSS9
VSS89
VSS167
VSS240
AT10
AJ1
T28
E15
VSS10
VSS90
VSS168
VSS241
AT7
AH35
T27
E13
VSS11
VSS91
VSS169
VSS242
AT4
AH34
T26
VSS12
E10
VSS92
VSS170
VSS243
AT3
AH32
P9
VSS13
E9
VSS93
VSS171
VSS244
AR25
AH30
P8
VSS14
E8
VSS94
VSS172
VSS245
AR22
AH29
P6
VSS15
E7
VSS95
VSS173
VSS246
AR19
AH28
P5
VSS16
E6
VSS96
VSS174
VSS247
AR16
AH26
P3
VSS17
E5
VSS97
VSS175
VSS248
AR13
AH25
P2
VSS18
E4
VSS98
VSS176
VSS249
AR10
AH22
N35
VSS19
E3
VSS99
VSS177
VSS250
AR7
AH19
N34
VSS20
E2
VSS100
VSS178
VSS251
AR4
AH16
N33
VSS21
E1
VSS101
VSS179
AR2
VSS252
AH7
N32
VSS22
D35
VSS102
VSS180
AP34
VSS253
AH4
N31
VSS23
D32
VSS103
VSS181
AP31
VSS254
AG9
VSS24
N30
D29
VSS104
VSS182
AP28
VSS255
AG8
VSS25
N29
D26
VSS105
VSS183
AP25
VSS256
AG4
VSS26
N28
VSS106
D20
VSS184
AP22
VSS257
AF6
VSS27
N27
VSS107
D17
VSS185
AP19
VSS258
AF5
VSS28
N26
VSS108
C34
VSS186
AP16
VSS259
AF3
VSS29
M34
VSS109
C31
VSS187
AP13
VSS260
AF2
VSS30
L33
VSS110
C28
VSS188
AP10
VSS261
AE35
VSS31
L30
VSS111
C27
VSS189
AP7
VSS262
AE34
L27
C
VSS32
VSS112
C25
C
VSS190
AP4
VSS263
AE33
VSS33
L9
VSS113
C23
VSS191
AP1
VSS264
AE32
VSS34
L8
VSS114
C10
VSS192
AN30
VSS265
AE31
VSS35
L6
VSS115
C1
VSS193
AN27
VSS266
AE30
VSS36
L5
VSS116
B22
AN25
VSS194
VSS
VSS
VSS267
AE29
VSS37
L4
VSS117
B19
VSS195
AN22
VSS
VSS
VSS268
AE28
VSS38
L3
VSS118
B17
VSS196
AN19
VSS269
AE27
VSS39
L2
VSS119
B15
VSS197
AN16
VSS270
AE26
VSS40
L1
VSS120
B13
AN13
VSS198
VSS271
AE9
VSS41
K35
VSS121
B11
AN10
VSS199
AD7
VSS272
VSS42
K32
VSS122
B9
AN7
VSS200
VSS273
AC9
VSS43
K29
VSS123
B8
AN4
VSS201
AC8
VSS274
VSS44
K26
VSS124
B7
AM29
VSS202
AC6
VSS275
VSS45
J34
VSS125
B5
AM25
VSS203
AC5
VSS276
VSS46
J31
VSS126
B3
AM22
VSS204
AC3
VSS277
VSS47
H33
VSS127
B2
AM19
VSS205
AC2
VSS278
VSS48
H30
VSS128
A35
AM16
VSS206
AB35
VSS279
VSS49
H27
VSS129
A32
AM13
VSS207
AB34
VSS280
VSS50
H24
VSS130
A29
AM10
VSS208
AB33
VSS281
VSS51
H21
VSS131
A26
AM7
VSS209
AB32
VSS282
VSS52
H18
VSS132
A23
AM4
VSS210
AB31
VSS283
VSS53
H15
VSS133
A20
AM3
VSS211
AB30
VSS284
VSS54
H13
VSS134
A3
AM2
VSS212
AB29
VSS285
VSS55
H10
VSS135
AM1
VSS213
AB28
VSS56
H9
VSS136
AL34
VSS214
AB27
VSS57
H8
VSS137
AL31
VSS215
AB26
VSS58
H7
VSS138
AL28
VSS216
Y9
VSS59
H6
VSS139
AL25
VSS217
Y8
VSS60
H5
VSS140
AL22
VSS218
Y6
VSS61
H4
VSS141
AL19
VSS219
Y5
VSS62
H3
VSS142
AL16
VSS220
Y3
VSS63
H2
VSS143
AL13
VSS221
B
Y2
VSS64
H1
B
VSS144
AL10
VSS222
VSS65
W35
VSS145
G35
AL7
VSS223
VSS66
W34
VSS146
G32
AL4
VSS224
VSS67
W33
VSS147
G29
AL2
VSS225
VSS68
W32
VSS148
G26
AK33
VSS226
VSS69
W31
VSS149
G23
AK30
VSS227
VSS70
W30
VSS150
G20
AK27
VSS228
VSS71
W29
VSS151
G17
AK25
VSS229
VSS72
W28
VSS152
G11
AK22
VSS230
VSS73
W27
VSS153
F34
AK19
VSS231
VSS74
W26
VSS154
F31
AK16
VSS232
VSS75
U9
VSS155
F29
AK13
VSS233
VSS76
U8
VSS156
AK10
VSS77
U6
VSS157
AK7
VSS78
U5
VSS158
AK4
VSS79
U3
VSS159
AJ25
VSS80
U2
VSS160
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
Sandy Bridge_rPGA_Rev0p61
CONN@ CONN@
CONN@ CONN@
A
A
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
2010/10/15
2010/10/15
2010/10/15
2011/10/15
2011/10/15
2011/10/15
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Custom
Custom
JE50-HR/SJV50-HR M/B Schematics
0.4
JE50-HR/SJV50-HR M/B Schematics
0.4
JE50-HR/SJV50-HR M/B Schematics
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.