Experiment: 1 VHDL Program Date: 15.07.

15

Aim: To write a VHDL program for: i) 8 bit comparator

ii) 3 to 8 decoder
iii) 4:1 mux
iv) 4 bit ALU

i) VHDL Program for 8 bit comparator:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comp8bit is
Port(a:in STD_LOGIC_VECTOR(7 DOWNTO 0);
b:in STD_LOGIC_VECTOR(7 DOWNTO 0);
agtb: out STD_LOGIC;
bgta: out STD_LOGIC;
aequalb: out STD_LOGIC);
end comp8bit;

architecture Behavioral of comp8bit is

begin
aequalb<='1'when(a=b) else '0';
agtb<='1'when(a>b) else '0';
bgta<='1'when(a<b) else '0';
end Behavioral;

Output of 8 bit comparator:

ii) VHDL Program for 3 to 8 decoder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder3to8 is
Port(a:in STD_LOGIC_VECTOR(2 DOWNTO 0);
y:out STD_LOGIC_VECTOR(7 DOWNTO 0));
end decoder3to8;

architecture Behavioral of decoder3to8 is

begin
process(a)
begin
case a is
when "000" =>y<="00000001";
when "001" =>y<="00000010";
when "010" =>y<="00000100";
when "011" =>y<="00001000";
when "100" =>y<="00010000";
when "101" =>y<="00100000";
when "110" =>y<="01000000";
when others =>y<="10000000";
end case;
end process;
end Behavioral;

Output of 3 to 8 decoder:
iii) VHDL Program for 4:1 mux:
Using CASE/WHEN Using WITH/SELECT Using WHEN/ELSE
library IEEE; library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity mux is entity mux is use
port(s:in std_logic_vector(1 port(a,b,c,d: in std_logic; IEEE.STD_LOGIC_UNSIGNED.ALL;
downto 0); s:in std_logic_vector(1
a,b,c,d:in std_logic; downto 0); entity mux4to1 is
z:out std_logic); z:out std_logic); port(s:in std_logic_vector(1
end mux; downto 0);
a,b,c,d:in std_logic;
architecture Behavioral of mux end mux; z:out std_logic);
is end mux4to1;
architecture Behavioral of mux
begin is architecture Behavioral of
process(a,b,c,d,s) mux4to1 is
begin begin
case(s) is begin
when "00"=> z <=a; WITH S SELECT z<=a when s="00"else
when "01"=> z <=b;
when "10"=> z <=c; z<=a when "00", b when s="01"else
when others=> z <=d; b when "01",
end case; c when "10", c when s="10"else
end process; d when "11";
end Behavioral; d when s="11";
end Behavioral;
end Behavioral;

Output of 4:1 mux Using CASE/WHEN:

Output of 4:1 mux Using WITH/SELECT:

Output of 4:1 mux Using WHEN/ELSE:

iv) VHDL Program for 4 bit ALU:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu is
port(a,b,z: in std_logic_vector(3 downto 0);
y: out std_logic_vector(3 downto 0));
end alu;

architecture Behavioral of alu is

begin
process(a,b,z)
begin
case z is
when "0000" =>y<=a;
when "0001" =>y<=(not a);
when "0010" =>y<=b;
when "0011"=>y<=(not b);
when "0100"=>y<=(a and b);
when "0101"=>y<=(a or b);
when "0110"=>y<=(a nand b);
when "0111"=>y<=(a nor b);
when "1000"=>y<=(a xor b);
when "1001"=>y<=(a+1);
when "1010"=>y<=(b+1);
when "1011"=>y<=(a+b);
when "1100"=>y<=(a-1);
when "1101"=>y<=(b-1);
when "1111"=>y<=(a-b);
when others =>y<=(a xnor b);
end case;
end process;
end Behavioral;

Output of 4 bit ALU:

Conclusion: The VHDL program for 8 bit comparator, 3 to 8 decoder, 4:1 mux and 4 bit ALU was studied
and successfully implemented.