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Synchronous Counters

A ripple counter can only be used for applications in which the speed of operation is not very
important. If several stages of counting are employed, the time taken for a clock pulse to
ripple through the counter may well be excessive.

The operation time can be shortened considerably by arranging for all the flip-flops to be
clocked at the same time. This is known as synchronous operation.

In a synchronous counter all the flip-flops change their state simultaneously, the operation of
each stage being initiated by the clock. The arrangements of a 3-bit MOD 8 synchronous
counter and a 4-bit MOD-16 synchronous counter are shown in figures 1 and 2, respectively.

Figure 1

Figure 2

Design of synchronous counters

Sequential circuits can be classified into two types: (1) those in which the output or outputs
depend only on the present internal state (Moore state machines) and (2) those in which the
output or outputs depend on both the present state and the input or inputs (Mealy state
machines).
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Steps involved in counter design
In general, these steps can be applied to any state machine.
1. Specify the counter sequence and draw a state diagram.
2. Derive a next-state table from the state diagram.
3. Develop a transition table showing the flip-flop inputs required for each transition.
This will depend on the type of flip-flop you intend to use.
4. Transfer the J and K states (or states of other flip-flops you intend to use) from the
transition table to Karnaugh maps.
There is a Karnaugh map for the input of each flip-flop.
5. Group the Karnaugh map cells to generate and derive the logic expression for each
flip-flop input.
6. Implement the expressions with combinational logic, and combine with the flip-flops
to create the counter.

Example 1 Design a MOD 8 counter using J-K flip-flops.

1. The counter is first specified and a state diagram drawn. The state diagram shows the
sequence of states through which the counter advances when it is clocked. Figure 3
shows a state diagram of a 3-bit binary counter.

Figure 3.
State
diagram of a
3-bit binary
counter.

The circuit has no inputs other than the clock pulse and no outputs other than its internal state
(outputs are taken off each flip-flop in the counter). The next state of the counter depends
entirely on its present state, and the state transition occurs every time the clock pulse occurs.

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2. Once the sequential circuit is defined by the state diagram, the next step is to obtain
the next-state table, which is derived from the state diagram in Figure 3 and is shown
in Table I.

Table I - State table

Present State Next State


Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0

Since there are eight states, the number of flip-flops required would be three. Now we want to
implement the counter design using JK flip-flops.

3. Next step is to develop an excitation table from the state table, which is shown in
Table II.

Table II - Excitation table

Output State Transitions Flip-flop inputs


Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0X 0X 1X
0 0 1 0 1 0 0X 1X X1
0 1 0 0 1 1 0X X0 1X
0 1 1 1 0 0 1X X1 X1
1 0 0 1 0 1 X0 0X 1X
1 0 1 1 1 0 X0 1X X1
1 1 0 1 1 1 X0 X0 1X
1 1 1 0 0 0 X1 X1 X1

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4. Now transfer the JK states of the flip-flop inputs from the excitation table to
Karnaugh maps to derive a simplified Boolean expression for each flip-flop input.
This is shown in Figure 4.

Figure 4.
Karnaugh
maps

5. The 1s in the Karnaugh maps of Figure 4 are grouped with "don't cares" and the
following expressions for the J and K inputs of each flip-flop are obtained:

J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1*Q0

6. The final step is to implement the combinational logic from the equations and connect
the flip-flops to form the sequential circuit. The complete logic of a 3-bit binary
counter is shown in Figure 5.

Figure 5 Logic diagram of a 3-bit binary


counter 4
Exercise 1

Design a MOD 8 counter using T flip-flops.

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