1.

i) B
ii) C
iii) B
iv) D
v) D

2A.

For addition:
(i) -14 and 11
10010
+ 01011
_____
11101 No overflow
ii) -10 and -13
10110
+ 10011
----------
01001 overflow occurs

For subtraction: To subtract the second number, form its 2's-complement and add it to
the 1st number
(i) -14 and 11
10010
+ 10101
------------
00111 Overflow occurs
(ii) -10 and -13
10110
+ 01101
------------
00011 No overflow

2B.
Trace:
M=000100, Q= 101011, Size=6
M C A Q Size
Initial:
000100 0 000000 101011 6
I1:
000100 0 000100 101011 6
000100 0 000010 010101 5
I2:
000100 0 000110 010101 5
000100 0 000011 001010 4
I3:
000100 0 000001 100101 3

I4:
000100 0 000101 100101 3
000100 0 000010 110010 2

I5:
000100 0 000001 011001 1

I6:
000100 0 000101 011001 1
000100 0 000010 101100 0

The final product is 000010 101100=172 ( For hardware----1M, For Initial, I1---0.5M,
I2&I3---0.5M, I4&I5----0.5M, I6&Final answer----0.5M)
3A. flags are usually grouped together in a special processor register called the condition code register
or status register.
Commonly used flags:
N(Negative): set to 1 if the result is ve, otherwise cleared to 0.
Z(Zero): set to 1 if the result is 0, otherwise cleared to 0.
V(Overflow): set to 1 if arithmetic overflow occurs, otherwise cleared to 0.
C(Carry): set to 1 if carry-out results from the operation, otherwise cleared to 0.

3B.

Diagram:1 M , Equation: 1M, Explanation: 1 M

si = xi yi ci
ci+1 = xiyi + xici + yici

Factoring the second equation into

ci+1 = xiyi + (xi + yi)ci

we can write
ci+1 = Gi + Pici
where
Gi = xiyi and Pi = xi + yi
The expressions Gi and Pi are called the generate and propagate functions for stage i. If the
generate function for stage i is equal to 1, then ci+1 = 1, independent of the input carry, ci . This
occurs when both xi and yi are 1. The propagate function means that an input carry will produce
an output carry when either xi is 1 or yi is 1. All Gi and Pi functions can be formed independently
and in parallel in one logic-gate delay after the X and Y operands are applied to the inputs of an n-
bit adder. Each bit stage contains an AND gate to form Gi , an OR gate to form Pi , and a three-
input XOR gate to form si . A simpler circuit can be derived by observing that an adequate
propagate function can be realized as Pi = xi yi , which differs from Pi = xi + yi only when xi =
yi = 1. But, in this case Gi = 1, so it does not matter whether Pi is 0 or 1. Then, using a cascade of
two 2-input XOR gates to realize the 3-input XOR function for si , the basic B cell in Figure 9.4a
can be used in each bit stage. Expanding ci in terms of i 1 subscripted variables and substituting
into the ci+1 expression, we obtain
ci+1 = Gi + PiGi1 + PiPi1ci1
Continuing this type of expansion, the final expression for any carry variable is
ci+1 = Gi + PiGi1 + PiPi1Gi2 ++PiPi1 P1G0 + PiPi1.. P0c0

Let us consider the design of a 4-bit adder. The carries can be implemented as
c1 = G0 + P0c0
c2 = G1 + P1G0 + P1P0c0
c3 = G2 + P2G1 + P2P1G0 + P2P1P0c0
c4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0c0
P14P13P12P11P10P9P8G7+P15P14P13P12P11P10P9P8P7G6+P15P14P13P12P11P10P
9P8P7P6G5+P15P14P13P12P11P10P9P8P7P6P5G4+
P15P14P13P12P11P10P9P8P7P6P5P4G3+
P15P14P13P12P11P10P9P8P7P6P5P4P3G2+
P15P14P13P12P11P10P9P8P7P6P5P4P3P2G1+
P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1G0+
P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0C0
In higher level generate propagate function,
c16 = GI3+ PI3GI2+ PI3PI2GI1+ PI3PI2PI1GI0+ PI3PI2PI1PI0c0