PIN DIAGRAM

PORTS
 PIN DIAGRAM of 8051
8051 is a 40 Pin IC where 24 pins have dual functions : (64 pin usage)

PINS 01 08 : PORT 1
9 - RST Reset
PINS 10 17 : Port 3
10, 11 - RXD ; TXD Receive Data ; Transmit Data
12, 13 - INT0, INT1 External Interrupts
14, 15 - T0,T1 Timer 0 & Timer 1 inputs
16, 17 - , Write Strobe , Read Strobe
18, 19 XTAL 2, XTAL 1 Crystal Inputs
20 GND
PINS 21- 28 : PORT 2

Address A8 A15
29 -
30 ALE /
31 - / VPP
PINS 32 39 : PORT 0
Address lines (A0 A8) ;Data Lines (D0 D8)
40 VCC (5V)
 PIN 31: EA External Access

Active low pin that gives an

indication/access of program memory

= 1 : Executes instruction from Internal

Program Memory till 0FFF ( beyond this from
external)

= 0 : Executes all instructions from

external memory

On-chip ROM is connected to VPP

Members without on-chip ROM (8031/32) - is connected to GND : Indicates

Code is stored externally
 MOSTLY USED BY 8031 BASED SYSTEMS

PIN 30: ALE/ - Address Latch Enable

Output (Active high) pin used during

Address/Data Multiplexing

ALE = 0 indicates Data D0 D7

ALE = 1 indicates Address A0 A7

PIN 29: - Program Store Enable

Output signal (8031/8051) used to access

external ROM

Used along with EA

When EA is connected to GND : PSEN is activated

(Connected to OE pin of external ROM)
 PORTS & PORT STRUCTURE

Interfaces to the outside world are inbuilt in 8051 PORTS

8051 has four 8 - bit (bi-directional) ports

P0 80h (Simple I/O Port & Address/Data bus)
P1 90h (Simple I/O Port)
P2 A0h (Simple I/O Port & Address bus)
P3 B0h (Simple I/O Port & Special functions)

Each Port has 8 pins. Each pin has

D Latch
2 tri state buffers
 PORT 0 (PINS 32 39)
P0.0 P0.7
8 bit Bi-directional (R/W) Dual Nature Port
General Purpose I/O
Multiplexes both low byte address & data for external memory design

PORT 1 (PINS 1 8)
P1.0 P1.7
8 bit Bi-directional (R/W) I/O Port

True I/O port It doesn't have any alternative functions & can be
configured as general I/O only.
 8051 capable of accessing up to 64kB of external memory Needs a
path for 16 bit address

PORT 2 (Pins 21 28)

8 bit Bi-Directional (R/W) Dual Nature Port
General Purpose I/O
High Byte of Address Bus for external memory design

It is used along with P0 to provide 16 bit address for external memory

PORT 3 (PINS 10 17)

8 bit Bi-Directional (R/W) Dual Nature Port
General Purpose I/O
Alternate pin operations
 INPUT OUTPUT CAPABILITY

All pins of an PORT (I/O Mode) can be used as Output Pins / Input Pins

On power up all ports of 8051 are configured as Output Ports

Using port pins as OUTPUT requires no initialization (as it is already

with zeros which initializes as output by default)
To configure pins as INPUT - Write logic 1 to it

HARDWARE STRUCTURE OF AN I/O PIN

Each pin of I/O Port has the following structure

Internal CPU Bus (Communicates with CPU)
D Latch (Store the value of the pin)
2 Tri State Buffers (TB1, TB2)
Transistor Gate
 I/O PIN STRUCTURE FOR PORT 1

Write to Latch = 1 - Write data into D Latch

TB1: Controlled by Read Pin; When activated reads data present at pin
TB2: Controlled by Read Latch; When activated reads value from internal latch
Transistor M1 gate: 0 = Gate Closed ; 1 = Gate Open

The structure is same for Port 2 as well as Port 3

PORT OPERATION AS OUTPUT PORT (P1)

By default all ports are configured as output ports

 WRITING A 1 TO THE OUTPUT PORT
Send 1 as Output

A 1 written to port bit is written to the D Latch

= 1 = 0

= 0 ; Transistor M1 is OFF; It blocks any path to ground for the pin

Pin is now high

When 1 is written to a pin the o/p is also 1

 WRITING A 0 TO THE OUTPUT PORT
Send 0 as Output

A 0 written to port bit is written to the D Latch

= 1 = 0

= 0 ; Transistor M1 is ON; It provides a path to ground for the pin

Pin is now grounded (low)

When 0 is written to a pin the o/p is also 0

PORT OPERATION AS AN INPUT PORT (P1)

If a Port Pin is to be used as an input pin then it

needs to be initialized write a value of 1 to it!
 READING DATA [HIGH or LOW] AT THE INPUT PIN

MOV P1, #0FFh or SETB P2.3

A 1 written to port bit is written to the D Latch. = 1 = 0
= 0 ; Transistor M1 is OFF; It blocks any path to ground for the pin
MOV A, P1
Input signal (1 OR 0) present at input is directed to TB1 which is read!
WHAT HAPPENS IF WE WRITE A 0 TO LATCH AND TRY TO READ A PIN?

MOV P1, #00h

Q=0;=1
Transistor Gate is turned on - Path to ground for both load as well as pin
MOV A, P1

Any attempt to read pin will always get low ground signal!
 To initialize a port pin as an input we must first write a logic 1 to it

e.g. SETB P3.2

Are we initializing P3.2 as input ?
Are we sending an o/p of 1 to P3.2 ?

MOV P2, #0FFH No way of telling if you are sending an o/p or making it
an input port

Only by examining what is connected to P2 would we be able to decipher

this piece of code correctly

LEDs (OUTPUT) - Cannot read the status of LEDs

Switches (INPUT) - We read the status of switches

 READING THE LATCH OR READING THE PIN?

When reading port, there are two possibilities

Reading Latch
Reading Pin

Depends on which instruction we are using

Commands that read Latch use Port/Pin as Destination Operand

ANL P1, A
JBC P1.1, target
INC P1
Activate the Read Latch of TB2
DJNZ P1, target
MOV P1.2 C
CLR P2.3

Commands that read Pin use Port/Pin as Source Operand

MOV A, P1
JB P1.1, target Activate the Read Pin of TB1
MOV C, P1.2
READING THE LATCH
 READ MODIFY - WRITE FEATURE

THREE ACTIONS ARE COMBINED IN A SINGLE INSTRUCTION

READ: CPU reads the latch of Port

CPU performs some Operation

MODIFY: Contents of Latch are Modified

WRITE: Data is written to the pin

 Following Code makes use of Port 1 as an I/p port

MOV A,#0FFH

MOV P1,A

MOV A,P1

MOV R7,A

ACALL DELAY

MOV A,P1

MOV R6,A

ACALL DELAY

MOV A,P1

MOV R5,A
 Following code makes use of P1 as an output port

MOV A,#55H

BACK: MOV P1,A

ACALL DELAY

CPL A

SJMP BACK