Performance of FinFET Based
Adiabatic Logic Circuits
IK. Srilakshmi, 2A. V. N. Tilak, 3K. Srinivasa Rao
12 Gudlavalleru Engineering College, Gudlavalleru, 3TRR College of Engineering, Inole.
I slkaza06@gmail.com, 2 avntilak@yahoo.com, 3 principaltrr@gmail.com
Abstract- The heat removal becomes a problem in modern
VLSI circuits due to increased power dissipation. To limit the
power dissipation adiabatic logic is the most widely used design
technique than standard CMOS logic as it does not dissipate
energy. Till now number of adiabatic logic families had been
implemented using bulk CMOS. The leakage power in the scaled
down bulk CMOS devices reduces the energy recovery efficiency
of adiabatic logic circuits. The power dissipation of different
adiabatic logic families with FinFET devices are compared using
4-bit adder. Due to lower leakage current, higher on-state
current, and design flexibility of FinFETs, the adiabatic 4-bit
adder implemented using FinFET gives up to 97% power
reduction over bulk CMOS circuits.
Keywords--Adiabatic logic; FinFET; U1tralow-power; 4-bit
adder; Energy efficiency
I. INTRODUCTION
Rapid developments in the field of VLSI design
technology have resulted in higher performance and
integration density. Simultaneously, the increasing power
dissipation has become the major obstacle against further
development of VLSI circuits. Power dissipation has two
major components: static and dynamic. The static power is
due to inherent device leakage when the circuit is in the off
state [1] and the dynamic power is caused by charging and
discharging of the capacitive nodes. Till recently the power
consumption was dominated by the dynamic power. Several
low power design technologies like adiabatic [2],
sub-threshold [3] and multi-threshold [4] have been
introduced to reduce dynamic power, among which adiabatic
logic, a novel low-power circuit structure, uses AC supply
rather than constant DC to recycle the energy of circuits.
Theoretically, zero power consumption can be achieved by the
adiabatic logic without considering the leakage power. In
recent years, there has been intensive research on low power
adiabatic logic. A 32x32 register file based on dual
transmission gate adiabatic logic was proposed by Linfeng Li
et aI., [5] that could be applied to a larger memory to reduce
the energy dissipation. Samson and Mandavalli [6] proposed
an energy efficient and high density adiabatic 5T SRAM.
Ultralow-power adiabatic sequential circuits like D, JK,
T flip-flops are explored in [7). It was reported that the
adiabatic logic families have better Differential Power
Analysis (DPA) resistance than the conventional CMOS logic
[8, 9). However, with the consistent scaling of threshold
978-1-5090-2597-8/16/$31.00 2016 IEEE
voltage and device technology, there is a significant increase
in leakage current, contributing to major part of power
consumption [10). So, it is hard to realize efficient bulk
CMOS adiabatic logic circuits due to large leakage currents.
Hence, there is a need to explore novel devices to reduce the
leakage power. Among them, FinFET is proposed as a
favorable alternative for addressing the challenges created by
the continued scaling [II). This device exhibits superior
performance and low-power operation [12). It can suppress
the Short-Channel Effects (SCEs) and the gate-dielectric
leakage current.
This paper compares the performance of bulk CMOS and
FinFET based adiabatic logic 4-bit adder. Four types of
adiabatic logic families, viz., Positive Feedback Adiabatic
Logic (PFAL), Efficient Charge Recovery adiabatic Logic
(ECRL), Clocked Adiabatic Logic (CAL) and Two-Phase
Clocked CMOS Adiabatic Logic (2PC2AL) are considered.
Simulations based on BSIM-CMG model with 45nm bulk
CMOS and FinFETs are carried out on 4-bit adder for
evaluating the performance. The remaining part of this paper is
organized as follows. Section II gives the background of this
work. Simulation results are given in section III. Finally,
section IV contains the conclusion of the paper.
II. BAC KGROUND
A. Adiabatic Logic
Power dissipation in static CMOS circuits occurs mainly
during device switching. In the charging period the energy
consumption from power supply through pull up PMOS block
is C LV DD2 Half of the energy is stored in load capacitor C L and
the remaining half is dissipated in resistive path and converted
into heat. The same amount of energy is consumed during
discharging phase. Adiabatic logic circuits [13] recover the
energy stored in load capacitor and gives back to the power
supply. Theoretically adiabatic logic circuits have zero power
dissipation. So in low power design domain, adiabatic logic is
an attractive technique in the circuit level. Generally, the
adiabatic circuit operation consists of four phases, namely,
wait, evaluate, hold and recover. The widely used adiabatic
logic techniques include PF AL, ECRL, CAL and 2PC2AL.
The circuit topologies of different adiabatic buffers/inverters
are shown in figures 1 to 4. PFAL buffer/inverter is shown in
Fig. 1. The advantage of this logic is that the functional block
is in parallel with PMOS, giving rise to smaller equivalent
resistance through which the capacitor charges [14).
2377
 PClK
PCLK

OUT o---""-i=~_""_Lo OUT OUT

~ CK

G~'D

Fig. l. PF AL buffer/inverter

Fig. 2 shows the ECRL buffer/inverter. ECRL logic family GND

makes use of PMOS transistors for pre-charging purpose [15],
there by offering higher operating speed. CAL buffer/inverter Fig. 3. CAL buffer/in verter
[16] is shown in Fig. 3. The CAL adiabatic logic includes
NMOS transistors, controlled with clock pulses (CK). The
drawback of CAL logic is generation of extra clock signal for
control transistors. Fig. 4 shows the 2PC2AL inverter [17].
The advantage of 2PC2AL logic is that using static CMOS
structure quasi-stable operation under one-phase driving can
be achieved.
"-~O OUT
PCLiK

PClJK

Fig. 4. 2PC2AL inverter

OUTIC'~--~'----J
The front and the back-gates of FinFET, configured in
different ways provides three basic working modes, namely,
Short-Gate (SG) mode, Independent-Gate (IG) mode and
Low-Power (LP) mode. Compared to bulk MOSFETs,
FinFETs offer low-power operation, excellent performance
and flexible working modes. In this paper a 4-bit Brent-Kung
adder is proposed with FinFET device using four adiabatic
logic techniques at 45nm technology node.

Fig. 2 .ECRL buffer/inverter

Oxille
B. FinFET Device
FinFET consists of a thin silicon body, formed
perpendicular to the plane of the wafer. The current flows
parallel to the wafer plane. The channel is wrapped by the gate
electrodes in three directions [18]. Fig.5 illustrates the (al (h,

three-dimensional structure and cross-sectional view of a

FinFET. The device can provide stronger control over the Fig. 5. (a) Three dimensional structure and (b) cross-sectional view of
channel and suppress the Short Channel Effects (SCEs) FinFET
resulting in higher on-state current, lower leakage and faster
switching speed.

2378 2016 IEEE Region 10 Conference (TENCON) - Proceedings of the International Conference
C. Adder Design III. SIMULATION RESULTS

The addition of two binary numbers is the fundamental
arithmetic operation in microprocessors, Digital Signal
Processors (DSP), and data-processing Application-Specific
Integrated Circuits (ASIC). Brent-Kung adder, first proposed
by Brent and Kung in 1982 uses logarithmic concept [19] to
improve the speed. The structure of 4-bit Brent-Kung adder is
shown in Fig. 6. This adder has three stages, namely
pre-processing, prefix carry tree and post-processing. A (0:3)
and B (0:3) are four-bit inputs, S (0:3) is four-bit sum output,
C3 is the final carry, and C1 and C2 are intermediate carry
signals. The use of Brent-Kung adder in adiabatic logic
circuits reduces the delay.
The generate and propagate signals computed in the
pre-processing stage are
To demonstrate the effectiveness of FinFET based adiabatic
logic circuits in lowering the power dissipation and area,
simulations on 4-bit Brent-Kung adder circuits are carried out
using 45nm BSIM-CMG model. The results are compared
with bulk CMOS implementations. The device parameters
chosen for the bulk CMOS are L=45nm, W = 90nm, threshold
voltage = 0.6V, while for the FinFET, L= 45nm, Tfin = 15nm,
Hfin=30nm, Tox= lnm, threshold voltage = O.4V. A sinusoidal
power clock is chosen as the power supply. Simulations are
carried out for different channel lengths and fin thicknesses by
varying the amplitude and frequency of the power clock from
0.5 to l.3V and 1K-100MHz respectively. The width of the
FinFET gate is obtained from the following relation .
(12) ,

P, =A, EBB, (1) where W fin , H fin ' and Tfin are the width, height and
G,=A,. B, (2) thickness respectively of the fin .
Table 1 compares the number of transistors used and area
The carry signals obtained from prefix carry tree are given by occupied for different topologies of the adiabatic 4-bit
C, =G, +~ .Go (3) Brent-Kung adder implemented using bulk CMOS.
C2 =G 2 +P2 .C, (4) T ABLE I. COMPARISON OF DIFF ERENT ADIABATIC LOGIC TECHNOLOGIES
FOR A 4-BIT ADDER USING BULK CMOS
C3 =Ro +Qo .C, (5)
where Qo and Ro are intermediate signals to generate C3 . PFAL ECRL CAL 2PC2AL
No. of
(6)
PMOS 42 42 42 87
(7) transistors
No. of
Post-processing stage is used for generation of sum outputs. NMOS 142 100 184 87
~=~ 00 transistors
S, =P, Eb Go (9) Area
0.745 0.575 0.915 0.705
(J.!m2)
S2 =P2 EB C, (10)
S3 =~ EB C 2 (11)
In this work the adder is designed with the help of gate Fig. 7 shows the variation of power dissipation of bulk
CMOS and FinFET based adder circuits with frequency. The
library having AND, OR and XOR gates, making use of bulk
adder circuits are simulated with power clock amplitude of
CMOS and FinFET based adiabatic logic technologies like
0.7V and frequency ranging from lK-lOOMHz. The 4-bit
PF AL, ECRL, CAL and 2PC2AL. PF AL adder designed with FinFETs dissipates 84% and 97%
Au Po r----------------------------- ~ less power than bulk CMOS circuit in 1K-IMHz and
80 Go r---- --------------------'D-Sl lO-lOOMHz frequency range respectively. The ECRL and
CAL adder circuits gives power saving of 95%, 85% in low
frequency range (lK-lOKHz); 82%, 76% in medium
frequency range (l00K-I0MHz); and 85%, 91% in high
Bl
frequency range (1O-100MHz). respectively.The 4-bit adder
designed with 2PC2AL logic gives rise to maximum power
savings of 76% in low frequency range than all the other logic
families, but the drawback is that it requires two power clock
signals.
Fig. 8 shows the effect of supply voltage scaling on power
dissipation of a PF AL 4-bit adder for different Land T fin
\-----_ c, dimensions at 1 and 100MHz frequencies . About a factor of
two reduction in power dissipation is observed at 1MHz,
when the supply voltage scales down from l.3 to 0.5V.
Maximum reduction by a factor of 2.4 and 1.5 occurs for the
Fig. 6 . Structure of Brent-Kung Adder case of L=45nm and T fin=25nm at 1 and 100 MHz frequencies
respectively.

2016 IEEE Region 10 Conference (TENCON) - Proceedings of the International Conference 2379
 PFAL 4-bit Adder, VDD=O.7V at I and 100MHz, when the supply voltage is changed from
1400 1.3 to O.SV for L=2Snm and Tfin= ISnm.
~ 1 200

-=- 1000
~>= 800
.S-
.; 600 ~ Bulk CM OS
,...
::: 3~O

=300
Q __ FmFET
I. 400
~ 200 ~ :!j O
~ ~"' l ml, TIiIl;o: I ~ 1U11
-5" : 00
~ L-'1 5 Il1n. TIlII-::E I ~ llIn
0.00 1 0.0 1 0.1 10 100 ~ 150
- . - Ir=-* 511111. Tfill= :! ~ lII n
F requenc:), (M Hz) ~ 100
'0
o
(a) I I 0.9 01 o. ~

300 ECRL 4-bir Adde r, VDD=O .7V

(a)

:000
_ _ Bulk CM OS
_ _ FmFET

~ L- ~.5 I1IJ1. Tfill- l ~ 1U1l

L=-Io~UlI L Tfm= l ~ IU I1
0 .00 1 0 .0 1 0. 1 10 100
~L 5111 11, T .i H:l:2 .... 11II1
F r equenc:y (MHz)

900 CAL 4-bit Adder, VDD=O .7V

(b) 1\ I I 09
SUPIJly \ o ll a.~t( \ ')

(b)
0'

J
800
Fig. 8. Effect of supply voltage scaling on power di ssipation ofPFAL
~ 700
4-bit adder at frequency of (a) IMHz a nd (b) IOOMHz
~ 600
.~ 500
.S-
~ 400
~ 100

i
300
90
200
100 [ 80
-0

0.00 1 0.0 1 0. 1 10 100 ~ 60

lO ......... L::: :: ~ 1I1lI Tfill- I ~ nm
Frequenc ~' (MHz) ~
<3 . 0 L "i lllil T li ll 1"' 11111

i
jO
.......- t ,.,---t 'i lllu.TIiII :! ~ 1I 11 1
:0
(c)
10

I \ 1 I 09 0- 0'

2PCl.-u. 4-bit Adde r, VDD=O.7V

~ 200

.
(a)
~ 150

.
.S-
_ _ Bulk CM OS
~ 100 HO
- FmFET
~ 50

0 .00 1 0 .0 1 0. 1 10 100
F requenc:y (M Hz )
___ L- -t -\ l lI lI. Tfili- I ~ I II I I

(d)

Fig. 7. Frequ ency vs power dissipation curves of 4-bit adder u sing bulk 1.1 0.9 0.7 0.5
MOSFET and FinFET at O.7V supply v oltage (a) PFAL (b) ECRL (c) CAL
and (d) 2PC2AL

The supply voltage scaling effect on power dissipation of (b)

4-bit ECRL adder is shown in Fig. 9. In this case the power Fig. 9. Effect of supply voltage sca ling on power di ssipation of ECRL
dissipation decreases by a factor of 2.26 and 1.S respectively 4-bit adder at frequency of (a) IMHz a nd (b) 100MHz

2380 2016 IEEE Region 10 Conference (TENCON) - Proceedings of the International Conference
 Fig. lO shows the effect of supply voltage scaling on circuits are shown in Fig. 12. Various logic families behave
power dissipation of 4-bit CAL adder. Minimum power distincitly for different frequency ranges and FinFET
dissipation is observed for the case of L=45nm and T fin=25nm dimensions.
at 1 and 100MHz frequenies. When the supply voltage is
varied from 1.3 to 0.5V, the power reduces by a factor 1.9 and
1.4 respectively at these frequencies .
SO L- ..a51U1i. TOil - 25m!)
\ 'DO O.-Y
~ -0
Eo 60
~ :e.O . PFAL
.E- ~ O
ECRl
~ 30
... CAL
~ 10
~L I SUlILTrul-> l !'uUl Q. '" 10 . 2PC2AL
L 5 LUI L TCul ....15uUl 0
000 1 00 1 0 1 10 1 0
Fr.qll .... <')' (~ nill

(a)

(a)
-0
L- 25llln. T llu-- l !=-um
60 \,DD ~O . -Y

160 L .:3t. ,ltttt'. r"' I I)(!l\ltfr. ~ ~O

-=-
~" -I _ Pf.~ L

'"
~ 30 EC'RL
- . - L _~ nm , Ttiu""' l 'li11lll is
_ CAL
....-L ~ 1 .1U . TIiII '-' 1 5 11 1l1 ~
Q ~p -' ~ A L
~ L~51'I\lTfil l::!!!l ~ ~ Hm
'" JO

0
I .' 000 1 00 1 10 100
Frf'flu en "'Y( IHzI

(b)
(b)
Fig. 10. E ffect of supply voltage scaling on power dissipation of CAL .----------.---.-.".---._.----.. ---._.---._.-.-- .. -------. ---------------------------._----------------------------..,
4-bit adder at frequency of (a) I MHz a nd (b) 100MHz ,,
The behaviour of 4-bit 2PC2AL adder with change in L ~ ~ Uln T fill L ~lIm
,
70 i
\ 'D~o . -y
supply voltage is shown in Fig.l1. For L=45nm and
~ 60
T fin= 15nm the power dissipation of this adder is an order of
100 more than that for other FinFET dimensions. In all the ~ 50

three cases, the power dissipation decreases by a factor ~ 40

1.1with supply voltage scaling. '"

~ 30
PF.-\L

15 fil E
;; 20

14000 2PCl.-\L Adder

10
AL

o i
~ 12000
I
-!.. 10000 fi't"(lut':nry (h IHt) j
~ 8000 ________________________________________________________ A _________________________________________________________ ~
.ii-
.S 6000 -eo- L-25nrn, TfuI- 1 5mn
Q (c)
... 4000 - - L-.l 5nm. T..-1 5nm
..! 2000
~ L-.:l 5run, TWl- 25run
Fig. 12. Power di ssipation of FinFET based adiabatic 4-bit adders with
(a) L=45nm , Tfi"=25nm, (b) L=25nm , Tfi"= 15nm and (c) L=45nm, Tfin= 15nm.
1.3 1.1 0 .9 0 .7 O.S
Supply 'oha,. (\) IV. CONCLUSION
In this paper, the performance of bulk CMOS and FinFET
Fig . II. Effect of supply voltage scaling on power dissipation of2 PC2AL
4-bit adder based PF AL, ECRL, CAL and 2PC2AL adiabatic logic
familes are compared by designing and simulating a 4-bit
The variation of power dissipation with frequency and Brent-Kung adder. The results indicate that power savings of
FinFET dimensions for all the four adiabatic logic adder 76 to 97% can be achieved by replacing

2016 IEEE Region 10 Conference (TENCON) - Proceedings of the International Conference 2381
 bulk CMOS with FinFET. The effect of supply voltage scaling [14]. A Vetuli, S D Pascoli and L M Reyneri, "Positive feedback in
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pp.1867-1869.
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2382 2016 IEEE Region 10 Conference (TENCON) - Proceedings of the International Conference