Field Effect Transistors

Electronics 2
Instructor: Armando V. Barretto

References
• Electronic Devices and Circuit Theory by Boylestad and
Nashelsky
• Electronic Principles by Albert Malvino and David Bates
Grading System
Final Grade = (Q1+Q2+Q3+Q4+2FE+2PE)/8
Passing Grade=>60
Field Effect Transistor (FET)
Field Effect Transistor
• FET is generally a three terminal device which could be used in applications
wherein bipolar junction transistors are used.
• It is a voltage controlled device as compared to a BJT which is a current
controlled device.
– Output voltages and currents are controlled by the input voltage rather
than by the input current.
• The term field effect is used because for FETs, an electric field established by
the carriers controls the conduction path of the output current without the
need for direct contact between the input signal parameters and the output
signal parameters.
• It is a unipolar device because current flow is only dependent on either
electron flow (n channel) or hole flow (p channel).
– BJT is a bipolar device because current flow is always dependent on
electron flow (n material) and hole flow (p material).
FET and BJT Comparison
• FETs have very high input impedance (1 Mohm or higher), because the p-n
junction at the input is operated in the revere bias condition. This is higher
than those of BJTs.
• FETs are more temperature stable compared to BJTs.
• FETs are usually smaller than BJTs making them useful in integrated
circuits.
• FETs are less sensitive to changes in the applied signal compared to BJTs,
resulting to smaller voltage gains than BJT voltage gain.
• FETs are usually more sensitive to handling compared to BJT.
Basic Types of FET
• The three basic types of FET are:
– Junction field effect transistor (JFET)
– Metal oxide semiconductor field effect transistor (MOSFET), which
has two types:
• Depletion MOSFET
• Enhancement MOSFET
– Metal semiconductor field effect transistor (MESFET)
• FETs could also be classified as n-channel FET and p-channel FET.
• The n-channel FET is more dominant than the p-channel FET.
Junction Field Effect Transistor JFET
• JFETs have three terminals: Gate, Drain and the Source.
• The Gate is used to control the flow of current flowing through the drain and
the source.
• The drain current is the same as the source current. Both currents flow
through the channel of the FET.
• The construction of an n-channel and that of p-channel JFET are shown
below: Drain (D) Drain (D)
ID = drain current ID = drain current
Depletion Depletion Depletion Depletion

region n region region p region
p p n n
Gate (G) Gate (G)
n p
IS = source current IS = source current

Source (S) Source (S)
N-channel JFET P-channel JFET
• The drain and the source are connected to both ends of the n type material
for n-channel, and to both ends of the p-type material for p-channel.
• The drain current and source current are equal in value.
• Drain and source current flows through the channel.
• The gate is made up of two materials which are internally connected.
• The channel is sandwiched between the two gate materials.
• Two depletion regions exist between the n-type materials and p-type
materials.
– The depletion region is void of carriers, thus no current could flow in the
depletion region.
– If the depletion region increases in width, less current could flow
through the channel, thus the drain and source current will be lower.
– The width of the depletion region can be increased by increasing the
reverse bias voltage between the gate and the source and between the
gate and the drain.
– Thus the drain current and source current can be controlled by changing
the reverse bias voltage between the gate and the source and between the
gate and the drain.
• For an n-channel JFET - When voltage between the gate and source (VGS) is
0 volt, and the voltage between the drain and the source (VDS) is positive at
the Drain, the following conditions exist:
– Depletion region between the Gate and the Drain is wider than the
depletion region between the Gate and the Source, because the p-n
junction between the Drain and the Gate is more reverse biased than the
p-n junction between the Gate and the Source. 9v
Drain (D) Drain (D) ID = Drain

ID = Drain
current current
Depletion
Depletion Depletion
Region
Region (wider Region VDD n 6v
near Drain) n (wider
near Drain) 9v Gate (G)
Gate (G) p p
p p
IG (Gate VDS
Current) n VGS n
VGS 3v
=0
Source Source
IS = Source current (S) IS = Source
(S) current
N-channel JFET with VGS= o volt and VDS is positive at the Drain
– Conventional current flows from Drain to Source through the channel,
and the current is only limited by the resistance of the n-channel between
the drain and the source.
– Drain current (ID) is equal to the Source current (IS).
– When Drain to Source voltage (VDS) increases, Drain current (ID) and
Source current (IS). also increase until VDS reaches the pinch off voltage
(Vp).
– When VDS increases beyond VP, Drain current (ID) does not increase and
practically remains at a constant saturation level called IDSS.
• This indicates that the Drain to Source resistance is approaching an
“infinite” value, as any increase in VDS does not result in an increase
in Drain current.
• This is caused by both depletion regions becoming very wide that they
“touch” each other, and that they almost close the n-channel (small
current path still exists).
• As the Drain to source voltage (VDS) increases beyond Vp, the region
of close contact between the two depletion region increases.
– IDSS is the maximum Drain current (Source current also, ID=IS) for the
JFET when VGS = 0 volt and VDS > |VP|, as long as VDS does not reach the
breakdown voltage.
– When VDS reaches the maximum allowed value (breakdown voltage –
VDS max , Drain current becomes very high and the FET could be damaged.
– For low values of VDS (VDS < VP) , resistance from drain to source is
relatively constant. In this region, JFET can be used as a constant
resistance source.
– Gate current (IG) is equal to zero because the p-n junctions are reverse
biased.
– For p-channel JFET, the same conditions exist, except the polarity of the
Drain to Source voltage (VDS) is reversed, and the direction of the Drain
current (IDS) is also reversed.
Ohmic Saturation region Breakdown

region region
ID (mA)
Saturation Level
(IDSS) VGS = 0 v
Drain
saturation
current
N-channel resistance (constant)
VDS (V)
Vp
(pinch off
voltage)
ID (mA)
JFET Characteristic Curve When VGS = 0 volt
• The Drain current is typically controlled by varying the Gate to Source
voltage (VGS).
• When VGS is more negative than the Source (for n-channel) and the Drain to
Source voltage (VDS) is positive at the Drain, the following conditions exist:
– Gate to Source voltage (VGS) is more reverse bias than when Gate to
Source voltage is equal to zero.
9v
Drain (D) Drain (D) ID = Drain

ID = Drain
current current
Depletion
Depletion Depletion Region
Region n Region VDD n
Gate (G) 9v Gate (G)

p p p p
Depletion
IG (Gate Region (wider VDS
Current) than when
=0 VGS n
VGS n VGS= 0 v)
VGG Source Source
IS = Source current (S) IS = Source
(S) current
N-channel JFET with VGS= o volt and VDS is positive at the Drain
– The depletion region between the Gate and the Source is wider than when
the Gate to Source voltage is equal to zero.
– As the Gate to Source voltage becomes more negative at the Gate, the
saturation level of the Drain current decreases and saturation level occurs
at lower values of VDS.
• This is because the two depletion regions come into contact with each
other earlier than when the Gate to Source voltage is zero.
• The pinch off voltage (Vp) drops in a parabolic manner as VGS
becomes more and more negative.
• Eventually, the Drain current becomes equal to zero when VGS
becomes equal to the pinch off voltage (Vp) for that particular
condition. (Vp changes as VGS change). This particular Vp is also
called VGS (off) .
• When VGS becomes equal to VGS (off), the JFET is turned “off”.
– Gate current (IG) is equal to zero all throughout, because the two p-n
junctions are always reverse biased.
– The above conditions also exist for p-channel JFET, except that the
voltages are reverse in polarity and currents are opposite in direction.
Junction Field Effect Transistor (n-channel JFET)
Characteristic Curve
Saturation region
Locus of pinch off Breakdown

voltages (VDS >=VDS max)
Saturation Levels for ID
Ohmic
ID (mA) region
(IDSS) VGS = 0 v
Drain
saturation VGS = -1 v
current for
VGS = 0 v Breakdown
VGS = -2 v region
VGS = -3 v
VGS = -4 v
ID = 0 mA VDS (V)
5 10 15 VGS = -5 v (VGS off
In this case)
Vp
(pinch off
Voltage for
VGS = 0 v)
ID (mA)
N-Channel JFET Characteristic Curve For Different Values of VGS

Junction Field Effect Transistor (p-channel JFET)
Characteristic Curve
Saturation region
Locus of pinch off Breakdown

voltages (VDS >=VDS max)
Saturation Levels for ID
Ohmic
ID (mA) region
(IDSS) VGS = 0 v
Drain
saturation VGS = 1 v
current for
VGS = 0 v Breakdown
VGS = 2 v region
VGS = 3 v
VGS = 4 v
ID = 0 mA VDS (V)
-5 -10 -15 VGS = 5 v (VGS off
In this case)
Vp
(pinch off
Voltage for
VGS = 0 v)
ID (mA)
P-Channel JFET Characteristic Curve For Different Values of VGS

Junction Field Effect Transistor (JFET) Characteristic Curve
• The characteristic curve of JFET has three regions which are: Ohmic
region, Saturation region, and breakdown region.
• The ohmic region is the region where the JFET resistance is constant for a
particular value of VGS.. It is also called voltage controlled resistance
region. In this region,
– The JFET can be used as a variable resistance device, such as those
used in Automatic Gain Control (AGC).
– The resistance between the Drain and the Source is a function of VGS.
– The resistance between the source and the drain in this region can be
approximated by:
ro
rd = = Drain to Source Resistance (ohms)
(1 − VGS/Vp )2
where : ro = Drain resistance when VGS = 0 volt

VGS = Gate to Source voltage (volt)
Vp = Pinch off voltage when ID = 0 = VGS off (volt)
Junction Field Effect Transistor (JFET) Characteristic Curve
• The saturation region is located at the right side of the locus of pinch off
voltages. It is also called constant current or linear amplification region. In
this region,
– the JFET can act as a constant current source, since any variations in VDS
does not result to changes in Drain current (IDSS).
– the JFET is typically employed as linear amplifier.
• The breakdown region is the region when the maximum Drain to Source
voltage (VDS max) is reached. In this region,
– Drain current becomes very high
– JFET could be damaged
– Drain current is limited by circuit components external to the JFET.
• As seen in the characteristic curve,
– ID ranges from 0 A to IDSS for all levels of VGS between 0 v and pinch off
voltage VGS(off) .
– IDSS is the maximum current and it occurs when VGS = 0 v.
Junction Field Effect Transistor (JFET) Schematic Symbols
• The schematic symbols for n-channel and p-channel JFET are shown below:
+ -
ID ID
Drain (D) Drain (D)
Gate (G) Gate (G) VDS

- VDS +
VGS Source (S) VGS Source (S)

IS IS
+ -
- +
n-channel JFET p-channel JFET
• Current direction and polarity of voltages are for typical JFET configuration.
• For typical biasing,
– Drain current is equal to the Source current.
– Gate to Source p-n junction and Gate to Drain p-n junction are reverse
biased.
– Gate current is equal to zero because both p-n junctions are reverse biased.
– Input signal is at the gate and output is taken from the drain or source.
Junction Field Effect Transistor (JFET) Typical Biasing
• Typical biasing for n-channel and p-channel JFET are shown below:
ID = Drain ID = Drain
current current
Drain (D) Drain (D)

Gate (G) Gate (G)
VDS VDS
IG (Gate IG (Gate
Current) Current)
=0 VGS =0 VGS
IS = Source IS = Source
VGG Source current VGG Source current
(S) IS=ID (S) IS=ID
Typical Biasing for n-channel JFET Typical Biasing for p-channel JFET
Junction Field Effect Transistor (JFET) Transfer
Characteristics
• The relationship between drain current (ID) and the VGS is defined by Shockley’s
equation shown below:
2
 VGS 
ID = IDSS 1 −  = Drain current (Ampere)
 VP 
where : IDSS = Saturation Drain current when VGS = 0 v (Ampere)
VGS = Gate to Source voltage (volts)
VP = VP(off) = VGS off = Pinch off voltage when ID = 0 ampere (volts)
• The transfer characteristics defined by Shockley’s equation are unaffected by

circuit components external to the JFET.
– The network equation may change but the transfer function is unaffected.
• The squared term in the equation results to nonlinear relationship between
Drain current and VGS.
• When VGS = Vp (off) = VGSoff , ID is equal to zero.
• When VGS = 0 volt, ID = IDSS.
Characteristics
• Example: Given IDSS = 8 mA, Vp = Vp (off) = -4 volt, n-channel JFET,
determine: ID when VGS = 0 volt, VGS = - 1 volt, VGS = -2 volts, VGS = -3
volts, VGS = -4 volts.
2
 VGS 
ID = IDSS 1 −
 VP  Be careful in applying the signs
2
 0 in the voltages, as this could result
ID = 8 x 10 −3 1 −  = 8 mA to wrong computations.
 - 4
2
 -1 
ID = 8 x 10 −3 1 −  = 4.5 mA For p-channel JFET, the same equation
 - 4 can be used, but the values of VGS
2 and VP are both positive.
−3  - 2
ID = 8 x 10 1 −  = 2 mA
 - 4
2
 -3
ID = 8 x 10 −3 1 −  = 0.5 mA
 - 4
2
 - 4
ID = 8 x 10 −3 1 −  = 0 mA
 - 4
Characteristics
• Shockley’s equation can be used to determine ID for specific ratios of VGS and
VP.
When VGS = 0 ⇒ ID = IDSS
2
 0.3VP  IDSS
When VGS = 0.3VP ⇒ ID = IDSS 1 − =
 VP  2
2
 VP/2  IDSS
When VGS = 0.5 Vp ⇒ ID = IDSS 1 − =
 VP  4
When VGS = Vp ⇒ ID = 0
• The above results could be used to approximate the transfer characteristic

curve of JFET whether n-channel or p-channel.
N-Channel Junction Field Effect Transistor (JFET) DC
Analysis Using Graphical Approach
• DC analysis for JFET can be done using graphical approach as shown below:
Ohmic Saturation region
region
Locus of pinch off
(IDSS) voltages Breakdown
ID (mA) ID (mA) (VDS >=VDS max)
ID= 8mA=IDSS 8 8 VGS = 0 v

7 7
6 6
5 5 VGS = -1 v
4 4 Breakdown
3 3 region
2 2 VGS = -2 v
1 1 VGS = -3 v
ID = 0 mA VDS (V)
VGS 2 4 6 VGS = - 4 v =Vp
(volt) -4 -3 -2 -1 0 = (VGS off
Vp
In this case)
(pinch off
ID= 0mA Voltage for
VGS = 0 v)
ID (mA)
N- Channel JFET DC Analysis Using Graphical Approach
N-Channel Junction Field Effect Transistor (JFET) DC
Analysis Using Graphical Approach
• The transfer curve can be obtained using Shockley’s equation.
• The graphs consist of two plots, one plot is ID versus VDS and the other plot
is ID versus VGS .
– VGS = 0 volt, ID = IDSS
– ID and VDS are output quantities
• As shown in the curve,
– When VGS = 0 volt, ID = IDSS
– When VGS = -4 volt = Vp = Vp (off), ID = 0 mA
• To determine the value of ID (output) for a certain value of VGS (input),
– Draw a vertical line at the left graph passing though VGS.
– Draw a horizontal line from the intersection of the vertical line and curve
drawn using Shockley’s equation up to the axis for ID.
– Get the value of ID.
• For p-channel JFET, the same procedures can be used, but the values of VP
and VGS are positive.
Junction Field Effect Transistor (JFET) Power Dissipation
• The power dissipated in a JFET could be computed as:
PD = (VDS)(ID) = power dissipated (watts)

where : VDS = Drain to Source voltage (rms) (volt)
ID = Drain current (rms) (Ampere)
• The power dissipated by a JFET must not exceed its maximum allowable
value or the JFET could be destroyed.
• The maximum power which a JFET could have must be derated as the
operating temperature increases.
• The maximum allowable power dissipation decreases as the temperature of
the JFET increases.
• Derating value is given in specification sheets.
• A derating value of 2 miliwatt per 0C means the maximum power dissipation
of the JFET must be reduced by 2 miliwatts for every degree centigrade
increase in operating temperature.
Junction Field Effect Transistor Linear Operating Region
• The area bounded by the green lines/curves below is the linear operating
region of a JFET. This region is typically used when a JFET is used as a
linear amplifier.
Ohmic Breakdown
region Saturation region region
Saturation
Locus of Level
pinch off for ID when
voltages VGS= 0 v
ID (mA) PDS max
(IDSS)
Drain
Breakdown
saturation
(VDS =VDS max)
current for Linear Operating
VGS = 0 v region
VGS = VGS off = Vp
(pinch off
Voltage
ID = 0 mA VDS (V)
VDS max
JFET Linear Operating Region

Typical Junction Field Effect Transistor (JFET)
Parameters
• The following are typical JFET parameters usually given in specification
sheets.
Maximum Ratings: (Should not be exceeded or JFET could be destroyed)

– Maximum Drain to Source voltage (VDS max)
– Maximum Drain to Gate voltage (VDG max)
– Maximum Reverse Gate to Source voltage (VGSR max or BVDSS.) - BVDSS is
the breakdown voltage with Drain to Source Shorted)
– Maximum Gate current (IG max)
– Maximum Total Power Dissipation (PD max) - (Power dissipated =
PD=IDVDS)
– Maximum Junction Temperature Range (TJ)
– Storage Channel Temperature Range (Tstg)
On Characteristics: (When JFET has Drain current is greater than zero)

– Zero-Gate-voltage Drain Current (IDSS) – (ID when VGS= 0 v)
Typical Junction Field Effect Transistor (JFET)
Parameters
Off Characteristics:
– Gate-Source Breakdown voltage (V(BR)GSS)
– Gate Reverse Current (IGSS) – Gate current when p-n junctions are
reverse biased.
– Gate Source Cut off voltage (VGS (off) = VP) – (VGS when ID = 0)
Small Signal Characteristics:

– Forward Transfer Admittance Common Source (Yfs)
– Output Admittance Common Source (YOS)
– Input capacitance (Ciss)
– Reverse Transfer Capacitance (Crss)
• Usually, the values in the specification sheets has a minimum, typical and
maximum value. This must be considered in the design of JFET circuits.
Metal Oxide Semiconductor Field Effect Transistor
(MOSFET)
• MOSFET is one of the most important device in the construction of
integrated circuits, such as those used in digital electronics / computers.
• MOSFETs have the following advantages:
– better temperature stability compared to BJT
– very high input impedance compared to BJT.
• MOSFETs have the following disadvantages:
– It is more sensitive to static electricity which necessitates more care in
handling the device.
– It has lower power handling levels compared to BJT.
• MOSFETs are categorized as depletion type or enhancement type.
Depletion Type MOSFET
• Depletion type MOSFET has the same characteristics as JFET between cutoff
and saturation at IDSS.
• Another name for depletion-type MOSFET is Insulated Gate FET or IGFET.
• It has the added feature of being able to operate with positive and negative
values of VGS. (Unlike JFET which could operate only with negative values of
VGS for n-channel and positive values for p-channel).
• The basic construction of a n-channel depletion type MOSFET is shown
below.
SiO2 (insulator)
n-doped region
n-channel
Drain (D) n
Metal contacts
p Substrate (SS)
Gate (G) n (Silicon
SiO2 (insulator) substrate)
Source (S) n
N-Channel Depletion Type MOSFET Construction

N-Channel Depletion Type MOSFET Construction
• A slab of p-type silicon material is used as the substrate.
• A substrate is the foundation on which a semiconductor device is
constructed.
• In some devices, the substrate is internally connected to the Source, while in
others, the substrate has a separate terminal called Substrate (SS).
• The Drain, Source, Gate and Substrate terminals are connected through
metallic materials.
• The Drain and Source are connected to n-type materials which are linked
through another n-type material.
• The gate is connected to a Silicon dioxide (SiO2) insulating material, and
therefore has no current for DC signals.
• The Silicon dioxide also acts as a dielectric which sets up opposing electric
field within the material when an external electric field is applied across the
material.
• The MOSFET name is derived from metal contacts of the terminals, Silicon
dioxide insulating material, and semiconductor structure of the device.
• For p-channel depletion type MOSFET, the construction is the same, except
the p-type materials are replaced by n-type, and vice versa.
N-Channel Depletion Type MOSFET Operation
• When the gate is at zero potential relative to the source, and the Drain has a
positive potential relative to the Source, the following conditions exist:
– Free electrons at the n-type materials are attracted to the positive terminal
of VDD, resulting to a current flow at the drain and the source (ID and IS).
– ID is equal to saturation current IDSS.
– IS is equal to ID.
– There is no current at the Gate.
ID Drain
(D)
n
Substrate
IG =0 (SS)
p
n
Gate (G)
Source n
(S) VDD
IS = ID = IDSS
• When the gate has a negative potential relative to the source and the Drain has
a positive potential relative to the Source, the following conditions exist:
– Electrons at the n-type channel will be repelled towards the p-type
substrate and holes at the p-type substrate will be attracted towards the
Gate.
– The electrons at the n-channel will recombine with the holes from the p-
substrate, resulting to lower Drain and Source current.
– The higher is the negative voltage at the gate, the higher is the
recombination rate, and the lower is the Drain and Source current.
Drain
ID (D)
n holes
Substrate Recombination of holes
IG =0 e + (SS) and electrons occur at
e p
+ the channel, resulting to
Gate (G) e lower ID and IS.
n +
Source n
electrons VDD
VGG (S)
IS
• When the gate has a positive potential relative to the source and the Drain has
– Electrons at the p-type substrate will be attracted towards the n-channel
because of the leakage current and establish new electron carriers at the n-
channel.
– The electrons from the p-type substrate will produce higher Drain and
Source current.
– The higher is the positive voltage at the gate, the higher is the number of
electrons attracted to the Gate, and the higher is the Drain and Source
current. Drain
ID (D)
n electrons
Substrate Free electrons from the
IG =0 e (SS) substrate are attracted to
e p
the n-channel resulting
Gate (G) e to higher ID and IS.
n
Source n
VGG (S) VDD
IS
N-Channel Depletion Type MOSFET Characteristic Curve
• The characteristic curve for n-channel depletion type MOSFET is shown
below.
Depletion Mode Enhancement Saturation region Breakdown Region
Mode (VDS >=VDS max)
ID (mA)
ID (mA)
12 VGS = 1 v
11 Enhancement
10 Locus of pinch off Region
9 (IDSS) voltages (VGS>0volt)
7 7
6 6
5 5 VGS = -1 v Depletion
4 4 Region
3 3 (VGS<0volt)
2 2 VGS = -2 v
1 1 VGS = -3 v
VDS (V)
VGS 2 4 6 VGS = - 4 v =Vp
(volt) -4 -3 -2 -1 0 +1 ID = 0 mA = (VGS off
Vp
In this case)
(pinch off
ID= 0mA ID (mA) Voltage for
VGS = 0 v)
N- Channel Depletion Type MOSFET Characteristic Curve
N-Channel Depletion Type MOSFET Characteristic Curve
• The characteristic curve for depletion type MOSFET is similar to that of
JFET except that positive values of VGS are also present for n-channel and
negative values are also present for p-channel.
– When VGS is equal to Vp (VGS (off)), IDS is equal to 0 A.
– When VGS is equal to 0 v, IDS is equal to IDSS.
• The region for positive VGS is called enhancement region because in this
region, Drain current is increased (“enhanced”) due to the attraction of free
electrons from the p substrate to the n-channel.
• The region for negative VGS is called depletion region because in this region,
Drain current is lessened due to the recombination of electrons at the n-
channel and the holes coming from the p substrate.
• The depletion type MOSFET still follows Shockley’s equation for the Drain
current, both for positive and negative values of VGS.
– Proper sign of VGS must be carefully considered when using Shockley’s
equation.
• The characteristic curve for p-channel depletion type MOSFET is the same
as that of n-channel , but the direction of ID is reversed, the positive values of
VGS will be negative, and negative values of VGS will be positive, because the
polarity of VDD and VGG will be reversed.
P-Channel Depletion Type MOSFET Construction
• The basic construction of a depletion type MOSFET is shown below.
• The construction is the same as that of n-type, but the location of the p-type
and n-type materials are interchanged.
SiO2 (insulator)
p-doped region
p-channel
Drain (D) p
Metal contacts
n Substrate (SS)
Gate (G) p (Silicon
Source (S) p
P-Channel Depletion Type MOSFET Construction

P-Channel Depletion Type MOSFET Operation
negative potential relative to the Source, the following conditions exist:
– Holes at the p-type materials are attracted to the negative terminal of VDD,
resulting to a current flow at the drain and the source (ID and IS). Direction of
Drain and Source current is opposite that of n-channel.
– ID is equal to saturation current IDSS.
– IS is equal to ID.
– There is no current at the Gate because it is connected to an insulator.
ID Drain
(D)
p
Substrate
IG =0 (SS)
n
p
Gate (G)
Source p
(S) VDD
IS = ID = IDSS
a negative potential relative to the Source, the following conditions exist:
– holes at the p-type channel will be repelled towards the n-type substrate and
electrons at the n-type substrate will be attracted towards the Gate.
– The holes at the p-channel will recombine with the electrons from the n-
substrate, resulting to lower Drain and Source current.
– The higher is the positive voltage at the gate, the higher is the
recombination rate, and the lower is the Drain and Source current.
Drain
ID (D) holes
p
Substrate Recombination of holes
IG =0 + e and electrons occur at
e n (SS)
+ the channel, resulting to
Gate (G) e
+ lower ID and IS.
p
Source p
electrons VDD
(S)
IS
• When the gate has a negative potential relative to the source and the Drain has
– Holes at the n-type substrate will be attracted towards the p-channel
because of the leakage current and establish new hole carriers at the p-
channel.
– The holes from the n-type substrate will produce higher Drain and Source
current.
– The higher is the negative voltage at the gate, the higher is the number of
holes attracted to the Gate, and the higher is the Drain and Source current.
Drain
ID (D)
p holes
Substrate Holes from the
IG =0 + (SS) substrate are attracted to
+ n
the p-channel resulting
Gate (G) p
+ to higher ID and IS.
Source p
(S) VDD
IS
P-Channel Depletion Type MOSFET Characteristic Curve
• The characteristic curve for p-channel depletion type MOSFET is shown
below.
ID (mA)
ID (mA)
12 VGS = -1 v
11 Enhancement
9 (IDSS) voltages (VGS<0volt)
7 7
6 6
5 5 VGS = 1 v Depletion
4 4 Region
3 3 (VGS>0volt)
2 2 VGS = 2 v
1 1 VGS = 3 v
VDS (V)
VGS 2 4 6 VGS = 4 v =Vp
(volt) +4 +3 +2 +1 0 -1 ID = 0 mA = (VGS off
Vp
In this case)
(pinch off
VGS = 0 v)
P- Channel Depletion Type MOSFET Characteristic Curve
Depletion Type MOSFET Schematic Symbols
• The schematic symbols for depletion type MOSFET are shown below:
+ -
ID ID
Drain (D) Drain (D)
Substrate Gate (G) Substrate V
Gate (G) (SS) VDS (SS) DS

VGS IS VGS IS
- +
n-channel Depletion Type p-channel Depletion Type
MOSFET MOSFET
+ -
ID ID
Drain (D) Drain (D)
Gate (G) VDS

Gate (G) VDS
VGS Source (S) Source (S)

IS VGS I
S
- +
n-channel Depletion Type p-channel Depletion Type
MOSFET MOSFET
Depletion Type MOSFET Parameters
• The following are typical depletion Type MOSFET parameters usually given
in specification sheets.

– Maximum Gate to Source voltage (VGS max.)
– Maximum Drain current (ID max)
PD=IDVDS)
On Characteristics: (When JFET has Drain current)

– Zero-Gate-voltage Drain Current (IDSS) – (ID when VGS= 0 v)
– On state Drain current (ID on) –Drain current for a given value of VDS and
VGS.
– Drain-Source Breakdown voltage (V(BR) DSX)
– Gate Reverse Current (IGSS) – Gate current when p-n junctions are
reverse biased.
– Gate Source Cut off voltage (VGS (off) = VP) – (VGS when ID = 0)
– Drain-Gate reverse current (IDGO)

– Output Admittance (YOS)
– Input capacitance (Ciss)
Functional Characteristic
– Noise Figure (NF)
• Usually, the values in the specification sheets has a minimum, typical and
maximum value. This must be considered in the design of MOSFET circuits.
Enhancement Type MOSFET
• The characteristics of enhancement type MOSFET are quite different from
those of depletion type MOSFET.
• Unlike depletion type MOSFET, the transfer characteristic is not defined by
Shockley’s equation.
• The Drain current is zero (cut off) until the gate to source voltage (VGS)
reaches a specific magnitude.
• For n-channel enhancement type MOSFET, current control at the Drain is
now done using positive voltages at the Gate, rather than negative voltages
used in n-channel JFET and n-channel depletion type MOSFET.
• For p-channel enhancement type MOSFET, current control is also opposite
that of p-channel JFET and p-channel depletion type MOSFET.
N-Channel Enhancement Type MOSFET Construction
• The construction of an n-channel enhancement type MOSFET is shown
below.
• The construction of n-channel enhancement type MOSFET is similar to that
of n-channel depletion type MOSFET, except that there is no n-channel
connecting the n-type regions at the Drain and the Source
SiO2 (insulator)
n-doped region
no channel
Drain (D) n
Metal contacts
p Substrate (SS)
Gate (G) (Silicon
Source (S) n
N-channel Enhancement Type MOSFET

N-Channel Enhancement Type MOSFET Construction
• A slab of p-type silicon material is used as the substrate.
metallic materials.
• The Drain and Source are connected to n-type materials which are linked
through the p-type substrate (no n-channel).
material.
• For p-channel depletion type MOSFET, the construction is the same, except
the p-type materials are replaced by n-type, and vice versa.
N-Channel Enhancement Type MOSFET Operation
positive potential relative to the Source, the following conditions exist:
– Since there is no n-channel and the p-n junction at the Drain is reverse
biased, ID and IS are practically zero. (different from JFET and depletion
type MOSFET where ID = IDSS)
ID=0 Drain
(D)
n
Substrate
IG =0 (SS)
p
Gate (G)
Source n
(S) VDD
IS = ID = 0
– Electrons at the p-type substrate will be attracted towards the Gate and
holes at the p-type substrate will be repelled towards the substrate
terminal, thus producing free electrons at the area between the n-type
materials at the Drain and the Source.
– If the positive Gate voltage is high enough to attract a substantial number
of free electrons, an n-type channel is produced in the area between the two
n-type materials.
– The creation of an n-type channel results to current flow at the Drain and
the Source.
– The higher is the positive voltage at the gate, the higher is the number of
electrons attracted to the Gate, and the higher is the Drain and Source
current.
– The level of VGS that results to significant increase in ID is called Threshold
voltage (VT or VGS (TH)).
– If VGS =< VT , ID is equal to zero.
– Gate current is still equal to zero because of the insulating material.
– If VGS is held constant at a positive value and VDS is increased positively, ID
will eventually reach a saturation level (VDS sat), and ID will not increase
even if VDS is increased.
• The saturation is due to pinching off of the channel (narrower channel)
near the Drain.
• If VDS is continuously increased after saturation has been reached, it will
eventually reach a breakdown value (VDS max) and ID will rise abruptly.
– Since there is no n-channel when VGS is equal to zero, and an n-channel is
created (enhanced) when VGS=VT, the device is called n-channel
enhancement type MOSFET. N-channel is created here
Drain if positive VGS is high
ID (D) enough (VGS > VT)
n
Substrate
IG =0 e + (SS)
e
Gate (G) +
e
+ p
Source n
Holes VDD
(S) electrons
IS
– The saturation level for VDS (VDS sat) can be computed as:
VDSsat = VGS − Vgs (Th) = Drain to Source voltage saturation level (volts)
where : VGS = Gate to Source voltage (volts)
Vgs (Th) = Gate to Source Threshold voltage (volts)
– Different saturation level for VDS exist for different levels of VGS.
– The greater is the value of VGS, the greater is the saturation level for
VDS.
– For levels of VGS <= VT, the drain current (ID) is equal to zero.
– For levels of VGS > VT, the drain current (ID) can be computed as:
ID = k(VGS − VGS(Th)) 2 = Drain current = Source current (Amp)

VGS(Th) = Gate to Source Threshold voltage (volts)
k = constant and a function of a particular device (Amp/volt 2 )
– Above equation shows that there is a non-linear relationship between the

Drain current and Gate to Source voltage.
N-Channel Enhancement Type MOSFET Characteristic
Curve
• The characteristic curve for n-channel enhancement type MOSFET is shown
below.
Saturation region Breakdown Region
(VDS >=VDS max)
ID (mA)
ID (mA)
12 12
11 11
10 10 VGS = 8 v
9 9 Locus of VDS sat
8 8
7 7 VGS = 7 v
6 6
5 5 VGS = 6 v
4 4
3 3 VGS = 5 v
2 2
1 1 VGS = 4 v
VGS = 3 v
VGS VDS (V)
0 (volt) 4 8 12
1 2 3 4 5 6 7 8 VGS = VT= 2 volt
in this case
VGS = VT=VGS(th)= 2 volt ID = 0 mA
in this case

P-Channel Enhancement Type MOSFET Construction
• The construction of a p-channel enhancement type MOSFET is similar to that
of an n-channel, but the p and n materials are reversed.
• A slab of n-type silicon material is used as the substrate.
metallic materials.
• The Drain and Source are connected to p-type materials which are linked
through the n-type substrate.
material.
P-Channel Enhancement Type MOSFET Construction
• The construction of an p-channel enhancement type MOSFET is shown
below.
SiO2 (insulator) p-doped region
no channel
Drain (D) p
Metal contacts
n
Gate (G) (Silicon Substrate (SS)
Source (S) p
P-channel Enhancement Type MOSFET

P-Channel Enhancement Type MOSFET Operation
negative potential relative to the Source, the following conditions exist:
– Since there is no p-channel and the p-n junction at the Drain is reverse
biased, ID and IS are practically zero. (different from JFET and depletion
type MOSFET where ID = IDSS)
ID=0 Drain
(D)
p
Substrate
IG =0 (SS)
n
Gate (G)
Source p
(S) VDD
IS = ID = 0
• When the gate has a negaive potential relative to the source and the Drain has
– Holes at the n-type substrate will be attracted towards the Gate and
electrons at the n-type substrate will be repelled towards the substrate
terminal, thus producing holes at the area between the p-type materials at
the Drain and the Source.
– If the negative Gate voltage is high enough to attract a substantial number
of holes, a p-type channel is produced in the area between the two p-type
materials.
– The creation of an p-type channel results to current flow at the Drain and
the Source.
– The higher is the negative voltage at the gate, the higher is the number of
holes attracted to the Gate, and the higher is the Drain and Source current.
– The level of VGS that results to significant increase in ID is called Threshold
voltage (VT or VGS (TH)).
– If VGS =< VT , ID is equal to zero.
– Gate current is still equal to zero because of the insulating material.
– If VGS is held constant at a negative value and VDS is increased negatively, ID
will eventually reach a saturation level (VDS sat), and ID will not increase
even if VDS is increased negatively.
• The saturation is due to pinching off of the channel (narrower channel)
near the Drain.
• If VDS is continuously increased after saturation has been reached, it will
eventually reach a breakdown value (VDS max) and ID will rise abruptly.
– Since there is no p-channel when VGS is equal to zero, and a p-channel is
created (enhanced) when VGS=VT, the device is called p-channel
enhancement type MOSFET. p-channel is created here
Drain if positive VGS is negatively
ID (D) high enough (VGS > VT)
p
Substrate
IG =0 + e (SS)
+
Gate (G) e
+ e
p
Source p
Holes VDD
(S) electrons
IS
VDSsat = VGS − VGS(Th) = Drain to Source voltage saturation level (volts)
VGS(Th) = VT = Gate to Source Threshold voltage (volts)
VDS.

– Above equation shows that there is also a non-linear relationship

between the Drain current and Gate to Source voltage.
P-Channel Enhancement Type MOSFET Characteristic
Curve
• The characteristic curve for n-channel enhancement type MOSFET is shown
below.
(VDS >=VDS max)
ID (mA)
ID (mA)
12 12
11 11
10 10 VGS =- 8 v
8 8
7 7 VGS = -7 v
6 6
5 5 VGS = -6 v
4 4
3 3 VGS = -5 v
2 2
1 1 VGS = -4 v
VGS = -3 v
VGS VDS (V)
0 (volt) -4 -8 -12
-1 -2 -3 -4 - 5 -6 - 7 - 8 VGS = VT= -2 volt
in this case
VGS = VGS(Th)=VT= 2 volt ID = 0 mA
in this case

Enhancement Type MOSFET Schematic Symbols
• The schematic symbols for enhancement type MOSFET are shown
below: + -
ID Drain (D) ID Drain (D)
Substrate Gate (G) Substrate V

Gate (G) (SS) VDS (SS) DS
VGS IS VGS IS Source (S)

Source (S)
- +
n-channel Enhancement Type p-channel Enhancement Type
MOSFET MOSFET
+ -
ID ID
Drain (D) Drain (D)
Gate (G) VDS

Gate (G) VDS
VGS IS VGS IS Source (S)

Source (S)
- +
n-channel Enhancement Type p-channel Enhancement Type
MOSFET MOSFET
MOSFET Handling
• MOSFETs are more sensitive to static electricity compared to BJT and JFET.
• Static electricity from surroundings are usually high enough to produce
destructive potential difference across the SiO2 insulator inside MOSFETs.
This could destroy the thin layer of SiO2 .
• The shorting foil / conductors connecting the leads when MOSFETs are
shipped should be kept in place until MOSFETs are installed.
– This will prevent potential difference from appearing across the terminals
of the device.
• Always touch the MOSFET at its casing to prevent introduction of static
electricity at its terminals.
• The power supply of circuits must be turned off before removing boards
containing MOSFETs to prevent surges from destroying the device.
• Two zener diodes placed back to back can be installed between the gate and
the source to prevent excessive voltages from being applied across the two
terminals.
Enhancement Type MOSFET Parameters
• The following are typical enhancement type MOSFET parameters usually

given in specification sheets.

– Maximum Drain to Gate voltage (VDG max.)
– Maximum Gate to Source voltage (VGS max.)
– Maximum Drain current (ID max)
PD=IDVDS)
On Characteristics: (When JFET has Drain current is greater than zero)

– Gate Threshold voltage (VT or VGS TH)
– Drain-Source on voltage (VDS ON)
– On state Drain current (ID on)
– Drain-Source Breakdown voltage (V(BR) DSX)
– Zero-Gate-Voltage Drain Current (IDSS)
– Gate Reverse Current (IGSS) – Gate current when p-n junctions are reverse
biased.

– Output Admittance (YOS)
– Input capacitance (Cjss)
– Drain-substrate capacitance (CD(SUB))
– Drain Source Resistance (rds (on))
Switching Characteristics:
– Turn on delay (tdl) – time for device to start switching on after input signal is
applied
– Rise Time (tr) - time for device to reach on level after starting to switch on
– Turn off delay (td2) – time for device to start switching off after input is applied
– Fall time (tf) – time for device to fall to off condition after starting to switch off
Vertical Metal Oxide Silicon FET (VMOS)
• The disadvantage of MOSFET of having lower power handling level could

be lessened by changing the structure of the MOSFET from a planar one to
a vertical one as shown below.
• The term vertical is due to the fact that the channel is now formed in the
vertical direction, and it also has a “V” shape in the semiconductor base.
• The application of a positive voltage at the Drain and a negative voltage at
the source with the gate at ground (0) potential results in the creation of two
n-channel in the two p-type regions.
Source terminals externally connected
- Source (S) Gate (G) Source (S) -

SiO2 (insulator) SiO2 (insulator)
n+ n+
p e e p
effective length
of channel
e e
n + substrate n + substrate
wider induced channel

Drain (D) +
Vertical Metal Oxide Silicon FET (VMOS)
• The reduced length of the channel also results to reduced resistance, which
translates to less power dissipated at the channel.
• The metal contacts are also increased which also reduces the resistance,
which also translates to less power dissipated at the device.
• The advantages of VMOS FETs are:
– It has reduced channel resistance levels than MOSFETs, resulting to
lower power dissipation in the device.
– It has higher current and power ratings than MOSFETs.
– It has positive temperature coefficient, which combats the possibility of
thermal runaway.
• If the temperature of the VMOS increases, its resistance level will
increase, causing a reduction in Drain current rather than an increase,
as in the case of JFETs.
– It has faster switching times compared to MOSFETs and BJTs, because
of the reduced charge storage levels due to shorter channel.
Complementary MOSFET (CMOS)
• Complementary MOSFET (CMOS) is a semiconductor device made up of
two MOSFETs, one p-channel and one n-channel, in a single substrate.
• It is commonly used in logic circuits.
• The advantages of CMOS are:
– Relatively high input impedance
– Fast switching speed
– Lower operating power level
Complementary MOSFET (CMOS) Construction
• Complementary MOSFET (CMOS) is a semiconductor device made up of
two MOSFETs, one p-channel and one n-channel, in a single substrate.
• A CMOS used as an inverter is shown below.
n-doped region
Ground Source 1 (S1)
when on n-channel
n
Metal contact
p Substrate (SS)
Gate 1 (G1) (Silicon
substrate)
Drain 1 (D1) n
p-doped region
Vo
when on p-channel
Drain 2 (D2) p
Vi
Gate 2 (G2) n
(Silicon Substrate (SS)
Source 2 (S2) p
VSS
Metal Semiconductor FET (MESFET)
• MESFET is more recently developed than MOSFET and junction FET.
• It uses GaAs as the base semiconductor material, which makes it faster in
terms of switching (higher speed).
• It is more expensive than MOSFET and JFET.
• The primary difference between a MESFET and a MOSFET is a MESFET
uses GaAs instead of Silicon as the substrate, and it uses Schottky barriers at
the Gate instead of silicon-dioxide insulating material.
– A Schottky barrier is a barrier made by depositing a metal (such as
tungsten) on an n-type channel.
• The absence of the insulating layer reduces the distance between the metal
contact surface of the Gate and the semiconductor layer, resulting to lower
capacitance between the two materials.
– The reduced capacitance results to better high frequency response and it
also allows higher mobility of carriers in the GaAs material.
– It also results to faster speed.
• Commercial MESFETs are manufactured using n-channel only because the
mobility of holes in GaAs is relatively low compared to negatively charged
carriers. Low mobility results to lower speed.
• MESFETs are also classified as depletion type MESFET and enhancement
type MESFET.
N-Channel Depletion Type MESFET
• The construction of an n-channel depletion type MESFET is shown below.
• The Gate is connected to a metallic conductor which is directly connected
to an n-channel between the Source and the Drain (no insulator).
• The presence of a metal-semiconductor junction is the reason for the name
metal-semiconductor FET.
• The use of GaAs results to higher speed.
• Using GaAs instead of silicon results to higher manufacturing costs and
lower density in ICs.
Heavily doped n-region
Drain (D) n GaAs

Metal tungsten
Gate (G) n p Substrate (GaAs)
Source (S) n
n-channel
Heavily doped n-region (lightly doped n-region)
N-Channel Depletion Type MESFET Schematic Symbol
• The schematic symbol for n-channel depletion type MESFET is shown below:
+
ID
Drain (D)
Gate (G)
- VDS
VGS Source (S)

IS
+
-
N-channel Depletion Type MESFET
• Current direction and polarity of voltages are for typical MESFET configuration.
• For typical biasing, Drain current is equal to the Source current.
N-Channel Depletion Type MESFET Typical Biasing
• Typical biasing for n-channel depletion type MESFET is shown below.
• Gate current is equal to zero.
• Source current is equal to the Drain current.
ID = Drain
current
Drain (D)
Gate (G)
VDS
IG (Gate
Source (S)
Current)
=0 VGS IS = Source
VGG Source current
(S) IS=ID
Typical Biasing For N-channel Depletion

Type MESFET
N-Channel Depletion Type MESFET Operation
• When the Gate has a negative potential relative to the Source and the Drain
has a positive potential relative to the Source, electrons will leave the n-
channel resulting to lower Drain current. The higher is the negative
potential at the Gate, the lower is the Drain current.
• When the Gate has a positive potential relative to the Source and the Drain
has a positive potential relative to the Source, electrons will be attracted to
the n-channel resulting to higher Drain current. The higher is the positive
potential at the Gate, the higher is the Drain current.
• The transfer characteristics of n-channel depletion type MESFET is similar
to those of n-channel depletion type MOSFET.
N-Channel Depletion Type MESFET Transfer Characteristics
• Just like JFETs and enhancement type MOSFETs, the relationship between
drain current (ID) and VGS is also defined by Shockley’s equation shown
below:
2
 VGS 
 VP 
VP = VP(off) = Pinch off voltage (volts) = VGS when ID = 0 ampere
• The transfer characteristics defined by Shockley’s equation are unaffected

by circuit components external to the enhancement type MESFET.
– The network equation may change but the transfer function is
unaffected.
• The squared term in the equation results to nonlinear relationship between
Drain current and VGS.
• When VGS = Vp (off), ID is equal to zero.
• When VGS = 0 volt, ID = IDSS.
N-Channel Depletion Type MESFET Characteristic Curve

ID (mA)
ID (mA)
12 VGS = 1 v
11 (IDSS) Enhancement
9 voltages (VGS>0volt)
7 7
6 6
5 5 VGS = -1 v Depletion
4 4 Region
3 3 (VGS<0volt)
2 2 VGS = -2 v
1 1 VGS = -3 v
VDS (V)
VGS 2 4 6 VGS = - 4 v =Vp
(volt) -4 -3 -2 -1 0 ID = 0 mA = (VGS off
Vp
In this case)
(pinch off
VGS = 0 v)
N- Channel Depletion Type MESFET Characteristic Curve

N-Channel Enhancement Type MESFET
• The construction of an n-channel enhancement type MESFET is shown
below.
• The Gate is connected to a metallic conductor which is directly connected
to the GaAs substrate between the Source and the Drain (no insulator).
• The response and characteristics of enhancement type MESFET are similar
to those of enhancement type MOSFET, but the “turn on” (threshold)
voltage is limited to 0v to 0.4 v (lower than that of enhancement type
MOSFET).
• Analysis is the same as that of enhancement type MOSFET.
+
ID
Heavily doped n-region
Drain (D)
Drain (D) n GaAs
Gate (G)
Metal tungsten - VDS
Gate (G) Substrate
VGS Source (S)
Source (S) n IS
+
Heavily doped n-region -
n-channel is created when gate is

N-channel Enhancement Type MESFET
sufficiently positive with respect to Schematic Symbol
Source
N-Channel Enhancement Type MESFET Operation
VDSsat = VGS − VGS(Th) = Drain to Source voltage saturation level (volts)
VDS.

– Above equation shows that there is a non-linear relationship between the

Drain current and Gate to Source voltage.
FET Biasing
FET Biasing
• For all FETs, there is a nonlinear relationship between ID and VGS, as shown
by Shockley’s equation.
– This results to more complicated mathematical approach to DC analysis
for FETs.
– Graphical approach is a quicker method for DC analysis for FETs, but
accuracy will be less.
• The input parameter is VGS, while the controlled output parameter is ID and
Is, which in turn control the voltages on the output side of the FET circuit.
• The general relationships which can be used in the analysis of all JFET,
MOSFET, and MESFET circuits are:
IG = 0 A
IS = ID
• For JFETs, depletion type MOSFETs and depletion type MESFETs,

Shockley’s equation is applicable.
FET Biasing
2
 VGS 
 VP 
For enhancement type MOSFETs and enhancement type MESFETs, the

following equations are applicable:
VDSsat = VGS − VT = Drain to Source voltage saturation level (volts)

VT = Gate to Source Threshold voltage (volts)
ID = k(VGS − VT) 2 = Drain current = Source current (Amp)

VT = Gate to Source Threshold voltage (volts)
FET Biasing
• The preceding equations are applicable only when the devices are in the
active region.
• Like BJTs, FETs can be biased using many ways.
• Some of the most common used biasing techniques for FETs are:
– Fixed biased
– Self biased
– Voltage divider biased
JFET Fixed Bias Configuration
• Fixed bias configuration for common source n-channel JFET is shown
below.
ID = Drain
RD current Cc2
Cc1 IG= 0
Drain (D)
Gate (G) VDD
IG (Gate VDS VO= Output voltage

RG Source (S)
Vi = Current)
VGS IS = Source
Input voltage =0
current
VGG IS=ID
Typical Fixed Bias Configuration For N-channel JFET
Assuming supply voltages and resistors allow JFET to operate in the active region, the following equation applies :
2
 VGS 
 VP 
• Fixed bias configuration for common source p-channel JFET is shown
below.
ID = Drain
RD current Cc2
Cc1 IG = 0
Drain (D)
Gate (G) VDD
IG (Gate VDS VO= Output voltage

RG Source (S)
Vi = Current)
VGS IS = Source
Input voltage =0
current
VGG IS=ID
Typical Fixed Bias Configuration For P-channel JFET
2
 VGS 
 VP 
• RG is placed to make sure that the AC input voltage (Vi) appears at the gate.
• RD is placed to make sure that the AC signal between the Drain and the Source
appear at the output (Vo).
• VDD is the supply voltage for the Drain while VGG is the biasing voltage for the
Gate. VGG keeps the p-n junction at the gate reverse biased, thus gate current is
always equal to zero.
• CC1 and CC2 are coupling capacitors. CC1 prevents DC voltages at the input from
appearing at the gate of the JFET, while CC2 prevents DC voltages at Drain from
appearing at the output of the circuit.
• For DC analysis, CC1 and CC2 can be considered “open” circuits.
• For AC analysis, CC1 and CC2 can be considered “short” circuits.
• For the DC analysis:
IG = IGQ = 0 A
IS = ISQ = ID = IDQ= Drain Quiescent Current = Source Quiescent Current
VRG = Voltage across RG= (IG)(RG) = 0 volt
VGS = VGSQ = VGG - VRG = VGG = voltage between the Gate and the Source
2
 VGS 
ID = IDQ = IDSS 1 −  = Drain current (Ampere)
 VP 
• For a certain value of VGG , VGSQ can be determined .
• Once VGSQ and Vp are known, IDQ can be computed or determined from a
graph.
• The output loop equation can be written as follows:
VDD = (ID)(RD) + VDS
• For a given value of VDD , and known values of ID and RD , VDS (also VDSQ)
can be computed.
• The following are conventions which are also encountered in DC analysis:
VD = VDS = voltage of Drain relative to ground

VG =VGS = voltage of Gate relative to ground
VS = voltage of Source relative to ground = 0 v (in this case)
• The values determined above are quiescent values (values at Q point), and are
applicable for DC analysis.
• The graphical approach is shown below:
– The graph below can be drawn using the following relationships:
When VGS = 0 ⇒ ID = IDSS
2
 0.3VP  IDSS
When VGS = 0.3VP ⇒ ID = IDSS 1 − =
 VP  2
2
 VP/2  IDSS
When VGS = 0.5 Vp ⇒ ID = IDSS 1 − =
 VP  4
When VGS = Vp ⇒ ID = 0
ID (mA)
ID= IDSS
Q point
ID= IDQ
VGS 0
(volt)
VGSQ = - VGG
ID= 0mA
• Example: Given Fixed Bias JFET circuit with the following parameters:
RG = 1.5 Mohm, RD = 2.5 kohm, VDD = 15 volts,
VGG= 2 volts, IDSS = 9 mA, Vp= -7 volts. Determine:
a. VGSQ
b. IDQ
c. VDSQ
d. VD
e. VG
f. VS
VGSQ = - VGG = - 2 volts

2 2
 VGSQ  −3  - 2 −3
IDQ = IDSS 1 −  = 9 x 10 1 −  = 4 .592 x 10 A
 VP   -7
VDSQ = VDD - (IDQ)(RD) = 15 – (4.592 x 10-3)(2500) = 3.52 volts

VD = VDSQ = 3.52 volts
VG = VGSQ = - 2 volts (IGQ = 0 A)
VS = 0 volt
The solution can also be done using graphical approach as follows:
When VGS = Vp = -7 V ID = 0 A
When VGS = Vp / 2 = - 3.5 V ID = IDSS / 4 = 9 x 10-3 / 4 = 2.25 x 10-3 A
When VGS = 0.3 Vp = - 2.1 V ID = IDSS / 2 = 9 x 10-3 / 2 = 4.5 x 10-3 A
When VGS = 0V ID = IDSS = 9 x 10-3 A
Based on graph, when ID (mA)

VGS = -2v , ID is around 12
4.6 A 11
10
ID= 9 mA = IDSS
The values of VGSQ , 9
8
VDSQ , VDQ ,VGQ,VSQ 7
can then be computed 6
using the equations on 5
4
the previous slide 3
2
1
VGS
(volt) -8 -7 -6 -5 -4 -3 -2 -1
JFET Self Bias Configuration
• Self bias configuration for common source n-channel JFET is shown
below.
RD ID = Drain
current Cc2
IG = 0
(Gate Current)
Drain (D) +
Gate (G) VDD
_
Cc1
S _ VDS VO= Output voltage
VGS +
Vi = +
IRG= 0 RG IS = Source
Input voltage RS current
_ IS=ID
Typical Self Bias Configuration For N-channel JFET
2
 VGS 
 VP 
• Self bias configuration for common source p-channel JFET is shown
below.
RD ID = Drain
current Cc2
IG = 0
(Gate Current)
Drain (D) _
Gate (G) VDD
Cc1 + VDS
S +
VGS _ VO= Output voltage
_
Vi = IRG= 0 IS = Source
Input voltage RG RS current
IS=ID
+
Typical Self Bias Configuration For P-channel JFET
2
 VGS 
 VP 
• Self bias configuration for common gate n-channel JFET is shown
below.
RD ID = Drain
current Cc2
IG = 0
(Gate Current)
Drain (D) +
Gate (G) VDD
_
VGS +
RS +
Vi =
IS = ID Input voltage Cc1
_
Typical Self Bias Configuration For Common Gate N-channel JFET
2
 VGS 
 VP 
• The gate to source voltage (VGS) is now determined by the voltage across Rs.
• There is no DC current flowing across RG (voltage across RG = 0) , and VGS is
equal to the voltage across Rs which is a function of the Source or Drain current.
VGS is now a function of Drain current and is no longer fixed.
• VDD is the supply voltage for the Drain.
appearing at output of the circuit.
• For the DC analysis (Applicable for common Source or common Gate):
RG can be replaced by a short circuit since there is no current across RG .
IG = IGQ = 0 A
IS = ISQ = ID = IDQ = Drain Quiescent Current = Source Quiescent Current
VG = 0 v
VRS = Voltage across RS = (IS)(RS)
VGS = VGSQ = - VRS = - (IS)(RS) = - (ID)(RS)
2 2
 VGS   (ID )(RS) 
ID = IDQ = IDSS 1 −  = IDSS 1 −
  = Drain current (Ampere)
 VP   VP 
• The resulting quadratic equation can be solved for ID.
• For a certain value of ID , VGSQ can be determined .
• The output loop equation can be written as follows:
VDD = (ID)(RD) + VDS + (IS)(RS)
• For a given value of VDD , and known values of ID, RD and RS, VDS (also VDSQ) can
be computed.
VD = VDS + VRS = voltage of Drain relative to ground

VG =VGS + VRS= 0 = voltage of Gate relative to ground
VS = VRS = (IS)(RS) = voltage of Source relative to ground
• The graphical approach is shown below (applicable for common Source or
common Gate:
1. The point when VGS = 0 is when ID = 0 (VGS = - IDRS )
IDSS - IDSS RS
2. When ID = ⇒ VGS =
2 2
3. A straight line can be drawn between the points (VGS = 0 , ID = 0)
 - IDSS RS IDSS 
and  VGS = ID = 
 2 2 
4. Based on the intersection of the straight line and the transfer characteristic curve
for the FET, IDQ and VGSQ can be determined.
5. The values of the other parameters can then be computed.
ID= IDSS ID (mA)
Q point ID= IDSS / 2

ID= IDQ
VGS = - IDSS RS / 2
VGS = 0 , ID = 0
VGS 0
(volt) VGSQ
• Example: Given Self Bias JFET circuit with the following parameters:
RG = 1.5 Mohm, RD = 2.5 kohm, RS = 1 kohm, VDD = 15 volts,
IDSS = 9 mA, Vp= -7 volts. Determine:
a. VGSQ
b. IDQ
c. VDSQ
d. VD
e. VG
f. VS
The problem can be solved using mathematical or graphical approach.

• Using mathematical approach, Shockley’s equation can be solved to

determine the value of IDQ. The values of the other parameters can then be
solved.
2 2
 VGS   - (ID )(RS) 
ID = IDQ = IDSS 1 −  = IDSS 1 −
 VP   VP 
( )
2
 - (ID )(1000) 
ID = 9 x 10 −3 1 − = −3
− D + 20,408ID = −3
− 2.565ID + 183ID
2
 9 x 10 1 285I 9 x 10
 -7 
0 = 9 x 10 −3 − 3.565ID + 183ID
2
3.565 ± 3.5652 − 4(183)(9 x 10 −3 )

ID = IDQ =
2(183)
= IDQ = 2.9806 x 10 −3 A
= IDQ = 16.49x 10 −3
Choose IDQ = 2.9806 x 10−3 A (This value is first reached when VGS
goes more negative)
VGSQ = -(ID )(RS) = -(2.9806 x 10 −3 )(1000) = −2.9806 volts
VDD = (ID)(RD) + VDS + (IS)(RS)
VDSQ=VDD - (ID)(RD) - (IS)(RS)=15-(2.9806 x 10-3)(2500) - (2.9806 x 10-3)(1000)
= 4.568 volts
VD = VDS + VRS = 4.568 + (2.9806 x 10-3)(1000) = 7.549 volts
VG =VGS + VRS= -2.9806 + 2.9806 = 0 volt (gate current is equal to zero)
VS = VRS = (IS)(RS) = = (2.9806 x 10-3)(1000) = 2.9806 volts

To determine the transfer characteristic curve of the JFET:
When VGS = 0 V ID = IDSS = 9 x 10-3 A
The transfer characteristic curve is drawn based on these points.
ID (mA)
For ID = (VGSQ)(RS): 12
When ID = 7 mA, VGS = - (7 x 10-3)(1000) = - 7 volts 11
10
When ID = 0 mA, VGS = 0 volts ID= 9 mA = IDSS 9
A straight line is drawn between these two points 8
7
6
Based on graph, 5
VGS = - 7 v , ID = 7 mA
Q 4
VGSQ = -3v ,
3
IDQ is around 3 A 2
1
The values of the other parameters are computed VGS
as in the mathematical approach. (volt) -8 -7 -6 -5 -4 -3 -2 -1
VGS = 0 , ID = 0
JFET Voltage Divider Bias Configuration
• Voltage divider bias configuration for common source n-channel JFET
is shown below.
+ RD ID = Drain
IRG1 current Cc2
RG1 IG = 0
(Gate Current)
_ Drain (D) +
Gate (G) VDD
_
Cc1 + S _ VDS VO= Output voltage
VGS +
Vi = +
RG2 IS = Source
Input voltage IRG2 RS current
_
_ IS=ID
Typical Voltage Divider Bias Configuration For Common Source N-channel JFET
2
 VGS 
 VP 
• Voltage divider configuration for common source p-channel JFET is
shown below.
_ RD ID = Drain
IRG1 current Cc2
RG1 IG = 0
(Gate Current)
Drain (D) _
+ Gate (G) VDD
Cc1 + VDS
_ S +
VGS _ VO= Output voltage
_
Vi = RG2 IS = Source
IS=ID
+ +
Typical Voltage Divider Bias Configuration For Common Source P-channel JFET
2
 VGS 
 VP 
• Similar to voltage divider bias for BJT, except IG = 0 .
• Since Gate current must be equal to zero, IRG1 and IRG2 must be equal.
IG = 0 IRG1 = IRG2 = VDD / (RG1 + RG2)
• The voltage across RG1 and RG2 can be computed as:
V RG2 = VDD - V RG1 = (VDD)(RG2) / (RG1 + RG2)
• Applying Kirchoff’s voltage law along Gate to Source loop, the following
equation can be derived:
VG = VRG2 = VGS + VRS = VGS + (ID)(RS) = voltage at gate relative to ground
VGS = VG - VRS = VG - (ID)(RS) = VRG2 - (ID)(RS) =Voltage across gate and source
• Shockley’s equation can be used to compute for ID.
2 2
 VGS   VRG2 - (ID )(RS) 
ID = IDQ = IDSS 1 −  = IDSS 1 −
 VP   VP 
• Source current is equal to Drain current (ID = IS)

• The output loop equation is:
VDD = (ID)(RD) + VDS + (IS)(RS) = (ID)(RD) + VDS + (ID)(RS)
be computed.

VG = VRG2 = voltage of Gate relative to ground (VRG2 in this case)
VS = VRS = (IS)(RS) = voltage of Source relative to ground (VRS in this case)
• Graphical approach can also be used.
VGS = VRG2 - (ID)(RS) = Voltage across gate and source
A straight line for the above equation can be drawn and the intersection of the
line and the transfer characteristic curve of the JFET can be determined, to
determine the quiescent values.
To plot the straight line, we set ID = 0, and then VGS = 0

VGS = VRG2 - (0)(RS) = VRG2 (when ID = 0 )
VGS = VRG2 - (ID)(RS) = 0 (when VGS = 0)
ID = VRG2 / RS (when VGS = 0)
• Values of the other parameters can then be computed.

• The graphical approach is shown below.
1. The point when VGS = 0 is when ID = VRG2 / RS
2. The point when ID = 0 is when VGS = VRG2
3. A straight line can be drawn using the two points above.
ID= IDSS ID (mA)
Q point VGS = 0 , ID = VRG2 / RS

ID= IDQ
VGS = VRG2 , ID = 0
VGS 0
(volt) VGSQ
• Example: Given voltage divider bias JFET circuit with the following
parameters:
RG1 = 2.5 Mohm, RG2 = 250 kohm , RD =1.5 kohm, RS = 2.4 kohm, VDD =
15 volts, IDSS = 9 mA, Vp= -7 volts. Determine:
a. VGSQ
b. IDQ
c. VDSQ
d. VD
e. VG
f. VS

solved. 2 2
 VGS   VRG2 - (ID )(RS) 
ID = IDQ = IDSS 1 −  = IDSS 1 −
 VP   VP 
2
  15 (250,000) 
  250,000 + 2.5 x 106 - (ID )(2,400) 
−3 
ID = 9 x 10 1 −    = 9 x 10 −3 (1.195 − 342.857ID )2
 -7 
 
 
(
= 9 x 10 −3 1.428 − 819.428ID + 117,551ID
2
)
0 = 12.852 x 10 −3 − 8.375ID + 1057.959ID
2
8.375 ± (−8.375) 2 − 4(12.852 x 10 −3 )(1057.959)

ID = IDQ =
2(1057.959)
= IDQ = 5.834 x 10 −3 A
= IDQ = 2.08x 10 −3 A
Choose IDQ = 2.08x 10 −3 A (This value is first reached when VGS
goes more negative)
VGSQ = VRG2 − ID RS
VDD RG2 (15) (250,000) −3
= − ID RS = − ( 2. 08 x10 ) (2,400)
RG2 + RG1 250,000 + 2.5x10 6
= - 3.628 volts
VDD = ID RD + VDS + IDRS

15 = (2.08x10 −3 ) (1,500) + VDSQ + (2.08x10 −3 ) (2,400)
VDSQ = 6.888 volts
VD = VDS + IDRS = 6.888 + (2.08x10 −3 ) (2,400) = VDD − IDRD

= 11.88 volts
VS = IDRS = (2.08x10 −3 ) (2,400)
= 4.992 volts
(15) (250,000)
VG = VRG2 =
250,000 + 2.5x106
= 1.36 volts
VGS = VRG2 - (0)(RS) = VRG2 (when ID = 0 ) ID (mA)
= (VDD)(RG2) / (RG2 + RG1) 12
= 15 (250,000) / (250,000 + 2.5 x 106) 11
=1.364 volts (when ID = 0 ) 10
ID = VRG2 / RS (when VGS = 0) ID= 9 mA = IDSS 9
8
ID = 15 (250,000) / [(250,000 + 2.5 x 106)(2400)]
7
=0.568 X 10 – 3 A (when VGS = 0) 6
VGS = - 7 v , ID = 7 mA 5
A straight line is drawn between these two points. 4
ID = 0
Q 3
Based on graph,
2
VGSQ is around - 3.6 volts
1
IDQ is around 2.2 mA
VGS
(volt) -8 -7 -6 -5 -4 -3 -2 -1 1 2
The values of the other parameters are computed VGS = 0
as in the mathematical approach.
JFET with Drain and Source Supply Configuration
+ VDD = 18 volts
RD = 2K ID = Drain
current Cc2
IG = 0
(Gate Current)
Drain (D) +
Gate (G)
_
VGS +
+
IS = ID RS = 1500
-
-VSS = - 5 volts
2
 VGS 
 V P 
• Example: Given the JFET circuit in the preceding slide with the following
parameters:
RD =2 kohm, RS = 1.5 kohm, VDD = 18 volts, VSS = -5 volts IDSS = 9 mA,
Vp= -7 volts. Determine:
a. VGSQ
b. IDQ
c. VDSQ
d. VD
e. VG
f. VS

solved.
 - (ID )(RS) − Vss 
2 2
 VGS 
ID = IDQ = IDSS 1 −  = IDSS 1 −  = Drain current (Ampere)
 VP   V P 
 - (ID )(1,500) − (-5) 
2
ID = 9 x 10 −3 1 −  = 9 x 10 −3
[1.714 - 214.286ID]
2
 -7
[
= 9 x 10 −3 2.938 - 734.572 ID + 45,918.49 ID 2 ]
0 = 26.44x 10 −3 − 7.611 ID + 413.266 ID
2
7.611 ± (−7.611) 2 − 4(26.44 x 10 −3 )(413.266)

ID = IDQ =
2(413.266)
= IDQ = 13.77 x 10 −3 A
= IDQ = 4.646x 10 −3 A
Choose IDQ = 4.646x 10 −3 A (This value is first reached when VGS
goes more negative)
VGSQ = −ID RS - VSS
= −(4.646x10 −3 ) (1,500) - (-5)
= - 1.969 volts
VDD = ID RD + VDS + IDRS + VSS

18 = (4.646 x10 −3 ) (2000) + VDS + (4.646 x10 −3 ) (1500) + (-5)
VDS = VDSQ = 6.739 volts
VD = VDS + IDRS + VSS = VDD − IDRD

= 6.739 + (4.646 x10 −3 ) (1,500) + (-5)
= 8.708 volts = voltage of Drain with respect to ground
VS = IDRS + VSS = (4.646 x10 −3 ) (1,500) + (-5)
= 1.969 volts = voltage of Source with respect to ground
VG = 0 volt = voltage of gate with respect to ground (gate is connected to ground)
VGS = -IDRS-VSS = -Vss (when ID = 0 ) ID (mA)
= -(-5) = 5 volts (when ID = 0 ) 12
ID = -VSS / RS (when VGS = 0) 11
ID = -(-5) / 1500 10
ID= 9 mA = IDSS 9
=3.333 X 10 – 3 A (when VGS = 0)
8
7
A straight line is drawn between these two points 6
Based on graph, VGS = - 7 v , ID = 7 mA Q
5
VGSQ is around - 2 volts 4
ID = 0
IDQ is around 4.6 mA 3
2
1
The values of the other parameters are computed
VGS
as in the mathematical approach. (volt) -8 -7 -6 -5 -4 -3 -2 -1 1 2 3 4 5
VGS = 0
Depletion Type MOSFET Biasing
• The similarities in the transfer curves of depletion type MOSFETs and
JFETs allow a similar DC analysis for the two devices.
• The difference in the operation of the two devices is that depletion type
MOSFETs can have positive or negative values of Gate to Source voltage
(VGS) while JFETs typically can only have negative values for VGS.
• The different biasing techniques and dc analysis applied to JFETs can also
be used for depletion type MOSFETs.
• Fixed bias, self bias, and voltage divider bias can also be used for depletion
type MOSFETs.
• For positive values of VGS for MOSFETs, Shockley’s equation can also be
applied.
Depletion Type MOSFET Voltage Divider Bias Configuration
• Voltage divider bias configuration for common source n-channel
depletion type MOSFET is shown below.
+ RD ID = Drain
IRG1 current Cc2
RG1 IG = 0
(Gate Current)
_ Drain (D) +
VDD
Gate (G)
+ _
Cc1 S _ VDS VO= Output voltage
VGS +
Vi = +
RG2 IS = Source
_
_ IS=ID
Typical Voltage Divider Bias Configuration For Common Source n-channel Depletion Type MOSFET
Assuming supply voltages and resistors allow MOSFET to operate in the active region, the following equation applies :
2
 VGS 
ID = IDSS 1 − = Drain current (Ampere)
 VP 
• Similar to voltage divider bias for BJT, except IG = 0 .
appearing at the gate of the MOSFET, while CC2 prevents DC voltages at Drain
from appearing at output of the circuit.
• Shockley’s equation can be used to compute for ID.
2 2
 VGS   VRG2 - (ID )(RS) 
ID = IDQ = IDSS 1 −  = IDSS 1 −
 VP   VP 

be computed.


line and the transfer characteristic curve of the JFET can be determined, to

VGS = VRG2 - (0)(RD) = VRG2 (when ID = 0 )
VGS = VRG2 - (ID)(RD) = 0 (when VGS = 0)

• The graphical approach is shown below.
1. The point when VGS = 0 is when ID = VRG2 / RS
2. The point when ID = 0 is when VGS = VRG2
3. A straight line can be drawn using the two points above.
ID= IDSS ID (mA)
Q point VGS = 0 , ID = VRG2 / RS

ID= IDQ
VGS = VRG2 , ID = 0
VGS 0
(volt) VGSQ
• Example: Given voltage divider bias for n-channel depletion type MOSFET
circuit with the following parameters:
RG1 = 100 Mohm, RG2 = 8 Mohm , RD =2 kohm, RS = 800 ohm, VDD = 18
volts, IDSS = 9 mA, Vp= -7 volts. Determine:
a. VGSQ
b. IDQ
c. VDSQ
d. VD
e. VG
f. VS
g. IDQ and VGSQ when RS is changed to 100 ohms

solved. 2 2
 VGS   VRG2 - (ID )(RS) 
ID = IDQ = IDSS 1 −  = IDSS 1 −
 VP   VP 
2
  18 (8 x 10 ) 6

  - (ID )(800) 
8 x 10 6
+ 100 x 10 6
ID = 9 x 10 −3 1 −    = 9 x 10 −3 (1.19 − 114.286ID )2
 -7 
 
 
(
= 9 x 10 −3 1.416 − 272ID + 13,061.29ID
2
)
0 = 12.744 x 10 −3 − 3.448ID + 117.551ID
2
3.448 ± (−3.448) 2 − 4(12.744 x 10 −3 )(117.551)

ID = IDQ =
2(117.551)
= IDQ = 25 x 10 −3 A
= IDQ = 4.337 x 10 −3 A
Choose IDQ = 4.337 x 10 −3 A
VDD RG2 (18) (8x106 ) −3
= − ID RS = − ( 4.337 x10 ) (800)
RG2 + RG1 8x10 + 100 x10
6 6
= - 2.136 volts
VDD = ID RD + VDS + IDRS

18 = (4.337 x10 −3 ) (2,000) + VDSQ + (4.337 x10 −3 ) (800)
VDSQ = 5.856 volts
VD = VDS + IDRS = 5.856 + (4.337 x10 −3 ) (800) = VDD − IDRD

= 9.326volts
VS = IDRS = (4.337 x10 −3 ) (800)
= 3.47 volts
(18) (8x106 )
VG = VRG2 =
8x106 + 100x106
= 1.333 volts
VGS = VRG2 - (0)(RS) = VRG2 (when ID = 0 ) ID (mA)
= (VDD)(RG2) / (RG2 + RG1) 12
= 18 (8x106) / (8 x106 + 100 x 106) 11
=1.333 volts (when ID = 0 ) 10
8
ID = 1.333 / 800
7
=1.666 X 10 – 3 A (when VGS = 0) 6
VGS = - 7 v , ID = 7 mA 5
ID = 0
Q 3
Based on graph,
2
VGSQ is around - 2 volts
1
IDQ is around 4.3 mA
VGS
(volt) -8 -7 -6 -5 -4 -3 -2 -1 1 2
The values of the other parameters are computed VGS = 0
Using mathematical approach, Shockley’s equation can be
solved to determine the value of IDQ when Rs is changed to 100
ohms. The values 2of the other parameters
2
can then be solved.
 VGS   VRG2 - (ID )(RS) 
ID = IDQ = IDSS 1 −  = IDSS 1 −
 VP   V P 
2
  18 (8 x 106 ) 
  - (ID )(100) 
6
+ 6
ID = 9 x 10 −3 1 − 
8 x 10 100 x 10   = 9 x 10 −3 (1.19 − 14.286ID )2
 -7 
 
 
(
= 9 x 10 −3 1.416 − 34ID + 204.09ID
2
)
0 = 12.744 x 10 −3 − 1.306ID + 1.837 ID
2
1.306 ± (−1.306) 2 − 4(12.744 x 10 −3 )(1.837)

ID = IDQ =
2(1.837)
= IDQ = 701 x 10 −3 A
= IDQ = 9.893x 10 −3 A
Choose IDQ = 9.893x 10 −3 A
VDD RG2 (18) (8x106 ) −3
= − ID RS = − (9 .893x10 ) (100)
RG2 + RG1 8x106 + 100x106
= 0.344 volts (VGS is now positive. Positive VGS is possible for depletion type
MOSFETs)
Graphical approach can also be used as shown in the next slide.

The transfer characteristic curve is drawn based on these points. VGS = 0
VGS = VRG2 - (0)(RS) = VRG2 (when ID = 0 ) ID (mA) 13

= (VDD)(RG2) / (RG2 + RG1) 12
= 18 (8x106) / (8 x106 + 100 x 106) 11
=1.333 volts (when ID = 0 ) 10
Q
8
ID = 1.333 / 100
7
=13.33 X 10 – 3 A (when VGS = 0) 6
VGS = - 7 v , ID = 7 mA 5
ID = 0
Q 3
Based on graph,
2
VGSQ is around + 0.3 volts
1
IDQ is around 10 mA
VGS
(volt) -8 -7 -6 -5 -4 -3 -2 -1 1 2
The values of the other parameters are computed
Enhancement Type MOSFET Biasing
• The computations and graphical approach for enhancement type MOSFETs
are quite different from those of JFETs and depletion type MOSFETs,
because of the differences in their transfer characteristics.
• For enhancement type MOSFETs, the drain current is zero (0) for levels of
gate to source voltage less than the threshold level VGSth.
• The drain current for enhancement type MOSFETs for voltages above VGSth
can be computed as:

k = constant and a function of a particular device (Amp/volt2 )
• Specifications sheet typically indicate the threshold voltage VGSth and a level
of drain current (IDon) for a particular value of VGS (VGSon). Based on these
values, the constant k can be computed.
Enhancement Type MOSFET Feedback Bias Configuration
RD ID = Drain
current Cc2
RG IG = 0
(Gate Current)
Drain (D) +
VDD
Gate (G)
_
VGS +
Vi = IS = Source
Input voltage current
IS=ID
Typical Feedback Bias Configuration For Common Source n-channel Enhancement Type MOSFET
• Feedback bias configuration is common for enhancement type MOSFETs.

RD ID = Drain
current Cc2
RG IG = 0
(Gate Current)
Drain (D) +
VDD
Gate (G)
_
VGS +
Vi = IS = Source
Input voltage current
IS=ID
Typical Feedback Bias Configuration For Common Source P-channel Enhancement Type MOSFET
• Feedback bias configuration is common for enhancement type MOSFETs.

• The gate resistor RG provides a suitably large voltage to the gate to drive the
MOSFET “on”. Since gate current is equal to zero, the voltage drop across
RG is zero, and the gate to drain voltage is effectively zero.
• The following conditions exist:
VD = VG
VDS = VGS
VDS = VDD – IDRD
VGS = VDD – IDRD
• A straight line can be plotted by setting ID = 0, and then VGS = 0.
VGS = VDD when ID = 0

ID = VDD / RD when VGS = 0
• The intersection of the line determined above and the transfer characteristic
curve of the device gives the Q point of the circuit.

(VDS >=VDS max)
ID (mA)
ID (mA)
VGS = VDD – IDRD
12 12
11 11
10 10 VGS = 8 v
8 8
7 7 VGS = 7 v
6 Q 6
5 5 VGS = 6 v
4 4
3 3 VGS = 5 v
2 2
1 1 VGS = 4 v
VGS = 3 v
VGS VDS (V)
0 (volt) 4 8 12
1 2 3 4 5 6 7 8 VGS = VT= 2 volt
in this case
VGS = VGS(th)=VT= 2 volt ID = 0 mA
in this case

• Example: Given feedback bias for n-channel enhancement type MOSFET
circuit with the following parameters:
RG = 8 Mohm, RD =2 kohm, VDD = 8 volts, IDON = 2.75 mA, VGSON = 5
volts, VGS(th)= 2 volts. Determine:
a. VGSQ
b. IDQ
c. VDSQ

• The procedures below describe the mathematical approach.

ID 2.75 x 10-3
k= = = 3.056 x 10-4 A / V 2
(VGS − VGS(Th)) 2
(5 − 2) 2
VDS = VDD – IDRD

VGS = VDD – IDRD = 8 − 2000 ID
ID = 3.056 x 10-4 (8 − 2000 ID − 2) 2
0 = 3.056 x 10-4 (36 − 24000ID + 4,000,000ID 2 )
0 = 0.011 − 8.334ID + 1,222.4ID 2
8.334 ± (−8.334) 2 − 4(0.011)(1,222.4)
ID = IDQ =
2(1,222.4)
= IDQ = 5.028 x 10 −3 A
= IDQ = 1.785 x 10 −3 A
Choose IDQ = IDQ = 1.785 x 10 −3 A
VGSQ = VDSQ = VDD – IDRD = 8 − (2000)( 1.785 x 10 −3 ) = 4.43 volts

• The procedures below describe the graphical approach.

ID 2.75 x 10-3
k= = = 3.056 x 10 -4
A / V 2
(VGS − VGS(Th)) 2 (5 − 2) 2
To determine the other points in the transfer characteristic curve,

we set VGS = 6 volts and 8 volts.
ID = k(VGS − VGS(Th)) 2 = 3.056 x 10-4 (6 − 2) 2 = 4.89 x 10-3 A when VGS = 6 v
ID = k(VGS − VGS(Th)) 2 = 3.056 x 10-4 (8 − 2) 2 = 11 x 10-3 A when VGS = 8 v
VGS = VDD – IDRD
A straight line can be plotted by setting ID = 0, and

then VGS = 0.
VGS = VDD = 8 volts when ID = 0

ID = VDD / RD = 8 / 2000 = 4 mA when VGS = 0
ID (mA) VGS = VDD – IDRD
12
Based on graph, 10
9
VGSQ is around 4.5 volts
8
IDQ is around 1.75 mA 7
6 Q
The values of the other parameters are computed 5
as in the mathematical approach. 4
3
2
1
VGS
0 (volt)
1 2 3 4 5 6 7 8
VGS = VT= 2 volt

in this case
Enhancement Type MOSFET Voltage Divider Bias Configuration
+ I RD ID = Drain
RG1
IG = 0 current Cc2
RG1 (Gate Current) Drain (D)
_ +
Gate (G) VDD
_
Cc1 + S _ VDS VO= Output voltage
VGS +
Vi = +
RG2 IS = Source
_
_ IS=ID
Typical Voltage Divider Bias Configuration For Common Source N-channel enhancement type MOSFET
Enhancement Type MOSFET Voltage Divider Bias
Configuration
_ IRG1 RD ID = Drain
IG = 0 current Cc2
RG1 (Gate Current) Drain (D)
+ _
Gate (G) VDD
Cc1 _ S + VDS VO= Output voltage
VGS
_
Vi = RG2 IS = Source
+ + IS=ID
Typical Voltage Divider Bias Configuration For Common Source P-channel enhancement type MOSFET
• The following equation can be used to compute for ID.

be computed.


line and the transfer characteristic curve of the MOSFET can be determined, to

VGS = VRG2 - (0)(RD) = VRG2 (when ID = 0 )
VGS = VRG2 - (ID)(RD) = 0 (when VGS = 0)

Field Effect Transistors

Загружено:

Сведения о документе

Исходное описание:

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Field Effect Transistors

Загружено:

Авторское право:

Доступные форматы

Electronics 2

Instructor: Armando V. Barretto

Final Grade = (Q1+Q2+Q3+Q4+2FE+2PE)/8

Depletion Depletion Depletion Depletion

IS = source current IS = source current

Drain (D) Drain (D) ID = Drain

Ohmic Saturation region Breakdown

N-channel resistance (constant)

Drain (D) Drain (D) ID = Drain

Gate (G) 9v Gate (G)

Locus of pinch off Breakdown

N-Channel JFET Characteristic Curve For Different Values of VGS

Locus of pinch off Breakdown

P-Channel JFET Characteristic Curve For Different Values of VGS

where : ro = Drain resistance when VGS = 0 volt

Gate (G) Gate (G) VDS

VGS Source (S) VGS Source (S)

Drain (D) Drain (D)

• The transfer characteristics defined by Shockley’s equation are unaffected by

• The above results could be used to approximate the transfer characteristic

ID= 8mA=IDSS 8 8 VGS = 0 v

PD = (VDS)(ID) = power dissipated (watts)

JFET Linear Operating Region

Maximum Ratings: (Should not be exceeded or JFET could be destroyed)

On Characteristics: (When JFET has Drain current is greater than zero)

Small Signal Characteristics:

N-Channel Depletion Type MOSFET Construction

P-Channel Depletion Type MOSFET Construction

Source (S) Source (S)

Gate (G) VDS

VGS Source (S) Source (S)

Maximum Ratings: (Should not be exceeded or JFET could be destroyed)

On Characteristics: (When JFET has Drain current)

Small Signal Characteristics:

N-channel Enhancement Type MOSFET

ID = k(VGS − VGS(Th)) 2 = Drain current = Source current (Amp)

– Above equation shows that there is a non-linear relationship between the

N- Channel Depletion Type MOSFET Characteristic Curve

SiO2 (insulator) p-doped region

P-channel Enhancement Type MOSFET

ID = k(VGS − VGS(Th)) 2 = Drain current = Source current (Amp)

– Above equation shows that there is also a non-linear relationship

N- Channel Depletion Type MOSFET Characteristic Curve

Substrate Gate (G) Substrate V

VGS IS VGS IS Source (S)

Gate (G) VDS

VGS IS VGS IS Source (S)

• The following are typical enhancement type MOSFET parameters usually

Maximum Ratings: (Should not be exceeded or JFET could be destroyed)

On Characteristics: (When JFET has Drain current is greater than zero)

Small Signal Characteristics:

• The disadvantage of MOSFET of having lower power handling level could

- Source (S) Gate (G) Source (S) -

wider induced channel

Heavily doped n-region

Drain (D) n GaAs

VGS Source (S)

N-channel Depletion Type MESFET

Typical Biasing For N-channel Depletion

• The transfer characteristics defined by Shockley’s equation are unaffected

Depletion Mode Enhancement Saturation region Breakdown Region

N- Channel Depletion Type MESFET Characteristic Curve

n-channel is created when gate is