CPEN111 Microelectronics

Laboratory Results

Submitted by:
Glenn L. Sampayan
BSCpE 5-1 | 201314473

Submitted to:
Ms. Sheryl D. Fenol
 INTRODUCTION

The Electric VLSI Design System is an EDA tool written in the early 1980s by

Steven M. Rubin. Electric is used to draw schematics and to do integrated circuit

layout. It can also handle hardware description languages such as VHDL and

Verilog. The system has many analysis and synthesis tools, including Design rule

checking, Simulation, Routing, Layout vs. Schematic, Logical Effort, and more.

Electric is currently part of the GNU project and has been developed in Java and

distributed as free and open-source software, subject to the requirements of the

GNU General Public License (GPL), version 3 or any later.

WinSpice is a port of Spice3F4 to Win32 systems. It is ported to run in a

window as a native 32-bit application. It can generate waveform plots to

individual floating windows and contains a powerful scripting language. It

contains several enhancements over the original Berkeley Spice3F4: better

compatibility with Spice2 and PSpice circuit files; such as handling for POLY

statements in nonlinear sources; support for PSpice-style libraries; manual and a

simple tutorial; both in Word for Windows 2 format; hundreds of bug fixes; three

versions of the BSIM3 model, JFET2, BSIM4 device models; zoomable plot windows;

the EKV MOSFET model from Ecole Polytechnique Federale de Lausanne (EPFL);

and parameterized sub circuits.

 RESULTS, SCHEMATIC, AND LAYOUT

Exercise No. 1 CMOS Inverter Static Characteristics

Figure 1. The CMOS Inverter Schematic.

Exercise No. 2 CMOS Inverter Dynamic Characteristics

Figure 2. The CMOS Inverter Icon.

Figure 3. The CMOS Inverter Icon Schematic.

Exercise No. 3 NOR and NAND Gates

Figure 4. The NOR Icon.

Figure 5. The NOR Icon Schematic.

Figure 6. The NAND Icon.

Figure 7. The NAND Icon Schematic.
Exercise No. 4 CMOS Inverter Layout and Layout Instance

Figure 8. The CMOS Inverter Layout.

Exercise No. 5 NOR and NAND Gates Layout

Figure 9. The NOR Layout.

Figure 10. The NOR Layout Schematic.

 Figure 11. The NAND Layout.

Figure 12. The NAND Layout Schematic.

Exercise No. 6 Half-Adder Schematic Layout

Figure 13. The Half-Adder Icon.

 Figure 13. The Half-Adder Icon Schematic.

Conclusion

In our experiment, the implementation of universal gates in logic circuits has

been made. We have used variables (A, B, C and X, Y) or in other words, inputs

that we must carry out possible combinations by connecting as instructed to

represent each of combinations output. We began to construct a circuit diagram

composed mainly of the NAND, NOR and an INVERTER logic gate for each

experiment. We also constructed a series of possible answer for each

combination to serve as a guide to the values were going to measure. We then

compared our computed or expected value to what we measured in actual

operation and the results did match to one another. Then, to perform the main
point of the experiment which was the universal gates, we are required to

reconstruct the circuits in the first procedure using universal gates only, but must

maintain the same behavior that the previous circuits had obtained. In other

words, we have to prove why the NAND and NOR gates are so called universal

gates. We converted the previous diagrams we made into circuits that were

composed mainly of NAND and NOR gates and followed the same procedure.

After the experiment, we can now say that using Universal gates we can

implement any gate like AND, OR and NOT, or any combination of these basic

gates and obtained the same output. Also, we have proved its most important

advantage compared to circuits using basic gates, and that is it minimizes the

logic ICs being used. Therefore, NAND and NOR gates really deserved their title

as the Universal gates.