Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

Performance Analysis of Power Gating designs in

Low Power VLSI Circuits
C. Chrisjin Gnana Suji, S. Maragatharaj, RHemima
PG Scholar, VLS] Design, PG Scholar, VLS] Design, PG Scholar, VLS] Design,

Anna University o/Technology, Anna University o/Technology, Anna University o/Technology,

Coimbatore,India Coimbatore,India Coimbatore,India

chrisjin suji@yahoo.co.in
_ smr.yuva@gmail.com r.hemima@gmail.com

Abstract --- The growing market of mobile, battery standby mode. The header switch is implemented by PMOS
powered electronic systems (e.g., cellular phones, to control Vdd supply. PMOS transistor is less leaky than
personal digital assistants, etc.) demands the design of NMOS transistor of the same size. The disadvantage of the
microelectronic circuits with low power dissipation. As header switch is that PMOS has lower drive current than
density and complexity of the chips continue to increase, NMOS of a same size. As a result, a header switch
the difficulty in providing power dissipation might limit implementation usually consumes more area than a footer
the functionality of the computing systems. Especially, at switch implementation. The footer switch is implemented by
nanometer level the power dissipation consumes about NMOS transistor to control VSS supply. The advantage of
35% of the chip power. The purpose of this project is to footer switch is the high drive and hence smaller area.
analyse the performance of one of the most trustful However, NMOS is leakier than PMOS and sleep transistor
approaches to low power design called as "Power become more sensitive to ground noise. An example for the
Gating". The focus is only on CMOS devices in sleep transistor and Distributed sleep transistor network are
nanometer scale, as this technology is being the most given in the figures 1 and 2 respectively.
widely adopted in current VLSI systems. In this project,
we compare the performance of various power gating
designs using 65nm technology. In a power gating . .J........... V/JJ)

'i;
.... _ ... .

i Low VII,
; I
structure, a transistor with high threshold voltage (Vth) is i
placed in series with a low Vth device. The high Vth ! logiC !
transistor is called as the Sleep Transistor. In the power : de\'ice !
gating structure, a circuit operates in two different ;mol S"""d (vGN: H;,h V,," 'p (ran istor
modes. In the active mode, the sleep transistors are
turned ON and can be treated as the functional
redundant resistances. In the sleep mode, the sleep
transistors are turned OFF to reduce the leakage power.
When a sleep transistor is placed at VDD, it is called as Figure 1: A Power Gating Structure.
the "Header switch" and while it is placed near the
ground, it is called as "Footer switch". In this project, I
;._. . _J_... .. .... :
- r 1 1 r ... ..l. D
V,h
. . .. --._._ .'.'.'-'.'

:
have taken the footer switch exclusively for all my
_._._._ _._._ ...

Law LJ Low VIl, Low V'/I' ;

logic
I

r IQgfr;
designs. I

! l log,c r
i i del/ices !
---!

de'P;ces dew'ces

Ske- - -' ;- -. 'e-0::;

Keywords- BCD Adder, Sleep transistors, distributed
sleep transistor network (DSTN), Clock gated power
gating, Sleep transistor Scheduling.

I. INTRODUCTION
Figure 2: A DSTN Structure.
Optimum sleep transistor design and
implementation are critical to a successful power-gating
design. There are special considerations for the sleep While implementing sleep transistors in CMOS
transistor design. Few of them are sleep transistor gate circuits, the perfonnance is found to be better when they are
length, width and body bias optimization for area, leakage interconnected to form a network. There is much such
and efficiency. In the power gating, sleep transistors are architecture out of which most notable structure is the
used as switches to shut off power to parts of a design in distributed sleep transistor network (DSTN).In a distributed
sleep transistor network gates in a cluster are connected to

978-1-61284-653-8/11/$26.00 2011 IEEE 689

Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

the sleep transistor by virtual-ground wires. The spot at

which sleep transistor is connected to logic gates is called
tapping point. By adding more wires to form a mesh
containing all virtual-ground wires, we obtain the DSTN
structure
Among the leakage reduction techniques, the power
gating technique has become one of the most effective
methods. With the circuit density being increased at nano
scale, the scheduling of the sleep transistors plays a vital role
in reducing the leakage power of the circuit. Here a new
scheduling method for the sleep transistors has been
designed and I have attempted to compare the performance
of various power gating designs at 65nm scale by
implementing the design on conventional 4-bit BCD adder.

II. CONVENTIONAL CMOS 4-BIT BCD ADDER Figure4: Schematic of 4 bit BCD adder.

The term BCD stands for binary coded decimal. It
is another method used to represent decimal numbers in
digital circuits. Since all the digital circuits need to display
the results in digital form, this circuit is inevitable in any
digital circuit. In BCD, many types of codes are used for
conversion; but the 8 - 4 - 2 - lis the most common code.
8 - 4 - 2 - 1 code indicates the weight of each bit
3 2 1 to logic gates is called tapping point. By adding more wires
in the following order: 2 - 2 - 2 - 2 .
For example, consider the decimal number: 9342.
This value can be converted to binary form using 8-4-2-1
BCD as follows:
9342 = 1001 0011 0100 0010
9 3 4 2
To implement a 4-bit BCD adder we need two 4-bit
full adders, one to add two 4-bit BCD numbers and the other
full adder to add 2's complement of the results greater than 9
to the result if carry is generated. Also we need 2 AND gates
and one OR gate to generate carry signal.
III. POWER GATED 4-BIT BCD ADDER DESIGN
A. 4-BIT BCD Adder Power Gated With DSTN
In a distributed sleep transistor network, gates in a
cluster are connected to the sleep transistor by virtual
ground wires. The spot at which sleep transistor is connected
to form a mesh containing all virtual-ground wires, we
obtain the DSTN structure.
While designing the DSTN for the BCD adder, two
sleep transistors are placed for each fulladder circuit. One
for the sum circuit and another for the carry circuit. The
sleep transistor in each full adder form a single cluster. The
sleep transistors present in each cluster are connected
through a single line which is called as the "Virtual
Ground". The virtual ground line is excited by means of an
external sleep signal. The schematic for the BCD adder
designed with DSTN power gating structure is given in the
figure .

...
; --l 4 BI T ADDER
....-
__ --.:=.
c COUT +-
L-_S-",_S-". __
S !.
1 _...- S..-'c....J CN1

o o

4 BIT ADDER
+-0

Figure 3: A 4 bit BCD adder.

Figure 5: 4-bit bcd adder power gated with dstn.
The schematic of a CMOS 4-bit BCD adder designed using
DSCH 3.1 is given in figure 4.

978-1-61284-653-8/11/$26.00 2011 IEEE 690

Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

.tlJlC 1!'fAl tJ111'!

tIDl!!I II :II 11.: 151.1 E ! )1.1 l4l: !OIl

B. 4-BIT BCD Adder With Clock Gated Power Gating

l kItI ll l J illlll llIllllllIl l lll I iii 1111 11111111111 1111 11111 11111111 111 1111

In clock gated power gating structure, an internal

' =:JJ
-Ir----'1 -,
- ====r'
_u_ -,

clock signal is used to excite the sleep transistors in the - ""'

1= rh -
==,--,J . .. _ . .
. . .. "P===
BCD circuit. The clock frequency is partially dependent rl-J _
.

_ .. U U - - -

on the average delay which occurs within the circuit. . ..- I T

F
I -I
,.
The clock speed is predetermined based on the
.
'1ul;==========-
propagation speed of intermediate results between logic .
. . _..
.u Ti
.-'-
. .
._ . _ ...._ . _...

clusters in the circuit. The schematic of the BCD adder .. .

with clock gated power gating is given in figure 6.

,R
'I I I I r.
o
. - -=
o_ . .. -

'I LJ .
,n

The above mentioned circuits are designed in 65nm - 1 . o uo o o

'I [ T[]l
scale. The sleep transistors used are designed to have a . :U!-l==
'I :. I uIFo""'Lr T I
,.
. ==

higher WIL ratio than the ones used in the BCD adder. ,.
' LlIT] 1 0 1 I -rn u - -

,..\'. -, '1----' T J .. r : r ...... -0

Figure 7: Output of conventional CMOS 4-bit BCD adder

1-hmoo \lew.'" 0ptI0.

I
uu un t.D K 4f.O ).C te., 010 lllC . ICO) liOJ MQ ia:_O

I .. 1111 11111111 I lliI 11IIIIIIIIIIIIIIIIIII 1IIIIIilIIIIIIIIIIIIIIIIIIIIII 1IIIIIlillllllllllllllllllllllllillilllllili

'I
'.bl ==' .
_ ... ._ . . . :
. . ..:

I' !-

'I I
'f ........... . .. .... . ......... .... ............

Figure 6: 4-bit bcd adder with clock gated power gating

'I . I. ........ '
.,",
I' L __+

IV SIMULATION RESULTS

In this section I have describes the simulation results

that were generated using DSCH3.l. First, we take the
output for the schematic designed using DSCH 3.l. Then we
Fig ure 8: Output of power gated 4-bit BCD adder.
convert the schematic into layout using the net list and
develop the layout design. From running the layout, we
A. VI Characteristics
obtain various characteristics of the circuit including the V-I
characteristics. The diagram 7 shows the output of
The V-I characteristics of the circuits designed above
conventional BCD adder and 8 shows the output of the
are generated using Microwind layout tool. It is found that
proposed power gated BCD adders.
the occurrence of the surge current is minimized to a great
extent when we use the power gating structures. The VI
characteristic of a CMOS 4-bit BCD adder is shown in the
figure 9. The figure 10 and 11 show the VI characteristics of
the circuit implemented with DSTN and Clock Gated
Structures respectively.

978-1-61284-653-8/11/$26.00 2011 IEEE 691

Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

Figure 9: VI characteristics of conventional 4-bit BCD

adder.
Figure 11: VI characteristics of 4-bit BCD adder with clock
gated Power gating.

In the above graphs, the voltage is given below and

the current values are given in top portion of the graph.

IV. PERFORMANCE ANALYSIS

A. Power Analysis

From the values of drain current and voltage across the

circuit, the power consumed by each of the circuit is
calculated and listed in the table 1. The power consumption
of power gated circuit is lower than the normal circuit. Also,
it is found that the clock gated power gating design performs
better than the DSTN design. The power consumed (in mW)
by each circuit at various time instants is tabulated.

Power Consumed(in J.1W)

s. Conventiona BCD
N Time I adder BCD adder
0 (ns) BCD adder (DSTN) (Clk gated)

1 0.1 0.514 0.5292 0.529

2 0.2 0.6625 0.55592 0.5559

Fig 10: VI characteristics of 4-bit BCD adder power gated
With DSTN. 3 0.3 0.1624 0.0986 0.0864

4 0.4 0.00312 0.0311 0.01071

5 0.5 0.0371 0.00441 0.000234

6 6 0.00265 I 0.000856 0.000051

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Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

B. Delay Analysis
7 6.1 0.001647 0.0001688 0.0000323

8 6.2 0.001342 0.0001653 0.000074 The delay analysis is preformed to calculate the
delay arising across the circuits designed above. This
9 6.3 0.0012 0.000164 0.00000755 allows us to determine the time interval for exciting the
sleep transistors. The results of delay analysis are listed
lO 6.4 0.00996 0.0001516 0.00000232
below.
11 6.5 0.OlOO12 0.0001624 0.00000128
12 19.2 0.00992 0.0001545 0.00000118
SNo Circuit Delay Power Delay
(in ps) Prod uct(,....)
Tablel: Power consumed conventional BCD adder,
BCD adder with DSTN and BCD adder with clock gated 1 Conventional 82.50 11.846
power gating. BCD adder

2 BCD 77.15 7.846

A graph is drawn using the above values. They
adder(DSTN)
provide a comparison of the performance of the power gated
circuits at 65nm scale. Finally, the average power consumed 3 BCD 72.36 6.138
by each circuit is listed. The clock gated design performance adder(Clock
is found to be optimum and it performs better than DSTN. gated)

---
0.7 - Table 2: Comparison of Delay and Power delay product
Of conventional BCD adder, BCD Adder with
0.6 +-Jf.I------
Clock gated power gating.
05
-+-conventional BCD v CONCLUSION
g::I. 04 adder

OJ +-----\1-- .... BCD adder with DST N Sleep transistor is designed at 65nm scale and

Q. implemented in power gating designs. The power gating
0.2 +----tf----
___ BCD adder with clock designs discussed in this project are DSTN and Clock
gated power gating
0.1 +-----1Itt--- gating. The sleep transistors in each cluster is connected by
means of daisy chain implementation which provides

1 2 3 4 5 6 7 8 9 10 11 12
enough time for the results to propagate from one cluster to

Time(io os) the other, thus synchronizing the circuit operation with
triggering of sleep transistors. Clock gating method is
introduced in power gating design, which provides
Fig 12: Power Consumed by conventional 4- bit BCD additional control over the excitation process of sleep
Adder, BCD adder with DSTN & Clock gated 4- transistors.
Bit BCD adder.
Finally, the performances of the DSTN and Clock

0.16 ,-----
Gating are compared in terms of power consumption of the
circuit and surge current. It is found from the results that the
0.14
power gating design is more efficient than the DSTN circuits
0.12 designed at 65nm scale.
0.1
REFERENCES
0.08

average power consu med

0.06
(W) 1. Abdullah A, Fallah F, and Pedram M, (Jan. 2007)
0.04 "A robust power-gating structure and power mode
transition strategy for MTCMOS design" IEEE
0.02
Trans. Very Large Scale Integr. (VLSI) Syst., Vol.
15, No.1, pp. 80-89.
Conventional BCD BCD
2. Chang H, Lee C, and Sapatnekar S.S, (2005) "Full
BCD adder adder(DSTN) adder(Clock
gated)
chip analysis of leakage power under process
variations, including spatial correlations" in Proc.
Des. Autom. Coni (DAC), pp. 523-528.
Figure 13: Average power consumption. 3. Chen Y.T, Juan L.C, Chang S.C, (2007) "An
efficient wake-up schedule during power mode

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Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)

transItIOn considering spurious glitches

phenomenon" in Proc. Int. Coni Comput.-Aided
Des. (ICCAD), pp. 777-782.
4. Designing Low-Power Circuits: Practical Recipes
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and implementation Simple concepts yet challenges
to be optimum" in Proc. VLSI-DAT, pp. 1-4.
6. Pan Z.D, Ramalingam A, Devgan A, (Apr 2007)
"Wake-up scheduling in MTCMOS circuits using
successive relaxation to millimize ground bounce"
ASP J. Low Power Electron. (JOLP), Vol. 3, No. 1,
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7. K. Shi and D. Howard, "Sleep transistor design and
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8. J. P. Uyemura, Introduction to VLSI Circuits and
Systems. New York: Wiley, 2002.
9. C. Long, J. Xiong, and L. He, "On optimal
physical synthesis of sleep transistors," ill Proc.
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network for power reduction," IEEE Trans. Very
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937-946, Sep. 2004.

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