A High Capacitive-Coupling Ratio (HiCR) Cell

for 3 V-Only 64 Mbit and Future Flash Memories

Yosiaki S. Hisamune, Kohji Kanamori, Taishi Kubota, Yoshiyuki Suzuki,
Masaru Tsukiji, Eiji Hasegawa, Akihiko Ishitani, and Takeshi Okazawa
ULSI Device Development Labomries.
NEC Corporation
1120 Shimokuzawa. Sagamihara, Kanagawa 229, Japan

Abstract undemeath the floating-gate side walls. The cell is designed

to have ultra-small tunneling regions (0.2 pm x 0.4 p)and
A novel contactless cell with b h capacitivesoupling a large floating-gate area (1.4 p m x 0.4 pm) in order to
ratio (Him) of 0.8, which is programmed and erased by obtain the high capacitive-coupling ratio of 0.8. Here, the
Fowler-Nordheim tunneling, has been developed for 3 V-only capacitive-coupling ratio, CRE, is defined by
64 Mbit and future flash memories. A 1.50 p2 cell area is CRE = CFG/ CT
obtained by using a 0.4 p m technology. The HiCR cell where CFG is the capacitance of the interpoly pxide-nitride-
structure is realized by 1) self-aligned definition of small Qxide (ONO) dielectrics between the control gate and the
tunneling regions undemeath the floating-gate side wall and floating gate, and CT is the total capacitance of the floating
2) advanced rapid thermal process for 7.5-nm thick tunnel gate-
oxynitride. The internal voltages used for PROGRAM and The cell is programmed by Fowler-Nordheim tunneling
ERASE are +8 V and +12 V, respectively. The total process- across the 7.5 nm oxynitride from the floating gate to the
step numbers can be reduced to 85 % compared to reported drain junction. Erase is also accomplished using Fowler-
memory cells so far. Nordheim tunneling from the source/drain junctions to the
floating gate (Fig. 2).
The fabrication process is based on a 0.4 pm CMOS
Introduction technology. Figure 3 shows the major processing steps to
form the HiCR cell structure. A modified LOCOS is used
Fast low-power nonvolatile memories are required for for the array isolation. The first polysilicon, silicon oxide,
future handheld computers and mobile computing systems to and silicon nitride stacked layer are formed and pattemed (Fig.
store operating systems or application software. For these 3a). A silicon nitride sidewall is then formed and thermal
applications, fast random-access high-density flash memories oxidation is carried out followed by sourcddrain implantation
are the most suitable devices. Recently, several innovative (Fig. 3b). Thus, the buried n+ diffusions are self-aligned to
technologies and new cell structures have been proposed for floating gates. After etching the silicon nitride and sacrificial
high-density 3-V power supply nonvolatile memories. silicon oxide films, the tunnel oxynitride is grown to 7.5 nm
However, these cells require high breakdown-voltage in these removed sidewall regions, and polysilicon films are
transistors for high internal voltage (> 18 V) operation [l] or deposited (Fig. 3c). The polysilicon films are etched back to
complex decoders and triple wells for negative internal form sidewalls (Fig. 3d) and the second polysilicon films are
voltage operation [2,3]. deposited (Fig. 3e). Finally, the second polysilicon is
This paper describes a novel contactless cell with a high pattemed, the 13-nm thick interpoly ONO dielectric is
capacitive-coupling ratio and its pracess technologies to formed, and then tungsten polycide films are deposited and
produce 3 V-only 64 Mbit flash memories. pattemed to form a stacked gate structure (Fig. 30. An SEM
photograph of the finished cell is shown in Fig. 4.
An advanced rapid thermal process is developed for the
Cell Structure and Technology tunnel oxynitride films. The process parameters are
summarized in Table 1.
The cell layout and cross sections are shown in Fig. 1. It
is a floating-gate type transistor, self-aligned with a buried
N+ some and drain. The unit cell area per bit (one memory Cell Array Architecture
cell, 2/32 select transistor and 1.5/32 contact hole area) is
1.50 pm2 based on a 0.4 pm design rule. The gate The new PROGRAM and ERASE scheme is shown in Fig.
dielectrics consist of 20-nm thick thermal oxide grown on the 5. To prog a cell, a pulse of 8 V is applied to selected bit
channel region and 7.5-nm thick silicon oxynitride formed line with the selected word line tied to ground and the source

2.3.1
0-7803-1450-6 $3.00 O 1993 IEEE IEDM 93-19

T
floating. During programming, the unselected bit line is
kept open and the unselected word line is applied to 5 V in
order to minimize the memory cell disturbances due to
Fowler-Nordheim tunneling current through the tunnel
oxynitride. To erase a cell, 12 V is applied to the word lines
with the bit lines and the source lines to ground. All
operating voltages, +8 V for PROGRAM, +5 V for PROGRAM
inhibit, and +12 V for ERASE, can be internally generated
from the 3-V supply through charge-pump circuits. This
PROGRAM and ERASE scheme results in a 15 96 reduction of
process s t e p which yields low-cost advantages compared to
conventional scheme, as explained in Table 2.
A schematic diagram of the memory cell array is shown
in Fig. 6. The memory cell m y has NOR structure, with
select transistors which act as switches for connecting and
disconnecting the target block to a main data line and a main
some line.
C. Endurance
Singlecell endurance characteristics are shown in Fig. 12.
The cell can withstand more than 100,ooO PROGRAM/ ERASE
cycles.
Conclusion
The HiCR cell for 3 V-only 64 Mbit, which utilizes
Fowler-Nordheim tunneling for PROGRAM and ERASE. has
been demonstrated. The intrinsic cell characteristics have
been examined. The cell performance is acceptable for actual
device operation in 3-V power supply. Moreover, the new
PROGRAM and ERASE scheme, which requires only non-
negative intemal voltage generation as low as 12 V, results
in a 15 Ireduction of the process steps. This memory cell
is promising for low cost, future generation flash memories.

Cell Characteristics
A. Programming and Erase
The programming characteristics of the obtained cell are
shown in Fig. 7. The cell can be programmed to l-V
threshold voltage using a 1-ms, 8-V drain pulse. The
substrate current of the cell during programming is low
enough to pgram 512-byte cells connected to the same word
line simultaneously, as shown in Fig. 8. The example of the
cell erase is shown in Fig. 9, where erase time is less than
100 ms by applying 12 volts to the control gate. These
characteristics are well-described by the conventional
modeling based on the Fowler-Nordheim expression.
Acknowledgment
The authors would like to thank Drs. M. Kamoshida, M.
Ogawa, M. Kikuchi, and J. M. Drynan for their continuous
encouragementand helpful discussions.
References
[ 11 T. Tanaka et. al., 1992 Symposium on VLSI Circuit, Digest
of Technical Papers, pp.20-21
[2] H . Kwne et al., 1992 IEDM Technical Digest, pp. 991-993
[3] H.Onada et al., 1992 IEDM Technical Digest, pp. 599-602

B. Program Disturbance

There exist two principal disturbances that can occur

during programming of an array [see Fig. 51. Disturbance I
is unexpected programming of the cell (12)connected to the
same source line (S)and to the selected word line (Wl). It 02. 115oc.6oseJc
is caused by the source voltage, VCG - VTM, of the cell,
where VCG is the program inhibit voltage of the unselected Table.1 7.5-nmthick tunnel oxynitride process.
word line (W2) and VTM is the threshold voltage of the
erased cells (the cell 21 works as a pass transistor when it is
erased). Disturbance I1 is unexpected programming of the
HER all
cells (21,22, ...)connected to the selected bit line (Bl).
0.83
These problems can be solved by utilizing the parallel
programming and sub-bit lines. The maximum duration of 0.97
Disturbance I is only 1 write cycle (1 ms) by the use of a
latch circuit. That of Disturbance I1 is 31 write cycles (31
OdO
ms) by setting the select transistors off except in the
programming mode. Characteristics of the Disturbance I and
11, which have sufficient margin for device operation, are Table2 HiCR cell has 20% cost advantage comparing
shown in Figs. 10 and 11,respectively. with conventional F-N tunneling cell.

2.3.2
20-IEDM 93

-~
ir ~ ~

1
A

I
Fontmigate

Floatinggate

ONO 13nm
In+-dMon
\ (drain)

n+-diffusion (source)
(a) celi layout

Gate oxide 20nm

Tunneling region
Tunnel oxynitride 7.5nm
@) cross section of the cell parallel to word line
Fig. 1 HiCR cell structure

vcgrov
0 Vdm8V
A'
-I

(d)
p-sub

V
Tunnel oxynitride
I

I I
(a) PROGRAM
vcgr12v
V*OV Q VdrOV

I I
(b) ERASE
Fig.2 Schematic of HiCR cell operation Fig.3 Key process steps for HiCR cell. Tunneling re-
gions are defined under the Si,N, side walls (step @)).
Bl S 82
w1-

w2-

Cell (1.1) operatingconditions

Fig5 Array operation

Fig.4 SEM cross section of HiCR cell.

2.3.3
IEDM 93-21

~~

1 ~~
 B1 s12 82

SG1

w1

w2

I
I
I
1.oM-07 1.00E-06 l.OOE-06 1.00E-U 1.WE-03 1.WE-02 1.WE-01 1.00E+M)
TIME (sec)

Fig.9 Erase chracteristics of the cell as a function of control

gate voltage variation.
6

(n+-diftuolon) 5
SG2

II 'Maln
II
~ O W C Olino
z4
(m-0 E3
Fig.6 Schematic of memory array 2

0
1.WE-07 1.WE-06 1.WE-05 1.OOE-04 1.WE-03 1.WE-02 1.WE-01 l.WE+oo
TIME (sec)
Fig.10 Threshold-voltageshifts during Disturbance I. The cell
was programed to a Vt of 5V before Disturbancemeasurement.
Maxmum Disturbance I is 1 write cycle(lms).
6

1.oM-07 1.IXlE-06 1.ooE-06 l.ooE.04 1.ooEo3 1.ooE-02 1.WE-01 l.OOE+oo

E
TIME (sec) E3
2
Fig.7 Programming characteristics of the cell as a function of
drain voltage variation. 1

0
l.00E-07 1.WE-06 1.WE-05 1.WEM 1.WE-03 1.WE-02 l.WE-01 l.OoE+oo
TIME (sec)
Fig. 11 Threshold-voltage shifts during Disturbance 11.
Maxmum DisturbanceII is 31 write cycle(3lms).

-= 8V;lmlE-3~

Program

Fig.8 Substrate curcent versus the drain voltage measured with loo 10' lo2 io3 10' io6
control-gate and floating-gate shorted (Vcg = Vfg = -3V). W E Cycles
Fig.12 Endurancecharacteristics of the cell.

2.3.4
22-IEDM 93
rl-