DIRECT DIGITAL FREQUENCY SYNTHESIS USING A MODIFIED CORDIC

Eugene Grayver, Babak Daneshrad

Integrated Circuits and Systems Laboratory
UCLA, Electrical Engineering Department
babak@ee.ucla.edu

ABSTRACT An alternative method for generation of a sinusoid is based on

This paper introduces a new approach to direct digital frequency trigonometric definition and properties of the sine and cosine.
synthesis (DDFS) based on the Coordinate Rotation (CORDIC) This method, known as coordinate rotation (CORDIC) [3],[6],
algorithm. The modifications to the standard CORDIC algorithm requires very few constant coefficients and is more suitable for
introduced in this paper allow fine frequency resolution, and implementation in a flexible ASIC architecture or a general
exhibit significant potential for low power applications. The new purpose processor. Two major problems have prevented use of
architecture does not need a large ROM and can be implemented the CORDIC algorithm in DDFS architectures, namely poor
on a general purpose processor, or on a flexible ASIC frequency resolution and potentially high power consumption. The
architecture. architecture proposed in this paper introduces modifications to the
classical CORDIC algorithm that circumvent both of these
problems.
1 DIRECT DIGITAL FREQUENCY SYNTHESIS
All passband communication systems employ some form of
up/down conversion. Frequency conversion is required to 2 CONVENTIONAL CORDIC
transmit the data in the desired frequency band. Different In the CORDIC algorithm [6], sine & cosine of the desired angle
frequency bands are also used to allow efficient use of the are calculated using a cascade of N sub-rotation stages. The kth
allocated spectrum when using FDMA. The baseband signal is stage rotates the input complex number, considered as a 2 element
up/down converted by either multiplication by a sinusoid of vector (2-vector), by /2k (=/2) radians depending on the kth
controllable frequency (e.g. QAM) or by directly modulating the bit of W. By changing the phase control word we can rotate an
frequency of the sinusoid (e.g. FM, GMSK) [1]. A fully digital initial vector by any angle in the range [0..-/2N+1] in increments
implementation of any communication system requires direct of /2N radians. Each stage implements a Givens plane rotation,
digital frequency synthesis (DDFS) [1],[2] . Digital frequency
of the form:
synthesis is also preferred over the analog approach due to lower
phase noise, fine frequency resolution and the ability to rapidly
x cos sin x 1 tan x
y = sin cos y = cos tan
change frequency.
1 y
(2).

Conventional methods for digital frequency synthesis use a phase
accumulation technique, as shown in Figure 1. The phase control CORDIC based designs recognize that the multiplications by
word, W, is continuously increased in constant increments of . cos() for all sub-rotation stages can be collected together into a
W is used as an argument to a sine lookup table or generator. single constant
Since frequency is defined as the derivative of the phase, the N 1
output of the sine generator is a sinusoid of a constant frequency, = cos( k ) (3)
determined by . This derivation is summarized in equation (1) k =0
[1],[2]. which is independent of the overall angle. Using the definitions in
equation (4),

N bits Sin() x 0 = ; y 0 = 0; N = number of stages; Tk = tan k
+ Look Up or 2
Reg Sin(W)
(4)
W Generation N
1 1 when the k bit of W is 1
th
= ak i ; a k = th
Figure 1. Conventional frequency synthesis architecture k =2 2 - 1 when the k bit of W is 0
the rotation by the angle set by W is summarized in equation (5).
W 1 d
W (t ) = f clk t; (t ) = ; f out = = f clk (1) x k 1 Tk y k 1 , y k 1 + Tk x k 1 when W [k ] = 1
2N 2 d t 2 N +1 ( xk , yk ) =
x k 1 + Tk y k 1 , y k 1 Tk x k 1 when W [k ] = 0 (5)
Most of the DDFS designs used today store pre-computed samples
of a sinusoid in a ROM lookup table [2]. A major disadvantage of x N = cos( ), y N = sin( )
this approach is the requirement of a rather large ROM in order to By continuously incrementing W we can obtain Sin/Cos(t)
achieve acceptable spectral purity. In traditional ROM based thereby generating a sinusoid, as shown in Figure 2. Note that
DDFS systems, the size of the ROM grows exponentially with equation (1) applies to this architecture as well.
spectral purity.

N bits Cos(W)
+ Reg 0 Sin(W)
W consumption and the chip area, making the traditional architecture
Figure 2. Traditional CORDIC architecture for DDFS
A DDFS system implemented using this method suffers from two
problems: The frequency resolution is determined by the number
of stages, and is given by
1 f is the clock frequency
f min = f clk where clk (6).
2 N
N is the number of stages
For high clock frequencies, a large number of CORDIC stages are
needed to obtain sufficiently fine frequency resolution. Also,
since W changes on every clock, all of the sub-rotation stages have
to operate at the clock frequency, using a significant amount of
energy.
3 PROPOSED ARCHITECTURE
3.1 Recursive Computation
The periodic nature of a sinusoid makes it ideally suited for
recursive computation. By continuously executing equation (7),
with the angle of rotation, , determined by the desired frequency,
a sustained sinusoid can be obtained.
x (n + 1) = x ( n ) cos y ( n ) sin f desired
= 2
y ( n + 1) = y ( n ) cos + x( n ) sin f clk
Once Sin() and Cos() corresponding to the desired frequency
have been computed, a feedback circuit implementing equation (7)
can be used to generate the sinusoid at the desired frequency.
The first modification to the standard CORDIC algorithm
introduced in this paper is shown in Figure 3. The first N-1
stages, identical to those used in Figure 2, are used to compute
Sin() and Cos(). The last stage implements the recursive
equation (7), generating a sustained sinusoid.
Precompute Stages Feedback Stage
Cos
0 Sin
W A number of papers [4],[5] have addressed the issue of spurs in
Figure 3. CORDIC with a feedback stage (first modification)
It is important to note that the pre-compute stages are only used
for at most N clock cycles every time W changes. Generation of a
constant frequency sinusoid uses only the last stage, making this
architecture significantly more power efficient than the classical
CORDIC DDFS architecture. A simple circuit can be used to
enable the pre-compute stages only when W changes.
3.2 Frequency Resolution
The traditional CORDIC DDFS architecture requires a large
number of stages to achieve fine frequency resolution at high
clock frequencies since f min f clk , as can be seen from
equation (6) (e.g. 26 stages are needed to achieve frequency
resolution of 1Hz at the clock frequency of 50MHz). Increasing
the number of stages has a negative impact on both the power
impractical.
The second modification to the CORDIC DDFS architecture
introduced in this paper allows fine frequency resolution without
requiring a large number of stages. To achieve fine frequency
resolution an additional sub-rotation stage is introduced, Figure 4.
This stage rotates by the same angle as the last precompute stage
(/2N-2 radians). Unlike the previous stages, it is controlled by the
MSB of an accumulator. Every time the accumulator reaches its
maximum value, the vector is rotated by an additional /2N-2
radians. An M-bit accumulator provides a frequency resolution of
1 1 1
f min = f clk = N + M 1 f clk (8).
2 N 2
2 M
2
Since M can be increased at very little cost, exteremely fine
frequency resolution is available. The frequency control word, W,
is N-2+M bits, with N-2 MSB bits controlling the sub-rotation
stages, and the remaining M bits going to the accumulator. The
addition of this stage has very little impact on the overall power
consumption of the circuit. Just like the other pre-compute stages,
the fine frequency resolution stage is off most of the time. The
only extra power is dissipated in the multiplexer every time the
accumulator overflows. A complete architecture, incorporating
the two modifications introduced above is presented in Figure 4.
(7)
Fine Freq. Feedback Stage
N-2 Precompute Stages
Resolution Stage
Cos
0 Sin
W[1..N-2] M bits
W[N-1..N-2+M] + Reg
Figure 4. DDFS using modified CORDIC
3.3 Spectral Characteristics
digitally synthesized waveforms. Derivations shown in these
papers prove that spurious free dynamic range (SFDR) of a
sinusoid obtained using direct digital frequency synthesis depends
on the smallest angle that can be resolved by the DDFS system
and on the finite precision calculations. The spurs due to finite
precision calculations are negligible. If the smallest angle is 2-N,
the SFDR is approximately given by 6N dB. For the purpose of
spectral analysis, the architecture presented above is equivalent to
a ROM based DDFS with an 2N word ROM.
In the proposed architecture, the SFDR can be increased by
adding more stages to the pre-compute part of the circuit.
However, the number of stages is limited by the width of the
databus. Since
 S inus oid decays
tan( x ) ~ x for x ~ 0 Tk = tan( k
) ~ 2 ( k +1) (9), 1
2
at least k bits are required to represent Tk. Thus, in order to
effectively utilize more stages, the width of the databus must be (a)
increased. If 14 precompute stages are used, with a 16bit wide
databus, the expected SFDR is 14*6=84. Results of a bit and
-1
cycle accurate simulation, shown in Figure 5, confirm this S am ple #
1000 2000 4000 5000
calculation.
Overflow c orruption
1

60
Power Spectrum Magnitude (dB)

(b)
40
80dB
20
-1
0 50 S am ple # 150 200
0
Figure 6. Finite Precision Effects
-20
A similar problem is solved in [7] by periodically resetting the
-40
system to a known state. Use of this method in the proposed
-60 architecture has a negative impact on the spectral characteristic of
0 0.1 0.2 0.3 0.4 0.5
the sinusoid (Figure 7b). This can be alleviated by introducing a
Figure 5. Spectrum for N=14 correction instead of resetting. Figure 7a shows a 15dB SFDR
To summarize the points made above: SFDR depends only on the gain when using correction instead of resetting.
Correction Resetting
number of precompute stages and is independent of the output
60 60
frequency, main clock frequency. The frequency resolution is
Power Spectrum Magnitude (dB)

Power Spectrum Magnitude (dB)

determined entirely by the sum of the number of precompute 40 50dB 40 35dB
stages and the width of the accumulator for the fine frequency
resolution stage. Thus, the number of precompute stages can be 20 20
decreased without affecting the frequency resolution, provided the
accumulator width is increased. It is therefore possible to 0 0
trade-off SFDR for circuit size by removing precompute stages
while retaining the same frequency resolution. The power -20 -20
consumption is determined only by the main clock frequency. It is
-40 -40
independent of the frequency of the output sinusoid, and shows
very weak dependence on the number of precompute stages. -60 -60
0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4
a b
3.4 Finite Precision Effects
An inherent difficulty in realizing recursive architectures is Figure 7. SFDR using the correction and resetting methods
accumulation of error caused by finite precision calculation. A The correction circuit is inserted in the feedback path of the last
multiplication of two L bit numbers results in a 2L bit number. CORDIC stage as shown in Figure 8. The details of this circuit
Since a constant data bus width is desirable, multiplication results are discussed in the ensuing sections.
must be truncated, thereby incurring a loss of precision. If
truncation decreases the number, the sinusoid generated by this Correction
architecture will decay, as shown in Figure 6a; if truncation Circuit
increases the number, the sinusoid will be corrupted by overflows, Precomputed Cos
as shown in Figure 6b.
Sin & Cos Sin
Feedback Stage
Figure 8. Feedback stage

3.4.1 Correcting Decaying Sinusoid

If the sinusoid is decaying, the correction necessary to prevent the

accumulation of error in the feedback DDFS is based on the
relationship cos 2 + sin 2 = 1 . Rewriting in terms of the
variables in equation (5) and applying Taylor expansion we get
 y2
x = 1 y2 1 . The approximation is very good for
2
small values of y. The correction is therefore applied once a preset
delay (tdelay) has elapsed and the value of y is below a preset value
(ymax). Suitable values for these parameters were determined
expreimentally to be: tdelay=60 cycles, ymax =1/16. The entire
correction circuit is shown in Figure 9.
1
+ Sin(t)
Cos
Sin
-
2
Counter < And
Reset Preset Carry
Figure 9. DDFS feedback correction (decaying)
3.4.2 Correcting Growing Sinusoid
If the sinusoid is growing, a different correction technique should
be used. As can be seen from Figure 6b, when the sinusoid is
growing, it is corrupted by overflows. In 2s complement binary
representation, an overflow causes a sign change. This type of
overflow can be easily detected and corrected using the circuit
shown in Figure 10.
A 1
x x A>0 & B>0 & C<0 (overflow)
C=A+B z Y S= y A<0 & B<0 & C>0 (underflow)
B -1 y computation, the architecture exhibits significant potential for low
3:1 MUX
S
Figure 10. DDFS feedback correction (growing)
Simulations show that better SFDR can be obtained using the
second correction method. An interesting property of the 2s
complement notation allows us to determine whether the sinusoid
will be growing or decaying. If a positive 2s complement number
is truncated, its magnitude is decreased; if a negative 2s
complement number is truncated, its magnitude is increased.
Thus, if the coefficients calculated by the pre-compute stages are
positive, the sinusoid will decay, otherwise it will grow. If
equation (5) is implemented directly, the coefficients will be
positive, and the first correction method has to be used. However,
if the value of x0 is set to instead of , the coefficients will be
negative and the sinusoid will grow. The current implementation
of the proposed architecture uses the second approach.
3.5 Hardware Implementation
There exist a number of ways to implement equation (5) [6]. Pre-
compute stages can be designed to be multiplierless [6]. The
architecture presented in this paper allows for a straightforward
mapping onto a flexible ASIC core as shown in Figure 11 and
discussed in [8].
W
N W[0] W[1]
0
Cos(t)
Where each is C
Figure 11. Detailed DDFS architecture
The feedback stage, which implements equation (7), cannot
exploit the simplification shown in equation (2), since the
precompute stages generate sine and cosine, and not a tangent.
The last stage must therefore consist of four multipliers, as shown
in Figure 11. It is possible to use a two multiplier feedback stage
if a tangent is first computed.
4 CONCLUSION
A novel architecture for direct digital frequency synthesis has been
presented. The architecture takes advantage of the periodic nature
of a sinusoid to allow generation of a sustained sinusoid using just
four multipliers. A modification to the CORDIC algorithm allows
very fine frequency resolution using a limited number of
sub-rotation stages. Since only the last stage is needed for the
power applications.
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