MANUAL COMPLETO

TTL INDICE

- CARACTERSTICAS DE LOS CIRCUITOS DIGITALES

- ESCALAS DE INTEGRACIN DE LOS CIRCUITOS DIGITALES
- SSI, MSI, LSI, VLSI.
- FAMILIAS LOGICAS DE LOS CIRCUITOS DIGITALES
- CARACTERSTICAS DE LAS FAMILIAS DIGITALES
- OTROS CIRCUITOS INTEGRADOS TTL
- ABREVIATURAS DE LOS CIRCUITOS DIGITALES
- INDICE SEGN LA CARACTERSTICAS DE LOS TTL
 Caracteristicas generales
de los circuitos digitales
ESCALAS DE INTEGRACION DE LOS
CIRCUITOS DIGITALES
De acuerdo a su complejidad, los circuitos
integrados digitales se clasifican en 4 categoras
bsicas llamadas SSI, MSI, LSI, y VLSI. Esta
clasificacin se fundamenta en la cantidad de
compuertas utilizadas para implementar la funcin
propia del chip. Como sabemos, las compuertas son
los bloques constructivos bsicos de todos los circuitos
Digitales.
SSI
Significa Small Scale Integration (integracin en
pequea escala) y comprende los chips que contienen
menos de 13 compuertas. Ejemplos: compuertas y
slip-flops. Los CI SSI se fabrican principalmente
empleando tecnologas TTL, CMOS y ECL. Los
primeros circuitos integrados eran SSI
MSI
Significa Mdium Scale Integration (integracin en
mediana scala) y comprende los chips que contiene de
13 a 100 compuertas. Ejemplos; codificadores,
registros, contadores, multiplexores,
decodificadores,demultiplexores. Los CI MSI se
fabrican empleando tecnologas TTL, CMOS y ECL.
LSI
Singnifica Large Scale Integration (integracin en alta
scala) y comprende los chips que contienen de 100 a
1000 compuertas. Ejemplos: memorias, unidades
aritmticas y lgicas (ALUs), microprocesadores de 8
y 16 bits. Los CI LSI se fabrican principalmente
empleando tecnologas 12L, NMOS y PMOS.
VLSI
Significa Very Large Scale Integration (integracin de
muy alta escala) y comprende los chips que contienen
ms de 1000 compuertas, Ejemplos:
microprocesadores de 32 bits, microcontroladores,
sistemas de adquisicin de datos. Los CI VLSI se
fabrican tambin empleando tecnologas 12L, NMOS y
PMOS.
FAMILIAS LOGICAS DE LOS CIRCUITOS
INTEGRADOS
Una familia lgica es un conjunto de componentes
digitales que comparten una tecnologa comn de
Fabricacin y tienen estandarizadas sus
caractersticas de entrada y salida; es decir, son
compatibles unos con otros.
Como consecuencia de la estandarizacin, la
interconexin entre dispositivos lgicos de una misma
familia es particularmente sencilla y directa: no
requiere de etapas adicionales de acoplamiento.
CARACTERISTICAS GENERALES DE LAS
FAMILIAS LGICAS
Todas las familias o tecnologas de fabricacin de
circuitos integrados digitales se agrupan en dos
categoras generales: bipolares y MOS. Las
caractersticas ms relevantes de un circuito integrado
digital con su velocidad, su consumo de potencia, su
inmunidad al ruido y su confiabilidad. A continuacin se
definen estos trminos, desde un punto de vista
general.
La Velocidad
Mide la rapidez de respuesta de las salidas de un
circuito digital a cualquier cambio en sus entradas. La
velocidad es una consideracin importante en el
diseo de sistemas que deben realizar clculos
numricos o en circuitos que trabajan con seales de
alta frecuencia.
El consumo de potencia mide la cantidad de
corriente o de potencia que consume un circuito digital
en operacin. El consumo de potencia es una
consideracin importante en el diseo de sistemas
operados por bateras
La inmunidad al ruido
Mide la sensibilidad de un circuito digital al ruido
electromagntico ambiental. La inmunidad al ruido es
una consideracin importante en el diseo de sistemas
que deben trabajar en ambientes ruidosos com
automviles, mquinas, circuitos de control industrial,
etc.
La confiabilidad
Mide el perodo til de servicio de un circuito digital, es
decir, cunto tiempo se espera que trabaje sin fallar
Niveles de voltaje y estados lgicos
En todos los circuitos digitales prcticos los estados
lgicos 1 y 0 se implementan con niveles de voltaje.
Estos niveles tienen rangos muy definidos, separados
por una zona de valores invlidos como se muestra en
la figura siguiente
Voltaje
Niveles de voltaje
V3
Estado alto vlido
V2
Valores invlidos
V1
Estado bajo vlido
V0
Tiempo
En esta figura, el nivel bajo vlido es el rango de
voltajes entre V0 y V1, mientras que el nivel alto vlido
es el rango de voltajes entre V2 y V3.
Los voltajes superiores a V3 inferiores a V0 son
generalmente dainos para los dispositivos digitales y
deben evitarse. Generalmente, V0 corresponde a un
nivel de 0 voltios y V3 al valor del voltaje de
alimentacin (5V, 9V, etc.).
La zona de niveles invlidos entre V1 y V2 es crtica.
En esta rea los circuitos digitales trabajan en forma
errtica porque no saben qu hacer. Un voltaje en ese
rango pude ser interpretado como un 1 lgico o como
un 0 lgico o no producir efectos alguno. Los niveles
de voltaje en circuitos integrados digitales varan de
acuerdo con la familia lgica (TTL o CMOS) a la que
pertenece el dispositivo.
Como hemos visto anteriormente en la tabla anterior
hay muchas familias lgicas en las cuales se
diferencian por las caractersticas anteriores
mencionadas pero que en este estudio veremos dos
de las familias mas utilizadas y mas conocidas por su
versatilidad y por su comodidad en el manejo de ellas
mismas, las cuales son los TTL y los CMOS.
LA FAMILIA DE LOS TTL
La familia lgica TTL es quizs la ms antigua y comn siguientes:
de todas las familias lgicas de circuitos integrados
digitales. La mayor parte de los chips SSI y MSI se
fabrican utilizando tecnologa TTL.
Los circuitos integrados TTL implementan su lgica
interna, exclusivamente, a base de transistores NPN y
PNP, diodos y resistencias.
La primera serie de dispositivos digitales TTL fue
lanzada por Texas Instruments en 1964. Los chips TTL
se usan en toda clase de aplicaciones digitales, desde
el ms sencillo computador personal hasta el ms
sofisticado robot industrial. Los circuitos TTL son
rpidos, verstiles y muy econmicos.
La familia TTL esta disponible en dos versiones: la
serie 54 y la serie 74. La primera se destina a las
aplicaciones militares y la segunda a aplicaciones
industriales y de propsito general. Los dispositivos de
la serie 54 tienen rangos de operacin de temperatura
y voltaje ms flexible (desde -55 hasta 125C contra 0
a 70C de la serie 74).
La familia TTL., o bipolar se divide en las siguientes
Categoras o subfamilias bsicas:
TTL STANDART
TTL SHOTTKY (S)
TTL DE BAJA POTENCIA (L)
TTL SHOTTKY DE BAJA POTENCIA (LS)
TTL DE ALTA VELOCIDAD (H)
TTL SHOTTKY AVAVNZAD (AS)
TTL SHOTTKY DE BAJA POTENCIA AVANZADA(ALS)
Otra familia bipolar muy popular es la ECL (Lgica de
emisor acoplado). Los dispositivos de esta familia se
caracterizan por su rapidez, pero consumen mucha
potencia, son costosos y su manufactura es
relativamente compleja. Su uso se limita a aplicaciones
de muy alta velocidad.
TTL estandard
Estndar La familia estndar comprende
principalmente los dispositivos que se designan como
74xx (7400, 7447, etc.). 74xxx (74123, 74193, etc.),
8xxx (8370, 8552, etc.) Y 96xx (9601, 9615, etc.),
Trataremos con preferencia la 1 series 74xx y 74xxx
que son las ms utilizadas en los circuitos modernos.
Existe una gran cantidad de funciones lgicas que se
realizan con esta tecnologa. Entre las principales
tenemos: compuertas, decodificadores, contadores, flip
flop, sumadores, multiplexores y muchas otras que
estudiaremos mas adelante.
Caractersticas de los circuitos integrados
TTL
Las caractersticas que ms se notan de los circuitos
integrados de la familia TTL, estndar son, los
Alta velocidad de operacin. Pueden trabajar con
frecuencias de 18 a 20 Mhz y en algunas veces hasta
80 Mhz. La velocidadoperacin se expresa casi
siempre en trminos del tiempo o retardo de
propagacin del CI.
El tiempo o retardo de propagacin de un circuito
digital es el tiempo que toma un cambio lgico en la
entrada en propagarse a travs del dispositivo y
producir un cambio lgico en la salida.
Los tiempos de propagacin en TTL normalmente del
orden de 2 a 30 nanosegundos por compuerta.
Alta disipacin de potencia. Es una desventaja
asociada con la alta velocidad de operacin. En
general, cuanto ms rpido sea un circuito, ms
potencia consume y viceversa. La mayora de los
circuitos TTL disipan tpicamente, de 1 a 25 milivatios
por compuerta.
Tensin de alimentacin nominal de +5V. Los circuitos
TTL en general pueden operar con tensiones de CC
entre 4.75 y 5.25 V pero el valor nominal de la tensin
de trabajo es +5 V. Por esta razn, los aparatos que
incluyen circuitos integrados TTL se deben alimentar
con una fuente regulada de 5 voltios.
Niveles de voltaje de 0 a 0.08 V para el estado bajo y
de 2.4 a 5.0 V para el estado alto. En general, los
circuitos TTL interpretan cualquier voltaje entre 0 y
0.8V como un cero (0) lgico o bajo y cualquier voltaje
entre 2.4 y 5V como un (1) lgico o alto.
El mximo voltaje positivo que puede aplicarse a una
entrada TTL es +5.5V y el mxino negativo es -0.5V. Al
excederse estos parametros, los dispositivos TTL
generalmente se destruyen.
Abanicos de entrada (fan-in) y de salida (fan-
out)
La familia TTL utiliza a dos parmetros para determinar
cuntos dispositivos TTL se pueden conectar entre s.
Estos parmetros se denominan abanico de entrada
(fan-out).
El fain-in mide el efecto de carga que presenta una ABREVIATURAS TIPICAS DE LOS
entrada a una salida. Cada entrada de un circuito TTL INTEGRADOS
estndar se comporta com una fuente de corriente
capaz de suministrar 1.8 mA. A este valor de corriente
se le asigna un fan-in de 1.
H = NIVEL LOGICO ALTO (ESTABLE)
L = NIVEL LOGICO BAJO (ESTABLE)
El fan-out mide la capacidad de una salida de = FLANCO DE SUBIDA (paso de nivel
manejar una o ms entradas. Cada salida de un lgico bajo a nivel alto)
circuito TTL estndar se comporta como un disipador = FLANCO DE BAJADA (paso de nivel
de corriente capaz de aceptar hasta 18 mA, es decir de lgico alto a nivel alto)
manejar hastra 10 entradas TTL estndares. Por tanto, X = NIVEL DE ESTADO DIFERENTE
el fan-out de una salida TTL estndar es 10. Z = ESTADO DE ALTA IMPEDANCIA DE UNA
SALIDA (LOGICA TRI-STATE)
Existen dispositivos TTL especiales llamados buffers a...h = EL NIVEL LOGICO ESTABLE DE LAS
(separadores) y drivers (manejadores) que tienen fan- ENTRADAS A...H
outs de 30, 50 r incluso 100. Se utilizan en Qo = SALIDAS DE FLIP FLOP
aplicaciones donde una determinada lnea de salida DATA INPUTS = ENTRADA DE DATOS
debe manejar al mismo tiempo un gran nmero de ENABLE = HABILITADOR
lneas de entrada. Los buffers y drivers se estudian en SELECT = SELECTOR
detalle en las lecciones 6 y 8. CS = SELECTOR DE ENCENDIDO O
APAGADO
GND = TIERRA
Otros circuitos integrados TTL VCC = VOLTAGE
DO.....Dn = ENTRADAS
Existen varias series o subfamilias TTL, adems e la CLOCK = ENTRADA O SALIDA DEL RELOJ
serie TTL estndar 74. Cada una de estas subfamilias INHIBIBIT-OUT = INHABILITADOR DE SALIDA
posee caractersticas propias que las hacen SG = SELECTOR DE GRUPO
adecuadas para aplicaciones o necesidades muy OUTPUT = SALIDA DE CONTROL
especficas. Las ms conocidas son:
TTL de baja potencia. Comprenden los
dispositivos designados como 74L00, 74L04.
Consumen 10 veces menos potencia que los
dispositivos TTL estndares correspondientes pero son
4 veces ms lentos.
TTL de alta velocidad. Comprende los
dispositivos designados como 74Hxx y 74Hxxx; por
ejemplo: 74H05, 74H123. Consumen 2.5 veces ms
potencia que los dispositivos TTL estndares pero son
2 veces ms rpidos.
TTL Shottky. Conprende los dispositivos
designados como 74Sxx y 74Sxxx; por ejemplo
74S181, 74S11. Consumen 1.8 veces ms potencia
que los dispositivos TTL estndares pero son 4 veces
ms rpidos.
TTL Shottky de baja potencia. Comprende los
dispositivos designados como 74LSxx 74LSxxx
(74LS83, 74LS221, etc.). Consumen 5 veces menos
potencia que los dispositivos TTL estndares y son
igual de rpidos. Esta es la subfamilia ms utilizada
entre todas las divisiones de la familia TTL.
TTL Shottky avanzada de baja potencia.
Comprende los dispositivos designados como
74ALSXX y 74ALSXXX; por ejemplo: 74ALS00,
74ALS73. Consumen la mitad de la potencia requerida
por los dispositivos LS equivalentes y son el doble de
rpidos.
TTL Shottky avanzada. Comprende los
dispositivos designados como 74AS xx y 74ASxxx; por
ejemplo 74AS00, 74AS73. Proporciona los ms cortos
tiempos de propagacin que el estado actual de la
tecnologa bipolar puede ofrecer y su consumo es
intermedio entre TTL estndar y LS.
TTL Selector Guide
ANO Gates
Dual 4-lnput
6-Bit Binary Rate Multlplier
ECG7497
Hex Non-lnverting
ECG74365
ECG74H21 9-Bit Perity Generetor/Checker ECG74LS365A
ECG74LS21 ECG74367
ECG74180
ECG74LS367
Triple 3-lnput ECG74SL280
ECG80C95
ECG7411 ECG80C97
ECG74H11
Buffer Gates
ECG74HC11
ECG74LS11
Quad 2-lnput
Quad 2-lnput NANO
ECG7437
ECG74LS37
Bus Transceivers
Octal lnverting
ECG74LS640
ECG7408 Quad 21nput NOR ECG74LS642
ECG74C08 ECG7428
ECG74HC08 Octal lnverting/Non-lnverting
ECG74LS28
ECG74HCT08 ECG74LS643
ECG74LS08 Dual 4-lnput NANO
Octal Non-lnverting
ECG74SD8 ECG7440
ECG74LS245
ECG74H40
ECG74LS641
ANO Gatas with Open
Conector Output
ECG74S40
ECG74LS645

Triple 3-lnput
ECG74LS15
Buffer Gates with Open Collector
Output
Quad lnvertlng
ECG74LS242
Quad Non-lnverting
Hex
Qued 2-lnput ECG7406 ECG74LS243
ECG7409 ECG7407
ECG74LS09 ECG7416
ECG7417 Counters, Asynchronous
Blnary/Ripple
AND/OR/lnvert Gates
2-Wide 4-lnput
Quad
ECG74125
ECG74HC4060
Decade
ECG74HC125
ECG74LS55 ECG7490
ECG74LS125A
ECG74C90
Dual 2-Wtde 2-lnput ECG74126
ECG74LS90
ECG74SS1 ECG74HC126
ECG74290
ECG74LS126
Dual 2-Wtde 2-2-3-2-lnput ECG74LS290
ECG74LS51 Ouad 2-lnput NANO
DualDecade
ECG7438
4-Wide 2-lnput ECG74HC390
ECG74LS38
ECG7454 ECG74LS390
Ouad 2-lnput NOR ECG74490
4-WKle 2-2-32-lnput ECG74LS490
ECG7433
ECG74H54
4-Bit Binary
4-Wtde 3-2-23-lnput
ECG74LS54 Buffers/Drivers
Hex lnverting
ECG7493A
ECG74CS3
ECG7406 ECG74LS93

Arithmetic & Logic Function

Devices
ECG7416
ECG80C96
ECG74LS293
Dual 4-Bit Binary
Adders Hex Non-lnverting ECG74393
1-Bit ECG7407 ECG74HC393
ECG7417 ECG74LS393
ECG7480
ECG8DC95 Divide-ByN
4-Bit ECG80CS7 ECG8520
ECG7483
Octal lnverting Divlde-By-12
ECG74LS83A
ECG74LS283 ECG74HC240 ECG7492
ECG74HCT240 ECG74LS92
Look-Ahead Carry-Generator ECG74LS240
ECG74182
True/Complement Zero/One Element
ECG74H87
ECG74LS540
Octal Non-lnverting
ECG74LS241
Counters, Synchronous
Decade
ECG74160
4-Bit Arithmetic Logic Unit/Function ECG74C244
ECG74LS160A
Generator ECG74HC244
ECG74162
ECG74HCT244
ECG74181 ECG74LS162A
ECG74LS244
ECG74LS181
ECG74LS541 4-Bit Binary
ECG74S181
ECG74161
4-Bit Magnitude Comparator
ECG7485
ECG74C85
Bus Drivers
Hex lnvertlng
ECG74C161
ECG74HC161
ECG74HCT161
ECG74LS85 ECG74366 ECG74LS161A
ECG74LS366A ECG74HC163
4 x 4 Register Files ECG74368 ECG74HCT163
ECG74170 ECG74LS368 ECG74LS163A
ECG74LS670 ECGBOC96 ECG8316
ECG8556
TTL Selector Guide (cont'd)
Counters, Up/Down
Decade
Decoders/Demultiplexers
Dual 2-Line-to-4-Line
Exclusive OR Gates with
Open Collector Output
ECG74LS168A ECG74HC139 Quad 2-lnput
ECG74LS190 ECG74LS139 ECG74136
ECG74C192 ECG74155 ECG74LS136
ECG74LS192 ECG74LS155
4-Bit Binary
ECG74LS169A
ECG74191
ECG8321
Dual 2-Line-to-4-Line (Open
Collectorl
Exclusive NOR Gates with
Open Conector Output
Quad 2-lnput
ECG74LS191 ECG74156
ECG74LS266
ECG74193 ECG74LS156
ECG74C193
ECG74LS193
4-line-to-16-Line
ECG74154 Expandable Gates
Dual 2-Wide Input AND/OR/lnvert
Counter/Latch 3-Line-to-8-Une ECG7450
Decade ECG74HC138 ECG74H50
ECG74HCT138 Dual 4-lnput NOR
ECG74176
ECG74LS138
ECG74196 ECG7423
ECG74S138
ECG74LS196
2-Wide 4-lnput AND/OR/lnvert
4-Bit Binary
ECG74177
ECG74LS197
Display Decoders/Drivers
BCD-to-Decimal - Orives Cold
ECG74H55
4-Wide 2-2-3-2-lnput AND/OR/lnvert
Cathode Tubes ECG74H52
ECG8554
ECG74141 ECG74H53

Data Selectors/Multiplexers
Dual 4-Line-to-1-Une
BCD-to-Decimal - Orives Gas
Filled Tubes
ECG7441
Expandable AND/OR/lnvert Gates
Dual 2-Wide 2-lnput
ECG74153
ECG74HC153 BCD-to-Decimal (Open Collector) ECG7450
ECG74LS153 ECG7445 ECG74H50
ECG74LS253 ECG74145 2-Wide 4-lnput
ECG74LS352 ECG74LS145 ECG74H55
ECG74LS353
BCD-to-7-Segment (Open Collectorl 4-Wide 2-2-3-2-lnput
ECG8309
ECG7447 ECG74H52
Quad 2-Line-to-1-line ECG74LS47 ECG74H53
ECG74157 ECG74LS49
ECG74C157
ECG74LS157
ECG74158
ECG74LS247
ECG74249
ECG74LS249
Expander Gates
Triple 3-lnput
ECG74LS158 BCD-to-7-Segment ECG74H61
ECG74HC257
ECG74LS257 ECG7448 4-Wide 2-3-3-2-lnput
ECG74LS258 ECG74C48 ECG74H62
ECG74S258 ECG74LS48
ECG8123
ECG8233
ECG74LS248
Flip-Flops, Master-Slave

Quad 2-Line-to-1-Line with Storage

ECG74LS298
Display Decoder/Drivers with
Input Latches
(M-S) Types
Dual J-K
ECG7473
Hexadecimal-to-7-Segment - ECG74H73
Quad 2-Line-to-1-Line (Open Orives Common Anode LEO
Collector) ECG74H76
ECG8374 ECG74H78
ECG8235
ECG8266
8-Line-to-1-Line
ECG74C151
Encoders
Keyboard Encoders
Gated J-K
ECG74H71
ECG7472
ECG74C922 ECG74H72
ECG74HC151 ECG74C923
ECG74LS151
ECG74251
ECG74LS251
8-Line-to-3-Line - Octal Priority
Encoder
ECG74LS148
Flip-Flops, J-K Edge
Triggered Types
ECG74S251 Dual J-K Negative Edge Triggered
16-Line-to-1-Line ECG74LS348 ECG74C76
ECG8318 ECG74C107
ECG8219
10-Line-to-4-line - Decimal to ECG74LS73

Decoder, 4-Line-to-10-Line
BCD-to-Decimal
BCD Priority Encoder
ECG74LS147
ECG74LS78
ECG74H106
ECG74LS107
ECG7442
ECG74C42
ECG74LS42
Exclusive OR Gates
Quad 2-lnput
ECG74H108
ECG74LS 112A
ECG74S112
ECG7486 ECG74LS113
ECG74H86 ECG74S113
ECG74HC86 ECG74LS114
ECG74LS86
ECG74LS386
TTL Selector Guide (cont'd)
Dual J-K Positive Edge Triggered
ECG74109
ECG74HC109
lnverters with Open Collector
Output
Retriggerable Monostable
ECG74122
Hex ECG74LS122
ECG74LS109A ECG74221
ECG7405
Gated J-K Positive Edge Triggered ECG74LS05 ECG74C221
ECG7470 ECG74S05 ECG74LS221
ECG7406 ECG9601
Gated J-K Negative Edge Triggered
ECG7416 Dual Retriggerable Monostable
ECG74H102
ECG74123

Flip-Flops, "D" Types

Dual
Latches
Octal "Dn
ECG74HC123
ECG74LS123

ECG7474
ECG74C74
ECG74H74
ECG74LS363
ECG74C373
ECG74HC373
NANO Gates
Quad 2-lnput
ECG74HC573 ECG7400
ECG74LS74A
ECG74HCT373 ECG74COO
ECG74S74
ECG74HCT573 ECG74HOO
Hex ECG74LS373 ECG74HCOO
ECG74174 ECG74HCTOO
ECG74C174 Quad S- R ECG74LS00
ECG74HC174 ECG74LS279 ECG74SOO
ECG74HCT174 Quad Latch ECG7437
ECG74LS174 ECG74LS37
ECG8314
ECG74S174 Triple 3-lnput
4-Bit Bistable
Octal ECG7410
ECG7475
ECG74HC273 ECG74C10
ECG74LS75
ECG74HCT273 ECG74H10
ECG74LS273 8-Bit Addressable ECG74HC10
ECG74C374 ECG74HC259 ECG74LS10
ECG74HC374 ECG74LS259 Dual 4-lnput
ECG74HC574
ECG7420
ECG74HCT374
ECG74LS374
ECG74HC377
Level Shifters (See Interface
Buffers)
ECG74C20
ECG74H20
ECG74LS20
Quad
ECG74175
ECG74C175
Line Drivers and Receivers
Dual 4-lnput NANO 50 Ohm
ECG7440
ECG74H40
ECG74S40
ECG74HC175
Line Driver
ECG74S140
Dual 5-lnput
ECG74LS175
ECG8092
ECG74LS379 Dual Differential Une Receiver
ECG8613 ECG9615
8-lnput
ECG74C30

Interface Gates, Hi-Voltage with

Open Collector Output
Octal lnverting Line Driver/Receiver
ECG74C240
ECG74HC240
ECG74H30
ECG74LS30
Hex lnverting ECG74HCT240
13-lnput
ECG7406 ECG74LS240 ECG74LS133
ECG7416 ECG74LS540 ECG74S133
Hex Non-lnverting
ECG7407
ECG7417
Octal Non-lnverting Line
Driver/Receiver
ECG74LS241
NANO Gates with Open
Collector Output
ECG74C244 Quad 2-lnput
Quad 2-lnput NANO
ECG74HC244 ECG74H01
ECG7426
ECG74HCT244 ECG74LS01
ECG74LS26
ECG74LS244 ECG74LS03
ECG74LS541 ECG74S03
Interface Buffers, Level Shifting
Hex Non-lnverting
Quad 2-lnput NOR 50 Ohm
Line Driver
ECG7426
ECG74LS26
ECG7438
ECG74C902 ECG74128
ECG74LS38

lnverters
Hex
Multiplexers/Demultiplexers
ECG74HC4053
Triple 3-lnput
ECG7412
ECG74LS12
ECG7404 ECG74HC4067
ECG74C04
Dual 4-lnput
ECG74H04
ECG74HC04
ECG74HCT04
Multivibrators, Monostable
(One Shots)
ECG7422
ECG74H22
ECG74LS22
Monostable ECG74S22
ECG74LS04
ECG74121
ECG74S04
Dual Retriggerable/Resettable
Monostable
ECG8853
ECG9602
TTL Selector Guide (cont'd)
NOR Gates
Quad 2-lnput
4-Bit Bidirectional Parallel
ECG7495
ECG74C95
ECG7402
ECG74C02 ECG74LS95B
ECG74HC02 5-Bit Serial-ln/Parallel-Out or
ECG74LS02 Parallel-ln/Serial-Out
ECG74S02 ECG7496
ECG7428
ECG74LS28 8-Bit Serial
ECG7491
Triple 3-lnput ECG74LS91
ECG7427
ECG74LS27 8-Bit Serial-in/Parallel-Out
ECG74164
Dual 4-lnput
ECG74C164
ECG7425 ECG74HC164
Dual 5-lnput ECG74LS164
ECG74LS260 8-Bit Parallel-ln/Serial-Out
Expandable Dual 4-lnput ECG74165
ECG7423 ECG74HC165
8-Bit Universal

NOR Gates with Open

Collector Output
ECG74199
8-Bit Bidirectional Universal
Quad 2-lnput ECG74198
ECG7433 ECG74HC299
ECG74LS299

OR Gates
Ouad 2-lnput
8-Bit Serial or Parallel-ln/
Parallel-Out
ECG7432 ECG74166
ECG74C32 ECG74LS166
ECG74HC32 Dual 8-Bit Serial
ECG74HCT32
ECG8328
ECG74LS32

Registers
Quad 1/0
Voltage Controlled
Oscillators (VCO)
Single
ECG8542
ECG74LS624
4-Bituou Dual
ECG74C173
ECG74S124
ECG74HC173
ECG74LS625
ECG74LS173
ECG74LS626
4-Bit x 16 Word FIFO ECG74LS627
ECG74HC40105 ECG74LS629

Schmitt Triggers
Dual 4-lnput NANO
ECG7413
ECG74LS13
Hex lnverter
ECG7414
ECG74C14
ECG74HC14
ECG74HCT14
ECG74LS14
Ouad 2-lnput NANO
ECG74132
ECG74HC132
ECG74LS132

Shift Registers
4-Bit Parallel
ECG74195
ECG74LS195A
4-Bit Universal
ECG74LS395A
4-Bit Bidirectional Universal
ECG74LS194A
ECG74S194
ECG74LS295A
TTL Logic Diagrams (Vcc = +5 V Nom.)
Diag. 1 14-Pin DIP See Fig. 06 Diag. 2 14-Pin DIP See Fig. 06 Diag. 3 14-Pin DIP See Fig. 06
ECG7400, ECG74COO, ECG74HOO, (See Also Diag. 3) (See Also Oiag. 2)
ECG74HCOO, ECG74HCTOO, ECG7401,ECG74LS01 ECG74H01
ECG74LS00,ECG74SOO

1Y 1A 18 2Y 2A 28 GND 1A 1B 1Y 2A 28 2Y GND

Ouad 2-lnput NANO Gate w ith Open

Collector Output Quad 2-lnput NANO Gate with Open
Quad 2-lnput NANO Gate * DISCONTINUEO Collector Output

Diag. 4 14-Pin DIP See Fig. D6 Diag. 5 14-Pin DIP See Fig. 06 Diag. 6 14-Pin DIP See Fig. 06
ECG7402,ECG74C02,ECG74HC02, ECG74LS03,ECG74S03 ECG7404,ECG74C04,ECG74H04,
ECG74LS02,ECG74S02 ECG74HC04, ECG74HCT04,
ECG74LS04,ECG74S04
4A 4Y 38 3A 3Y Vcc 6A 6Y 5A 5Y 4Y

1Y 1A 18 2Y 2A 28 GND 1A 18 1Y 2A 28 2Y GND 1A 1Y 2A 2Y 3A 3Y GND

Quad 2-lnput NOR Gate Quad 2-lnput NANO Gate with Open Hex lnverter
Collector Output
Diag. 7 14-Pin DIP See Fig. D6 Diag. 8 14-Pin DIP See Fig. 06 Diag. 9 14-Pin DIP See Fig. 06
ECG7405, ECG74H05, ECG74LS05, ECG7406 ECG7407
ECG74S05
6Y 5A 5Y 4A Vcc 6A BY 5A 5Y 4A 4Y 6A 6Y 5A 5Y 4A 4Y

1A 1Y 2A 2Y 3A 3Y 1A 1Y 2A 2Y 3A 3Y GND

Hex lnverter/Buffer with Hi-Volt (30 V) Open Hex Buffer with Hi-Volt (30 V) Open
Hex lnverter with Open Collector Output Collector Output Collector Output

Diag. 10 14-Pin DIP See Fig. 06 Diag. 11 14-Pin DIP See Fig. 06 Diag. 12 14-Pin DIP See Fig. D6
ECG7408, ECG74C08, ECG74H08*, ECG7409,ECG74LS09,ECG74S09 ECG7410,ECG74C10,ECG74H10,
ECG74HC08, ECG74HCT08, ECG74HC10,ECG74LS10,ECG74S10
ECG74LS08,ECG74S08

1A 18 1Y 2A 28 2Y GND
Quad 2-lnput ANO Gate with Open Collector
Quad 2-lnput AND Gate Output
* DISCONTINUED * DISCONTINUED Triple 3-lnput NANO Gate
Vcc 1C 1Y 3C 3B 3A 3Y Vcc 1C 1Y 3C 3B 3A 3Y
Vcc 2D 2C NC 2B 2A 2Y
14 13 12 11 10 9 8 14 13 12 11 10 9 8
14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7
1 2 3 4 5 6 7
1A 1B 2A 2B 2C 2Y GND 1A 1B 2A 2B 2C 2Y GND
1A 1B NC 1C 1D 1Y GND

Vcc 6A 6Y 5A 5Y 4A 4Y Vcc 1C 1Y 3C 3B 3A 3Y Vcc 6A 6Y 5A 5Y 4A 4Y

14 13 12 11 10 9 8 14 13 12 11 10 9 8 13 10 9 8
14 12 11

1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7
1A 1Y 2A 2Y 3A 3Y GND 1A 1B 2A 2B 2C 2Y GND 1A 1Y 2A 2Y 3A 3Y GND

Vcc 6A 6Y 5A 5Y 4A 4Y Vcc 2D 2C NC 2B 2A 2Y Vcc 2D 2C NC 2B 2A 2Y

14 13 12 11 10 9 8 14 13 12 11 10 9 8 14 13 12 11 10 9 8

1 2 3 4 5 6 7 3 5 6 7
1 2 4 1 2 3 4 5 6 7
1A 1Y 2A 2Y 3A 3Y GND 1A 1B NC 1C 1D 1Y GND 1A 1B NC 1C 1D 1Y GND

STROBE STROBE
Vcc 2D 2C NC 2B 2A 2Y Vcc 1X 2D 2C 2G 2B 2A 2Y Vcc 2D 2C 2G 2B 2A 2Y
14 13 12 11 10 9 8 16 15 14 13 12 11 10 9 14 13 12 11 10 9 8

1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7
1A 1B NC 1C 1D 1Y GND 1X 1A 1B STROBE 1C 1D 1Y GND 1A 1B STROBE 1C 1D 1Y GND
1G 1G
Vcc NC H G NC NC Y
Vcc 4B 4A 4Y 3B 3A 3Y
14 13 12 11 10 9 8
14 13 12 11 10 9 8

1 2 3 4 5 6 7
1 2 3 4 5 6 7
A B C D E F GND
1A 1B 1Y 2A 2B 2Y GND
 OUTPUTS
OUTPUTS
Vcc f g a b c d e
Vcc f g a b c d e
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9

f g a b c d e
f g a b c d e

BI /
B C LT RBO RBI D A BI /
B C LT RBO RBI D A

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
B C LAMP RB RB D A GND B C LAMP RB RB D A GND
TEST OUT IN TEST OUT IN
INPUTS PUT PUT INPUTS INPUTS PUT PUT INPUTS
TTL Logic Diagrams (cont'd)
Oiag. 50 14-Pin OIP See Fig. 06 Oiag. 51 14-Pin OIP See Fig. 06 Diag. 52 14-Pin OIP .See Fig. D6
(See also Oiag. 51 'ancl 52) (See also Oiag. 50 and 52) (See also Diag. 50 and 51)
ECG7464 ECG74H54 ECG74LS54

A C 0 F NC GNO e o G GND ,. e e o Y GloO

4-Wide 2-lnput ANO/OR/lnvert Gate 4-Wde 2-2,2-3 Input ANO/OR/lnvert Gate 4-Wide 3-2-2-3 Input ANO/OR/lrivert Gate

Diag. 53 14-Pin OIP See Fig. 06 Oiag. 54 14-Pin DIP See Fig. D6 Oiag. 55 14-Pin DIP See Fig. 06
(See also Diag. 54) (See siso Oag. 53) ECG7460
ECG74H55 ECG74LS5&

1A 18 1C 2A 28 2C GN0

Expandable 2-Wide 4-lnput ANO/OR/

tnvert Gate 2-Wide 4-lnput ANO/OR/lnvert Gate Dual 4-lnput Expander

Diag. 56 14-Pin.OIP See Fig. D6 Diag. 57 14-Pin OIP See Fig. D6 Diag. 60 14-Pin OIP See Fig. 06
ECG74H81 ECG74H62 ECG7470

NC CL A J1 J2 GND

Gated J.K Positiva Edge Triggered Ftip-Flop

Triple 3-lnput Expander 4-Wide 3-2-2-3 Input ANO/OR Expender with Preset and Cler

Diag. 61 14-Pin OIP See Fig. 06 Diag. 62 14-Pin DIP See Fg. D6 Diag. 63 14-Pin DIP See Fig. 06
ECG74H71 ECG7472,ECG74H72 (See also Diag. 64)
ECG7473,ECG74H73
20

JlA J18 J2A J2B PR O CNO

1 CK 1 UC Vcc
CLA

Gated J-K M/S Flip-Flop w ith Preset and

Gated J-K M/S Flip-Flop with Preset Clear Dual J-K M/S Flip-Flop with Clear
Tn Logic Diagrams (cont'd)
Diag. 64 14-Pin DIP See Fig. 06 Diag. 65 14-Pin DIP See Fig. 06 Diag. 66 16-Pin DIP See Fig. 08
(See also Diag. 63) ECG7474, ECG74C74, ECG74H74, ECG7475,ECG74LS75
ECG74C73, ECG74LS73 ECG74LS74A, ECG74S74

1 1k Vcc 2 CK 2 2J 1 10 1CK
ClR CLI' ClR

Dual J-K Negativa Edge Triggered Flip-Flop 4-Bit Bistable Latch with Complementary
with Clear Dual "O" Flip-Flop with Preset and Clear Output

Oiag. 67 16-Pin DIP See Fig. 08 Oiag. 68 16-Pin OIP See Fig. 08 Diag. 69 14-Pin DIP See Fig. 06
(See also Diag. 68) (See afso Diag. 67) ECG74LS77
ECG74H76 ECG74C76,ECG74LS7&A

1CI( 1PR 1 1J Vcc 2CI( 2PA 2

1 Vcc 2CK 2PR 2 o
ClR
1J
CLR CLR CLR
10 2D
,..
( ,-A.BLE VCC lO NC

Dual J-K M/S Flip-Flop with Preset and Dual J-K Negative Edge Triggered Flip-Ffop
with Preset and Clear
Clear 4-Bit Bistable Latch
* DISCONTINUED
Diag. 70 14-Pin DIP See Fig. 06 Diag. 71 14-Pin OIP See Fig. D6 Diag. 72 14-Pin DIP See Fig. D6
(See afso Diag. 71) (See also Diag. 70) ECG7480
ECG74H78 ECG74LS78

B
"'

lK 10 1J 20 GNO CK 1 PR 1J Vcc CLR 2PR 2K

Dual J-K M/S Flip-Flop with Presets and a Dual J-K Negative Edge Triggered Flip-Flop
Common Clock and Clear with Preset and a Common Clock and Clear Gated Full Adder with Complementary Sum
Outputs

Diag. 74 14-Pin DIP See Fig. 06 Oiag. 75 16-Pin OIP See Fig. 08 Oiag. 76 16-Pin DIP See Fig. D8
ECG7482 ECG7483,ECG74LS83A ECG7485,ECG74LS85
A2 82 O GNO C2 OATA tNPUTS
a <' C. ca GNO 81 A1 [1 A .

H ca B1 Al

e n
B3 80
A A2
A 8 A >< 8 A B A B A e: 8 A 8
I 3 AJ 83 12 82 IN IN IN OUT OUT OUT

vcc co NC NC
A I 3 AJ 83 VCC l 2 82 A2 o .rrA ~ \ A ) B A:BA<81 GNO
INPUT CASCADINC INPUTS OUTPUTS

2-Bit Binary Full Adder 4-Bit Full Adder 4-Bit Magnitude Comparator
TTL Logic Diagrams (cont'd)
Diag. 77 16-Pin DIP See Fig. D8 Diag. 78 14-Pin DIP See Fig. D6 Diag. 79 14-Pin DIP See Fig. D6
ECG74C85 ECG7486, ECG74H86, ECG74HC86, ECG74H87
IHPUTS OUTPUTS ECG74LS86, ECG74SS6
,..._.A-,.,___,.__
Al a3 A> B A< I

e 8

IA 18 IV 2A 28 2V GND
e Al Y1 NC A2 Y2 GND
Quad Exclusive OR Gate
4-Bit Magnitude Cornparator * DISCONTINUED 4-Bit True/Cornplernent Zero/One Elernent

Diag. 80 16-Pin DIP See Fig. D8 Diag. 81 14-Pin OIP See Fig. 06 Oiag. 82 14-Pin DIP See Fig. 06
ECG7489 ECG7490,ECG74C90, ECG74LS90 ECG7491,ECG74LS91
HI.ICT INP\ITS DATA SlNII OATA IINII

~
f.......,T OUTl'VT IW\IT OUT,vf INl"UT ttv,uT

' ' a CNO ClOCK NC

.. .. CK

$l

NC NC NC vcc NC

Decade Counter 8-Bit Serial Shift Register

64-Bit RAM (16 x 4)

Oiag. 83 14-Pin OIP See Fig. D6 Diag. 84 14-Pin DIP See Fig. 06 Oiag. 85 14-Pin DIP See Fig. D6
ECG7492,ECG74LS92 ECG7493A, EC.G74LS93 ECG74C93,ECG74l93

'""''
A NC

...,,

,_,, NC YCC NC lliK:

4-Bit Binary Counter
Divide-by-12 Counter 4-Bit Binary Counter * OISCONTINUEO

Diag. 86 16-Pin DIP See Fig. D8 Diag, 87 14-Pin DIP See Fig. D6 Oiag. 88 14-Pin OIP See Fig. 06
ECG7494 (See also Diag. 88) (See also Oiag. 87)
ECG7495, ECG74LS95B ECG74C95
OUTNJTS ClOClt 2
~ C l C X : l t \ L-$tt!Fl
Vcc CA 0e CJc Oc, RSHlfT tLO&O,

Ck.1 CIU

$f.JIIAL INPVT

P1A P1B P1C Pt D Vcc PE1 SER. CLOC K ~ ~ MOOE CiNO

IN - - - - - V - - - CONT~OL
INl"UfS

4-Bit Scr:al or Parallel Shift.Register 4-Bit Bidirectional dr Parallel Shift Register 4-Bit Bidirectional Parallel Shift Register
TTL Logic Diagrams (cont'd)
Diag. 89 16-Pin DIP See Fig. D8 Diag. 90 16-Pin DIP See Fig. D8 Diag. 92 14- Pin DIP See Fig. 06
ECG7496 ECG7497 ECG74H102

""''"" , .......1.(
cu CAICJl,Oa 1Nt'Vf '111091 C:lOC:C

CLOCK ~ Vcc o ( ll'AUH

'--v--' fNA81..l
"-Afl~TS
PRUET

5-Bit Serial-ln/Parallel-Out or Parallel-ln/ Gated J-K NegativeEdg triggered FlipFlop

Serial-Out Shift Register Synchronous 6-Bit Binary Rate Multiplier with Preset and Clear

Diag. 93 14-Pin DIP See Fig. D6 Diag. 94 16-Pin DIP See Fig. D8 Diag. 95 14-Pin DIP See Fig. 06
ECG74H103 ECG74H106 (See also Diag. 96}
ECG74107
2J

1 Ct(. 1 PR 1 U Vcc 2 CK 2 PR 2
CLA CLR

Dual J-K Negativa Edge Triggered Flip-Flop Dual J-K Negativa Edge Triggered Flip-Flop
with Clear with Clear Dual J-K MIS Flip-Flop -with Clear

Diag. 96 14-Pin DIP See Fig. D6 Diag. 97 14-Pin DIP See Fig. 06 Diag. 98 16-Pin DIP See Fig. 08
(See also Diag. 95) ECG74H108 ECG74109, ECG74HC109,- ECG74LS109A
ECG74C107,ECG74LS107

1 1J 11( 1 CK 1 PR 10 10 GNO
CLR

Dual J-K Negativa Edge Triggered Flip-Flop Dual J-K Negativa Edge Triggered Flip-Flop Dual J-K Positiva Edge Triggered Flip-Flop
with Clear with Clear with Preset and Clear

Diag. 99 14-Pin DIP See Fig. D6 Diag. 101 16-Pin DIP See Fig. D8 Diag. 102 14-Pin DIP See Fig. 06
ECG74110 ECG74LS112A, ECG74S112 ECG74LS113,ECG74S113

Gated J-K M/S Flip-Flop with Preset and Dual J-K Negativa Edge Triggered Flip-Flop Dual J-K Negativa Edge Triggered Flip-Flop
Clear with Preset and Clear with Preset
Tn Logic Diagrams (cont'd)
Diag. 103 14-Pin DIP See Fig. 06 Diag. 104 14-Pin DIP See Fig. 06 Diag. 105 14-Pin DIP See Fig. 06
ECG74LS114,ECG74S114 ECG74121 ECG74122, ECG74LS122

Al A2 81 IIZ CLII GNO

Dual J-K Negativa Edge Triggered Flip-Flop Retriggerable Monostable Multivibrator with
with Presets and a Common Clock and Clear Monostable Multivibrator Clear

Oiag. 106 16-Pin OIP See Fig. 08 Oiag. 107 16-Pin DIP See Fig. 08 Oiag. 108 14-Pin OIP See Fig. D6
ECG74123, ECG74HC123,ECG74LS123 ECG74S124 ECG74125,ECG74HC125,ECG74LS125A

IA 18 1 1C IA IV 2C 2A 2Y G"D
CLII

Dual Retriggerable Monostable Quad Bus Buffer with 3-State Output (Active
Multivibrator with Clear Dual Voltage Controlled Oscillator Low)

Diag. 109 14-Pin DIP See Fig. 06 Diag. 110 14-Pin DIP See Fig. 06 Diag. 111 14-Pin DIP See Fig. 06
ECG74126,ECG74HC126,ECG74LS126 ECG74128 ECG74132,ECG74HC132,ECG74LS132

1C 1A 1V 2C 2A 2V GNO 1V 1A 18 2V 2A 28 GND

Ouad Bus Buffer with 3-State Output (Active

High) Ouad 2-lnput NOR 50 Ohm Line Driver Quad 2-lnput NANO Schmitt Trigger

Oiag. 112 16-Pin DIP See Fig. 08 Diag. 114 14-Pin DIP See Fig. 06 Diag. 115 16-Pin OIP See Fig. 08
ECG74LS133,ECG74S133 ECG74136,ECG74LS136 ECG74HC138, ECG74HCT138,
ECG74LS138,ECG74S138
.. H y
Vcc 48 4A 4Y 311 3A 3Y
DATA OUTPUU
,------/\-----~

A Y6

A B C O G G"O

1A 18 IV 2A 28 2Y GNO ~ ~oui!u,GND
S EL ECT ENABU
Quad Exclusive OR Gate w ith Open
13-lnput NANO Gate Collector Output 3-Line-to-8-Line Oecoder/Dernultiplexer
TTL Logic Diagrams (cont'd)
Diag. 116 16-Pin DIP See Fig. 08 Diag. 117 14-Pin DIP See Fig. 06 Diag. 118 16-Pin DIP See Fig. 08
ECG74HC139,ECG74LS139 ECG74S140 ECG74141
OUTPUTS OUffUTS

1A 11 NC 1C 10 IV GNO
..!..._!.., ~ Ycc ~ 2
OU1l'IJT$ INPUT$ INl'UTS OUll'IJT

BCD-to-Decimal Decoder,Driver for Cold

Dual 2-Line-to-4-Line Decoder/Demultiplexer Dual 4-lnput NANO 50 Ohm Une Driver Cathode Tubas

Diag. 119 16-Pin DIP See Fig. D8 Diag. 122 16-Pin DIP See Fig. D8 Diag. 123 16-Pin DIP See Fig. DS
ECG74142 ECG74145,ECG74LS145 ECG74LS147

'---------.v,--------'
DRIVER OUTPUTS
OUTPUTS

BCD-to-Decimal Decoder Driver with Open

BCD Counter/4-Bit Latch/BCD Decoder/Driver Collector Output

Diag. 124 16-Pin DIP See Fig. D8 Diag. 125 24-Pin DIP See Fig. D15 Diag. 126 16-Pin DIP See Fig. 08
ECG74LS148 ECG74150 ECG74151, ECG74C151, ECG74HC151,
OUTPUTS INPUTS ECG74LS151
~ ~ OU~~UT

GS 3

AO 03

8-Line-to-1 -Line Data Selector/Multiplexer

8-Line-to-3-Line Octal Priority Encoder 16-Line-to-1-U ne Data Selector/Multiplexer with Strobe * DISCONTINUED
Diag. 128 16-Pin DIP See Fig. D8 Diag. 129 24-Pin DIP See Fig. D15 Diag. 130 16-Pin DIP See Fig. D8
ECG74153, ECG74HC153, ECG74154,ECG74C154,ECG74HC154 ECG74155,ECG74LS155
ECG74LS153 INPUTS
DATA INPUTS

' - - - - - - - - - .vr--- - -- - -'

OUTPUTS
OATl\, INPUTS
4-Line-to-16-line Decoder/Demu lt iplexer
Dual 4-line-to-1-Line Data Selector/
Multiplexer * DISCONTINUED Dual 1-line-to-4-Line Decoder/Oemultiplexer
TTL Logic Diagrams (cont'd)
Oiag. 131 16-Pin OIP See Fig. 08 Oiag. 132 16-Pin DIP See Fig. 08 Oiag. 133 16-Pin DIP See Fig. 08
ECG74156,ECG74LS156 ECG74157, ECG74C157, ECG72LS157, ECG74158,ECG72LS158
INPUTS OUTPUT INPUTS OUTPUT INPUTt OUTPUT INPUT$ OUTPUT
,--1'-, ~ ,--1'-, ,.........A--..
.tA 48 v 3A 38 3Y Vcc STROIE 4A 48 4V 3A 38 JV

JV JV

SELEC T ~ IV ~ 2V GNO
SElEc;T ~ IV ~ 2V GND
INPUTS OUTPUT INPUTS OUTPUT
INPUT$ OUTPUT INPUTS OUTPUT
Dual 1-Line-to-4-Line Decoder/Dernultiplexer Ouad 2-Line-to-1-Line Data Selector/Multiplexer Quad 2-line-to-1-line Data Selector/Multiplexar
with Open Collector Output with Non-lnverting Output with lnverting Output

Diag. 134 16-Pin DIP See Fig. 08 Diag. 135 16-Pin DIP See Fig. D8 Diag. 136 16-Pin DIP See Fig. 08
ECG74160,ECG74LS160A ECG74161,ECG74C161,ECG74HC161, ECG74162,ECG74LS162A
OUTPUTS ECG74HCT161,ECG74LS161A
OUTPUTS

ClUR l040 ClUA l040

CLUR ClOCk 4
~
8 C
04T4 INPUTS
.
O EN48lE GND
ClUR ClOCK ~ E N ~ B l E GNO
DATA INPUT$

Presettable Synchronous Oecade Counter Presettable Synchronous 4-Bit Binary Presettable Synchronous Decade Counter
with Oirect Clear Counter with Oirect Clear with Synchronous Clear

Diag. 137 16-Pin DIP See Fig. 08 Oiag. 138 14-Pin OIP See Fig. 06 Diag. 139 16-Pin DIP See Fig. 08
ECG74183, ECG74HC183, ECG74164, ECG74C164, ECG74HC164, ECG74165,ECG74HC165,ECG74LS165
ECG74HCT163,ECG74LS163A ECG74LS164
OUTPUTS CLOCK P4R4lLEl 1...UTS SE1114LOUTPUT
OUTPUTS
Vcc INHIBIT ~ INPUT 0H
Vcc ~ClUAClOCK

13 12

. .IFTI
L 040
A CK

ClOCK ~ E N A , B L E GNO
OAT A IM'UTS
Presettable Synchronous 4-Bit Binary
Counter with Synchronous Clear 8-Bit Parallel-ln/Serial-Out Shift Register
* DISCONTINUED 8-Bit Serial-ln/Parallel-Out Shift Register * OISCONTINUED
Diag. 140 16-Pin DIP See Fig. 08 Diag. 141 16-Pin DIP See Fig. D8 Diag. 142 16-Pin DIP See Fig. D8
ECG74166,ECG74LS166 ECG74LS168A ECG74LS169A
,ARALLfL PAAALLEL INPUT$
SHIF\' INP\JT OUTll'UT ,__...,.,._"'
Vcc LOAO H "4 G

13

SERIAL
IN,uT Cl EAR

SERIAL A 8 C O ClOCK CLOCK GNO

INl'UT _ _ , , , _ . . INHIBIT
PARALLEL INPUTS
DATA INPUTS DATA INl'UTS

8-Bit Serial or Parallel-ln/Serial-Out Shift Presettable Synchronous Oecade Up/Oown Presettable Synchronous 4-Bit Binary
Register Counter Up/Oown Counter
TTL l!ogic Diagrams (cont'd)
Diag. 143 16-Pin DIP See Fig. D8 Oiag. 144 16-Pin OIP See Fig. 08 Oiag. 145 16-Pin OIP See Fig. 08
ECG74170,ECG74LS170 ECG74173*, ECG74C173, ECG74HC173, ECG74174, ECG74C174, ECG74HC174,
ECG74LS173 DATA ENA8LE
ECG74HCT174, ECG74LS174,
DATA INPUTS INPUTS ECG74S174
ClEAR ~ ~

02 02

~ ~ CLOCK GND
OUTPUT CONTROL OUTPUTS
CU AR YO 10 20 20 JD )Q GNO
4-Bit "O" Register with 3-State Output
4 x 4 Register File with Open Collector Output * OISCONTINUEO Hex "O" Flip-Flop with Clear

Oiag. 146 16-Pin OIP See Fig. 08 Oiag. 147 14-Pin OIP See Fig. 06 Oiag. 148 14-Pin OIP See Fig. 06
ECG74175,ECG74C175,ECG74HC175, ECG74176 ECG74177
ECG74LS175,ECG74S175*

CLEAR 0D D B Oe

COUNT/
LOAD
,
CLOCK COUNT/
LOAD
CLOCK
1
CLOCK CLOCK
2 2

Quad "D" Flip-Flop with Complementary ~8~TI C1c ~A~A tN~T~ 0A CLC::K GND rn~~T/ Oc ~ 0A CL'::K GND
Outputs DATAINPUTS

* DISCONTINUED Presettable Decade Counter/Latch Presettable 4-Bit Binary Counter/latch

Diag. 150 16-Pin DIP See Fig. D8 Oiag. 151 14-Pin OIP See Fig. 06 Diag. 152 24-Pin DIP See Fig. 015
ECG74179 ECG74180 ECG74181,ECG74LS181,ECG74S181
!NPUTS

G A

EVEN 000
H INPU T INPUT

..!...__ ~ SERIAL 0A CLOCK GND

~ IN OUTPUT OUTPUT ~ ____"____J EVEN 000 I EVEN 1 000 GND
- y - I N PUT INPUT OUTPUT OUTPUT Arithmetic Logic Unit (ALU)/Function
INPUTS
4-Bit Parallel Shift Register with Generator
Complementary Final Stage 9-Bit Odd/Even Parity Generator/Checker * OISCONTINUEO
Diag. 153 16-Pin OIP See Fig. D8 Diag. 154 14-Pin DIP See Fig. D6 Oiag. 155 16-Pin DIP See Fig. 08
ECG74182 ECG74H183
I..PUTS OUTPUT OUTPUT
ECG74LS190
DATA
tN,UTS

A
OUT.,.,fS

,.........,_..,..........,...
fU"'U: MAX /
CLOCK CL.OCK WN
-------
LOAD
IN,UTS

DATA
C
DATA
D

Ck
ClOCI< MIN

GI

PI GO PO CJ PJ

DATA Oe OA ENA8ll DOWN/

8 G Uf'
' - , - ' ' - . , - J .,_,,__., .__,,.._..,
INPUT OUTPUTS INPUTS OUTPUTS

Presettable Synchronous Oecade Up/Oown

Look-Ahead Carry Generator Dual Carry/Save Adder Counter
TTL Logic Diagrams (cont'd)
Diag. 156 16-Pin DIP See Fig. DS Diag. 157 16-Pin DIP See Fig. D8 Diag. 158 16-Pin DIP See Fig. DS
ECG74191,ECG74LS191 ECG74192*,ECG74C192,ECG74LS192 ECG74193,ECG74C193,ECG74hS193

Vcc
,........--..~-----.
OAlA
A
tNPVtS

a.oca C\OCK
OOT~TJ

9'tH\.E MAX/
MJN LOAD
*"Ull

CATA
e
DATA
o

Presettable Synchronous Decade Up/Down

Presettable Synchronous 4-Bit Binary
Counter with Dual Clocks Presettable Synchronous 4-Bit Binary
Up/Down Counter * DISCONTINUED * DISCONTINUED Up/Down Counter with Dual Clocks

Diag. 159 16-Pin DIP See Fig. DS Diag. 160 16-Pin DIP See Fig. D8 Diag. 161 14-Pin DIP See Fig. D6
ECG74LS194A, ECG74S194 ECG74195,ECG74LS195A ECG74196,ECG74LS196
vcc OA Os CLOCK $1 SO '"''"'

CLEAR so
COUOIT I
lOAO ,
ClOCK

CLOCII
1

J A I C O GNO
'--y--J ' - - - - y - - - - /
PARA&.LEL INPUT$ SERIAL INPUT$ 1"AftAllt:l tWUTS ~~~T Qc ~ 0A CL~II GOIO
DATA IM'\JTS
4-Bit Patallel Shift Register with
4-Bit Bidirectional Parallel Shift Register Complementary Final Stage Presettable Decade Counter/Latch

Diag. 162 14-Pin DIP See Fig. D6 Diag. 163 24-Pin DIP See Fig. D15 Diag. 164 24-Pin DIP See Fig. D15
ECG74117*,ECG74LS117 ECG74198 ECG74199
DATA - T I SHlf T/ .....,,
"'ce lOAO M

CCIU'ITI CLOCII
LOAO 1

~~~T' Oc ~ 0A CL~II GOIO Sl111Al Millll'UT$

DATA tl\lPVTS
8-Bit Serial or Parallel-ln/Parallel-Out Shift
Presettable 4-Bit Binary Counter/Latch Register
8-Bit Bidirectional Parallel Shift Register
* DISCONTINUED
Diag. 165 16-Pin DIP See Fig. DB Diag. 166 20-Pin DIP See Fig. D12 Diag. 167 20-Pin DIP See Fig. 012
ECG74221,ECG74C221,ECG74LS221 ECG74C240, ECG74HC240, ECG74LS241
ECG74HCT240*, ECG74LS240
vcc
1R. .1
c, c,
t .
10 20 CLR
2
28 ,.

,. 18 1 10 GNO
CLR
Octal Buffer/Une Driver/Une Receiver with
lnverting 3-State Output Octal Buffer/Une Driver/Une Receiver with
Dual Monostable Multivibrator * DISCONTINUED Non-lnverting 3-State Output
TTL Logic Dia rams (cont'd)
Diag. 168 14-Pin DIP See Fig. 06 Diag. 169 14-Pin DIP See Fig. 06 Diag. 170 20-Pin DIP See Fig. 012
ECG74LS242 ECG74LS243 ECG74C244,ECG74HC244,
vcc oaa. Ne ,. 21 ll
EC'G74HCT244,ECG74LS244
,i ,.. , ... , , .., l 'I' )

GAi NC ,.. ,. ZA 3A U. GND

Quad Bus Transceiver with lnverting 3-State Quad Bus Transceiver with Non-lnverting Octal Buffer/Une Driver/Line Receiver with
Output 3-State Output Non-lnverting 3-State Output

Diag. 171 20-Pin DIP See Fig. 012 Diag. 172 16-Pin DIP See Fig. 08 Diag. 173 16-Pin OIP See Fig. 08
ECG74LS245 ECG14LS247 ECG74LS248

nn ou, ..,, ~
""'"'
Octal Bus Transceiver with Non-lnverting BCD-to7-Segment Oecoder/Driver with
3-State Output Hi-Volt (15 V) Open Collector Output BCO-to7-Segment Decoder/Oriver

Diag. 174 16-Pin DIP See Fig. 08 Oiag. 175 16-Pin OIP See Fig. 08 Oiag, 176 16-Pin DIP See Fig. 08
ECG74249,ECG74LS249 ECG74251,ECG74LS251,ECG74S251 ECG74LS253
DATAN'UTS
,------_,A,__ _.,...,

BCD-to-7-Segment Decoder/Driver with

Open Collector Output 8-Line-to-1-Line Data Selector/Multiplexer Dual-4 Line-to-1-Line Data Selector/
with Complementary 3-State Output Multiplexer with 3-State Output

Diag. 177 16-Pin DIP See Fig. 08 Diag. 178 16-Pin DIP See Fig. 08 Diag, 179 16-Pin DIP See Fig. 08
ECG74HC257,ECG74LS257 ECG74LS258,ECG74S268 ECG74HC259, ECG74LS259
INPUTS INPUTS
OUTPUT ,--,1'o---, OUTPUT ~ OUTPUT
vccCONTROl 4A 48 4Y JA l8 lV

lY

SELECT ,.!!....,..!!, IV ~ 2V GNO

INPUTS OUTPUT INNJTS OUTPUT

Ouad 2-Line-to-1-Line Data Selector/ Ouad 2-Line-to-1-Line Data Selector/

Multiplexar with 3-State Output Multiplexar with lnverting 3-State Output 8-Bit Addressable Latch
TTL Logic Diagrams (cont'd}
Oiag. 180 14-Pin DIP See Fig. 06 Oiag. 181 14-Pin OIP See Fig. D6 Diag. 182 20-Pin DIP See Fig. D12
ECG74LS260 ECG74LS266 ECG74HC273. ECG74HCT273,
ECG74LS273

Ouad Exclusive NOR Gate with Open

Dal 5-lnput NOR Gata Collector Output Octal "D" Flip-Flop with Clear

Diag. 183 16-Pin DIP See Fig. 08 Diag. 184 14-Pin D!P : , Fig. D6 Diag. 185 16-Pin DIP See Fig. D8
ECG74LS279 ECG74LS280 ECG74LS283

G
u
"'

,l
tWUT (Ylfrll 000

-"' ~
0Ul'V1'

Quad S-R Latch 9-Bit Odd/Even Parity Generator/Checker

4-Bit Full Adder

Diag. 186 14-Pin OIP See Fig. 06 Diag. 187 14-Pin OIP See Fig. 06 Diag. 188 14-Pin OIP Sea Fig. D6
ECG74290,ECG74LS290 ECG74LS293 ECG74LS295A
OUT>VTI

4-Bit Bidirectional Parallel Shift Register

Decade Counter with 3-State Output

Oiag. 189 16-Pin OIP See Fig. 08 Oiag. 190 20-Pin OIP Sea Fig. 012 Oiag. 191 16-Pin OIP See Fig. 08
ECG74LS298 ECG74HC299,ECG74LS299 ECG74LS348

11cc
~
OUTPUTS

0... Qe Qc
M>AD JW\JT
0o CLOCltSELECT CI
DATA
.._ -....... OUTP\ITS
~ ~ ~UT
),.,UTS

15 14 13

CI "

~-- MIi Cl'Qrc

......,,
coa.r-.s
OAJAINPUTS
8-Bit Bidirectional Shift/Storage Register 8-Line-to-3-Line Priority Encoder with
Quad 2-lnput Multiplexar w ith Storage with 3-State Output 3-State Output
TTL Logic Diagrams (cont'd)
Diag. 192 16-Pin DIP See Fig. DB Diag. 193 16-Pin DIP See Fig. DB Diag. 194 20-Pin DIP See Fig. D12
ECG74LS352 ECG74LS353 ECG74LS363
DATA INPUTS
DATA 1....VTS
r---~A..__ _""'I INMLI'
m tD JDJO IQe tDIO o

OVTPU't 10 10 a, 1G JO .O .a ONO
CC.TIIOL
=;;_=:..,v,;=_;;;=
OATAlNfl'VTS
DATA INPVTS

Dual 4-Line-to-1-Line Data Selector/ Dual 4-Line-to-1 -Line Data Selector/ Octal "D" Transparent Latch w ith 3-State
Multiplexer with 3-State Output Multiplexer w ith lnverting 3-State Output Output

Diag. 195 20-Pin DIP See Fig. D12 Diag. 196 16-Pin DIP See Fig. DS Diag. 197 16-Pin DIP See Fig. DB
ECG74LS364 ECG74365,ECG74LS365A ECG74366,ECG74LS386A
vcc IA IV 5A 5Y 4A 4Y
ce ' ., tO to Cloc:

""" ....
OUT'f'UT IQ tO JO JO JO JO t0 .c:a GJtD

G1 1A 1V 2A 2Y l.A 3V GNO ~1 1A 1Y 2A l'J 3A ]Y GNO

Hex Bus Driver with Non-lnverting 3-State Hex Bus Driver with lnverting 3-State
Octal "D" Flip-Flop with 3-State Output Output (Common Enable) Output (Common Enable)

Diag. 198 16-Pin DIP See Fig. DB Diag. 199 16-Pin DIP See Fig. DB Diag. 200 20-Pin DIP See Fig. D12
ECG74367,ECG74LS367 ECG74368,ECG74LS368 ECG74C373,ECG74HC373,
ECG74HCT373, ECG74HC573,
ECG74HCT573,ECG74LS373
lfllMU
\/cclO e, 1'0 10 to., ID 10 G

1Ai 1V 2A 2Y ]A ]Y Gfrr(O
G1 U, lY 2A 1'f )A lY CHO

Hex Bus Driver with Non-lnverting 3-State Hex Bus Driver with lnverting 3-State
Output (4-Line/2-Line Enable) Octal "D" Transparent Latch with 3-State
Output (4-Line/2-Line Enable) Output

Diag. 201 20-Pin DIP See Fig. D12 Diag. 202 20-Pin DIP See Fig. D12 Diag. 203 16-Pin DIP See Fig. D8
ECG74C374, ECG74HC374, ECG74HC377,ECG74LS377* ECG74LS378
ECG74HCT374, ECG74HC574,
ECG74HCT574*, ECG74LS374 80 80 10 70 60 60 50 50 CLOC K

YcclOIOJD7010

"' ... Etli A8L E 10

e
10 20 20 JO JO 40 4Q GNO ENABlE
e
10 10 10 10 30 10 GNO

Octal "D" Flip-Flop w ith 3-State Output Octal "D" Flip-Flop with Common Enable
* DISCONTINUED * DISCONTINUED Hex "D" Flip-Flop w ith Common Enable
TTL Logic Diagrams (cont'd)
Diag. 204 16-Pin DIP See Fig. D8 Diag. 205 14-Pin DIP See Fig. D6 Diag. 206 16-Pin DIP See Fig. D8
ECG74LS379 ECG74LS386 ECG74HC390,ECG74LS390
vcc vcc 48 4A 4Y 3Y 38 3A OU TPVTS
' JO ClOCk
2 OUTPl,JT
vcc 2A CLEAA 20A 2 8 ~

ENA8l.E 10 ll'f 10 10 20 GNO

,r IA
1A 18 ,V 2Y 2A 28 GNO 16 ~GND

Quad "D" Flip-Flop with Complementary OVTPUTS

Outputs Quad Exclusive OR Gate Dual Decade Counter

Diag. 207 14-Pin DIP See Fig. D6 Diag. 208 16-Pin DIP See Fig. D8 Diag. 209 20-Pin DIP See Fig. D12
ECG74393,ECG74HC393,ECG74LS393 ECG74LS395A ECG74LS398
OUTPIJTS OUT,UTS

CK

OUT,UT
CLEAA CONTROL

wo"o
uuc,
a.., 12 SI ffa 0a GNO

PARALLEL INPUTS
OUT,UTS
4-Bit Cascadable Parallel Shift Register with Quad 2-lnput Multiplexer with Storage
Dual 4-Bit Binary Counter 3-State Output Complementary Outputs

Diag. 210 16-Pin DIP See Fig. D8 Diag. 211 16-Pin DIP See Fig. D8 Diag. 212 20-Pin DIP See Fig. 012
ECG74LS399 ECG74490,ECG74LS490 ECG74LS540
ZOA 2 OUTPUTS
Vcc 0o 01 02 C2 Cl CLOCK
~~~9~
2 2 OUT
VCC CLOCK CLEAR f'\JT

01 02 C2 Cl

ws CK

1
CLOCIC CLEAA
1 10A
OVl
1
SET
~ G NO Octal Buffer/
PVT TOi OUH'UTS Une Driver
with lnverting
Quad 2-lnput Multiplexer with Storage Dual Decade Counter 3-State Output

Diag. 213 20-Pin DIP See Fig. 012 Diag. 214 14-Pin DIP See Fig. 06 Diag. 215 16-Pin DIP See Fig. 08
ECG74LS541 ECG74LS624 ECG74LS625
e to
Vcc CONTIIOI.. NC NC NC Vcc
;
OUTPUT

19

18

17

16

15

14

13
Octal Buffer/
Une Driver 12
il y
with Non-
lnverting
,, ONO (NAILE OUTP'UT

Voltage Controlled Oscillator with Dual Voltage Controlled Oscillator with

3-State Output Complementary Output Complementary Output
TTL Logic Diagrams (cont'd)
Diag. 216 16-Pin DIP See Fig. 08 Diag. 217 14-Pin DIP See Fig. 06 Diag. 218 16-Pin DIP See Fig. 08
ECG74LS626 ECG74LS627 ECG74LS629
2 Cut
GNO

1 8 1 FREO 1C)( l 1CX2 1Y GNO

Dual Voltage Controlled Oscillator with "ce CO'-llROl OUTf'UT

Complementary Output and Enable Dual Voltage Controlled Oscillator Dual Voltage Controlled Oscillator w ith Enable

Diag. 219 20-Pin DIP See Fig. 012 Diag. 220 20-Pin DIP See Fig. D12 Diag. 221 20-Pin DIP See Fig. 012
ECG74LS640 ECG74LS641 ECG74LS642
ENAB LE E N AB L E
EN.A.BLE
vcc G a1 12 BJ " es a, e1 aa v cc G a1 a2 BJ B-4 es B6 e1 68 vcc G u1 02 Bl B4 es es s7 se

OIR Al A2 Al A A5 A6 A7 AS G flrilO

Octal Bus Transceiver with lnverting 3-State Octal Bus Transceiver with Non-lnve rting Octal Bus Transceiver with lnverting Open
Output 3-State Open Collector Output Collector Output

Diag. 222 20-Pin DIP See Fig. D12 Diag. 223 20-Pin DIP See Fig. D12 Diag. 224 16-Pin DIP See Fig. D8
ECG74LS643 ECG74LS645 ECG74LS670
ENABLE.
H1 8? B3 8~ B~ 86 B7 ee vcc G s1 e2 B3 84 as es B7 ea

01 u,

04 U)

DIR Al A2 A) M AS A6 A7 A.8 GNO OIR Al A2 AJ A4 AS A6 A7 A8 GND

Octal Bus Transceiver w ith lnverting and Octal Bus Transceiver with Non, lnverting
Non-lnverting 3-State Output 3-State Output 4 x 4 Register File w ith 3-State Output

Diag. 225 14-Pin DIP See Fig. D6 Diag. 226 14-Pin DIP See Fig. D6 Diag. 227 14-Pin DIP See Fig. D6
ECG74C901 ECG74C902 ECG74C903

CND

Hex CMOS to TIL Interface Buffer (lnverting Hex CMOS to TIL Interface Buffer (Non- Hex PMOS to TIUCMOS Interface Buffer
Output) lnverting Output) (lnverting Output)
ITL Logic Diagrams (cont'd)
Diag. 229 18-Pin DIP See Fig. D10 Diag. 230 20-Pin DIP See Fig. D12 Diag. 232 16-Pin DIP See Fig. D8
ECG74C922 ECG74C923 ECG74HC4020
ROWYI 21 V,:c
ROWYI
AOW Y2 19 ol.l out
ROWYJ 11 DATA OUT A.
AOVI' VJ 11 DATA OUT 8
AOWYJ tl OAlAOUll

15 OATAOUTC
ROW Y4
" DATA OUl C

ROWY!i li O,.U. OUT 0

OSCIUA.TOR 14 DATA OUT O

l(YIOUfllCE IIA$1C 1l 01TffllTTllnlT

OSClllAYOA
" DATA OUT E

11.HBOUNCE WASK 14 OUTPUT hAILE

COLUIIN XC 1Z OAU 4VAILAILE IJ

COlliMN .U OAA AVAI LAIU
11
COlUMfll Xl COLU'-'frl Xl 12 COLUMN X1
COlUMN Xl

GNO !O COLUM~ Xl GNl IIJ

TOPVIEW TOPVIEW

16-Key Keyboard Encoder with 3-State 20-Key Keyboard Encoder with 3-State
Output Output 14-Stage Binary/Ripple Counter

Diag. 233 16-Pin DIP See Fig. D8 Diag. 234 16-Pin DIP See Fig. D8 Diag. 235 16-Pin DIP See Fig. 08
ECG74HC4040 ECG74HC4053 ECG74HC4060

2Y1 vcc 011 vcc

2Yo 2Z 012 Qg
3Yt 1Z 013 Q7
3Z 1Y1 Q5 Os
JYQ 1YO 04 MR
E so Q5 RS
VEE Q3
GND S2 GND CTC

14-Stage Ripple-Carry Binary Counter/

12-Stage Binary/Ripple Counter Triple 2-Channel Analog Multiplexer Divider and Oscillator

Diag. 236 24-Pin DIP See Fig . D15 Diag. 237 16-Pin DIP See Fig. D8 Diag. 238 16-Pin DIP See Fg. D8
ECG74HC4067 ECG74HC40105 ECG80C95
z vcc
Y7 Yg OE vcc
YS Yg DIR so
Y5
SI DOR
Y4

Y3 Y12 00 QO
Y2 V13 01 01
Y1 Y14
02 02
Yo Y15
03
So E
S1 S2
GND -,,_ _ __r- S3
Hex Buffer with 3-State Output (Common
16-Channel Multiplexer/Demultiplexer 4-Bit x 16-Word FIFO Register Enable)

Diag. 239 16-Pin DIP See Fig. D8 Diag. 240 16-Pin DIP See Fig. D8 Diag. 241 14-Pin DIP See Fig. D6
ECGSOC96 ECGSOC97 ECG8092
vcc Y2 e, 82

14 13 \1 10

OIS. IN , Ol.!1" , IN1 OVT2. 1111 OUT1 GHC OIS. IN . OL: 1 , 1~, OUT i 1~ 1 OVl ) Ct./0
e,
Hex lnverter/Buffer with 3-State Output Hex Buffer w ith 3-State Output (2-Line/
A1
' ' ( 1 Y1 GNO

(Common Enable) 4-Line Enable) Dual 5-lnput NAND Gate

TTL Logic Diagrams (cont'd)
Diag. 242 16-Pin DIP See Fig. 08 Diag. 243 24-Pin DIP See Fig. D15 Diag. 244 16-Pin DIP See Fig. D8
ECG8123 ECG8219 ECG8233
ENABLE
STROIE
INPUTS
-----.. OUTPUT
WUTS
OUTPUT
INPUT S
____,.___ ___,.___ ~
OUTPUT
SELECT
Vcc

,e
G

1s
A4

14
M

13
Y4

12
Al

11
83

10
Yl

9 VCC
24
E8
23
E9
22
OATA INPUTS

E10 E11 E12 E13 E14 E1S

21 20 19 18 17 16
------

SELECT

15
e
14
e
fl
vcc
16
A4
15
84
14
Y4
13
Y3
12
83
11
A3
10
S
9

3 7 9 10 11 12
f7 E6 ES E4 El E2 El EO ENABLE W D GN0
OUT DATA
DATA ~PUT S SELECl 1 2 3 4 5 6 7 8
s
SELECT
A1 81 Y1
OUTP\JT
A2 82

OUTPUT
GNO A1 81
---...- Y1
~
Y2 82
'---.--
A2 S2 GNO
SELECT
tNPUTS INPU TS OUTPUT INPUTS
Quad 2-Line-to-1-Line Data Selector/ 16-Line-to-1-Line Data Selector/Multiplexar Quad 2-Line-to-1-Line Data Selector/
Multiplexer with 3-State Output with lnverting 3-State Output Multiplexar

Diag. 245 16-Pin DIP See Fig. D8 Diag. 246 16-Pin DIP See Fig. D8 Diag. 247 16-Pin DIP See Fig. D8
ECG8234 ECG8235 ECG8266
INPUTS OUTPUT
INPUTS
,...._...,.____ OUTPUT
___,.___ ~ SELECT
_____,.____ Vcc A4 84 Y4 Y3 83 A3 S1
INPUTS OUTPUT
A4 84 .....+-16_-+-15_-+14_-L..13 12 11 10 9
15 14

5 6
82 A2 6
---.,--, Az
OUTPUT INPUTS 1 2 3 4 5 6 7 8 ~

A1 B1 Y1 Yz B2 A2 GNOS2 OUTPUT INPUTS

,_______, ~

SELECT
INPUTS OUTPUT INPUTS
Quad 2-Line-to-1-Line Data Selector/ Ouad 2-Line-to-1-Line Data Selector/
Multiplexar with lnverting Output Ouad 2-Une-to-1-Line Data Selector/ Multiplexer with Conditional Outputs
Multiplexer with Open Collector Output

Diag. 248 16-Pin DIP See Fig. 08 Diag. 249 24-Pin DIP See Fig. D15 Diag. 250 16-Pin DIP See Fig. D8
ECG8301 (See Also Diag. 269) ECG8309
ECG8308
--------
lNPUTS
OUTPUTS SELECT DATA INPUTS
Vcc A e -----. INPUT
Vcc Y2 Y2 A 2CO 2C 1 2C2 2C3
16 15 14
16 15 14 13 12 11 10

-------
e
INPUTS
o
OUTPUT9
GNO

--------
Yt

OUTPUTS
Vt SELECT
INPUT
B
1CO 1Ct

DATA INPUTS
1C2 1C3 GNO

Dual 4-Une-to-1-Line Data Selector/

BCD-to-Decimal Decoder Dual 4-Bit Latch Multiplexer w ith Complementary Output

Diag. 251 16-Pin DIP See Fig. D8 Diag. 252 16-Pin DIP See Fig. D8 Diag. 253 16-Pin DIP See Fig. D8
ECG8314 (See Also Diag. 270) ECG8318
ECG8316
01
15
.$2
14
03
12
,$4
11
Vcc
16
-----
OUTPUTS

EO
15
GS
14 13
IHPUTS

12 11
O
OUTPUT

10
AO

CLEAR LOAD

_2 3
$1 D1
6
6 8

El ~ GNO
ClEAR CLOCK A 8 C O ENABLE GNO INPUTS OUTPUTS
'----v------' p
DATA INPUTS
Presettable Synchronous 4-Bit Binary
Ouad Latch Counter with Dirct Clear 8-Line-to-3-Line Priority Encoder
TTL Logic Diagrams (cont'd)
Diag. 254 16-Pin DIP See Fig. D8 Diag. 255 16-Pin DIP See Fig. D8 Diag. 257 16-Pin DIP See Fig. D8
ECG8321 ECG8328 ECG8370

Q7 07 S D2 Dt
[5 14 13 12 11

..!2 3 4 5 6 7
07 07 $ D1 D2 CP2

REGI STER
2 l ATC H
( N.ti.lU
RB
OUT
,UT =~
PUT 1WUTI
QNO

Dual 2-Une-to-4-Une Decoder/Demultiptexer Dual 8-Bit Serial Shift Register Hexadecimal-to-7-Segment Decoder/Latch/
Driver with Open Collector Output
Diag. 258 16-Pin DIP See Fig. DB Diag. 259 16-Pin DIP See Fig. DB Diag. 260 16-Pin DIP See Fig. 08
ECG8374 ECG8520 ECG8542
OUTP\JTS

EXTERHAl
E:COR EX-OR 0000 SERtAL EX-OA
Vcc DIS 1 A4 84 B3 AJ CLOC!( CLEAR
PflESH INPUT OUTPUT OUTPUT GNO OETECT OUTPUT CONTAOl 16 15 14 13 12 11 10 9
15 ,. 13 12 11 10

SERIAL
INPUT
Pl SERIAL/
PARALLEL
P2 vcc P3
INPUT
1 2 3 4 5 6 7 8
INPUT
DIS 2 Al 81 B2 A2 E2 El GND

Hexadecimal-to-7-Segment Decoder/Driver/
Latch for Common Anode Displays Module "N" Divider Ouad 1/0 Register with 3-State Output

Diag. 261 16-Pin DIP See Fig. D8 Oiag. 263 16-Pin DIP See Fig. D8 Oiag. 264 16-Pin OIP See Fig. 08
ECG8S46 ECG8553 ECG8554
Vcc C2 IISI/L.80 1/ 0 1 1/ 0 2 1/ 0 3 1/0 4 00 DATA -.JTSt OUTPUTS

l,e 15 14 13 12
" ' 9 VCC
TRANSFER
ENABLE CP PRESET CLEAA NC CEP CET
16 15 14 13 12 11 10 9

- ....

5 a

c1
' 2

LS1/ll$0 1/0
3

a
4

110 1 110 6
5

1/ 0 5
7

CLOCI(
T
(IN)
....._........
OUTPUT
e D
OUTP\ITS
8 TEAM.
COUHT
(IN)

DISMt.fS

8-Bit Bidirectional 1/0 Shift Register with Synchronous 4-Bit Binary Counter/Latch
3-State 1/0 Unes 8-Bit Latch with 3-State 1/0 Unes with 3-State Output

Diag. 266 16-Pin DIP See Fig. D8 Oiag. 267 16-Pin OIP See Fig. 08 Oiag. 268 16-Pin DIP See Fig. 08
ECG8556
ce
....
COUHT 1/0o 110c 00 1/0g I I OA CLOCK
ECG8613

ce G4 04 04 GJ 03 03
ECGS853

16 ,s ,. 13 12 11 10 9 16 1S 13 12 10
CLEAA
9

2 4 S 8
CE 0o Oc AESET 0a GND
4 1 8 C i(1' Rx1 Co1 Dt1 t1 0 1 01 GHO
CLOCK G1 DI 01 D2 02
Presettable Synchronous 4-Bit Binary GND
Dual Retriggerable/Resettable Monostable
Counter w ith 3-State Output Quad Gated "D" Flip-Flop Multivibrator with Delay
TTL Logic Diagrams (cont'd)
Diag. 273 16-Pin DIP See Fig. DB Diag. 274 16-Pin DIP See Fig. 08
ECG9602, ECG96L02" ECG96S02 ECG9615
EXT
Vcc CAP R OUTA Vcc
ACTIVE
PULL UPA
ACTIVE
STROBEA PULL UP 8

AESPA STROBE B

RESP B

130(1
t
A
CAP EXT
R 8-
GND
Dual Retriggerable/Resettable Monostable
Multivibrator
* DtSCONTINUED Dual Differential Line Receiver