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org
Published in IET Power Electronics
Received on 19th March 2012
Revised on 1st September 2012
Accepted on 30th September 2012
doi: 10.1049/iet-pel.2012.0127

ISSN 1755-4535

Analysis and implementation of a new soft switching

DC/DC PWM converter
Bor-Ren Lin, Chih-Cheng Chien
Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 640, Taiwan
E-mail: linbr@yuntech.edu.tw

Abstract: This study presents a new DC/DC converter with series-connected transformers to achieve zero voltage switching
(ZVS) for power switches, less transformer secondary winding and partial ripple current cancellation. Two three-level circuits
using the same active switches are operated with interleaved half switching cycle. The voltage stress of all switches is
clamped at Vin/2. The transformers secondary windings are connected in series to balance the primary side currents. The
current-doubler rectier is adopted on the output side. Thus, the output inductor ripple currents can be partially cancelled
each other and the resultant ripple current at the output capacitor is reduced compared with the output ripple current of the
centre-tapped rectier topology. Based on the resonant behaviour by the output capacitance of active switches and the leakage
inductance (or external inductance), all power switches are turned on at ZVS. Laboratory experiments with a 1 kW prototype,
verifying the effectiveness of the proposed converter, are described.

1 Introduction applications. Three-level soft switching converters [1823]

Based on the efciency requirements of the Environment
Protection Agency (EPA) and Climate Saver Computing
Initiative (CSCI) for modern power supply units, power
converters with soft switching techniques have been
proposed for the cloud server power unit and
telecommunication applications. For medium/high-power
applications, three-phase power factor correctors (PFC) are
adopted in the front stage of the switching power units. The
DC bus voltage of a three-phase PFC circuit may be greater
than 500800 V. Thus, MOSFETs with 500 V (or 600 V)
voltage stress and low turn-on resistance cannot be used in
the rear DC/DC stage with half-bridge or full-bridge
converter. Although, the high-voltage MOSFETs such as
900 V voltage stress can be used in the rear DC/DC
converter, the disadvantages of high-voltage MOSFETs are
high cost and large turn-on resistance. To overcome the
voltage limitation of MOSFETs, three-level or multi-level
converters/inverters [16] have been proposed for high
voltage and medium/high-power applications. By using the
more MOSFETs, split capacitors and clamp diodes, the
voltage stress of each MOSFET can be reduced to one-half
of DC bus voltage. Therefore MOSFETs with 600 V
voltage stress can be used in the rear DC/DC converter for
high-input voltage applications. Soft switching techniques,
such as active clamped converters [79], asymmetric
half-bridge converters [10, 11], series resonant converters
[1214] and phase-shift full-bridge converters [1517], have
been proposed to achieve zero current switching (ZCS) at
turn-off instant or zero voltage switching (ZVS) at turn-on
instant. These topologies are based on the two-level PWM
scheme such that they cannot be used in the high-voltage
have been proposed in past decade to achieve ZCS or
ZVS for all switches at the desired load range. The
current-doubler rectiers [2426] have been adopted to
have one voltage drop, low-output ripple current and
low-current stress of the output lter inductors. Thus, the
current-doubler rectier has better efciency compared with
the centre-tapper rectier and diode bridge rectier for
high-output current applications.
This paper presents a new ZVS converter with two series
transformers and a current-doubler rectier for high-input
voltage applications. The main advantages of the proposed
converter are low switching losses, ZVS turn-on and
low-voltage stress on MOSFETs. Two three-level PWM
circuits with the same power switches and two series
transformers are adopted in the proposed converter to lessen
input ripple current, reduce the size of the magnetic core
and clamp the voltage stress of active switches at one-half
of the input voltage. The secondary windings of two
transformers are connected in series to balance the primary
currents. Phase-shift PWM scheme is used to regulate the
output voltage at the desired voltage level. Current-doubler
rectier is adopted at the secondary side to reduce the
ripple current at output capacitor. Current doubler rectier
can also reduce the secondary winding turns and decrease
the voltage stress of the rectier diodes such that the
conduction loss on the rectier diodes can be reduced.
Based on the resonant behaviour by the output capacitance
of switches and the leakage inductance of the transformer
(or external inductance) at the transition interval, all
switches can be turned on at ZVS. Experiments based on a
1 kW prototype to verify the effectiveness of the proposed
converter are described.

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Fig. 1 Circuit conguration of the proposed ZVS PWM converter

2 Circuit configuration and Css are large enough to be treated as three constant
voltages VC1 = VC2 = VCss = Vin/2 and (7) Co is large enough
The circuit conguration of the proposed three-level ZVS to be considered as a constant output voltage. Based on the
PWM converter is given in Fig. 1. Input capacitances Cin1 on/off states of S1 S4, Da Db and D1 D2, the proposed
and Cin2 are equal and large enough to share the input converter has ten operation modes in a switching period.
voltage vCin1 = vCin2 = Vin/2. S1 S4 are power MOSFETs The equivalent circuits of these modes are shown in Fig. 3.
and the voltage stresses of S1 S4 are clamped at Vin/2. Prior to time t0, S1, S2 and D1 are conducting. Inductor
Cr1 Cr4 are the output capacitances of MOSFETs S1 S4, currents iLr1(t0) < 0 and iLr2(t0) > 0.
respectively. Da and Db are the clamped diodes. Css is the Mode 1 [t0 t < t1, Fig. 3a]: At time t0, S1 is turned off.
ying capacitor and its voltage equals Vin/2. C1 and C2 are Since iLr1(t0) < 0 and iLr2(t0) > 0, Cr1 is charged and Cr4 is
the DC blocking capacitances. The average DC blocking discharged through the ying capacitor Css. The rising slope
voltages VC1 = VC2 = Vin/2. Lr1 and Lr2 are the resonant of the drain-to-source voltage of S1 is limited by Cr1 and
inductances. Lm1 and Lm2 are the magnetising inductances Cr4. Thus, S1 is turned off at ZVS. Since iLm1 (Io iLo1 )/n
of the transformers T1 and T2, respectively. D1 and D2 are and iLm2 (Io iLo1 )/n and Lo1 and Lo2 are large enough,
the rectier diodes. Lo1 and Lo2 are the output lter the primary currents iLr1 and iLr2 are almost constant in this
inductances. Ro and Co denote the load resistance and mode. Therefore Cr1 is charged linearly from zero voltage
output capacitance. There are two three-level ZVS PWM
circuits with the same power switches, the ying capacitor
and the clamped diodes in the proposed converter. The
components of the rst three-level circuit include Cin1, Cin2,
Da, Db, Css, S1 S4, Cr1 Cr4, C1, Lr1, T1, D1, D2, Lo1 and
Lo2. The second three-level PWM circuit includes the
components of Cin1, Cin2, Da, Db, Css, S1 S4, Cr1 Cr4,
C2, Lr2, T2, D1, D2, Lo1 and Lo2. The phase-shift PWM
scheme is used in the proposed converter. S1 and S4 are the
leading switches, and S2 and S3 are the lagging switches.
Three voltage levels Vin, Vin/2 and 0 are generated on the
terminal voltages vAB and vBC. Since the average voltages
VC1 = VC2 = Vin/2, three voltage levels Vin/2, 0 and Vin/2
are generated on the terminal voltages vp1 and vp2. The
primary and secondary windings of transformers T1 and T2
are connected in series in order to ensure that the primary
currents of T1 and T2 are balanced. The current-doubler
rectier with the series transformers is adopted at the
secondary side to obtain a stable output voltage Vo with one
diode conduction loss and to cancel partially the output
ripple current.

3 Operation principle
The theoretical PWM waveforms of the proposed converter in
a switching period are shown in Fig. 2. The following
assumptions are made to simplify the system analysis. (1)
Power semiconductors S1 S4, D1 D2 and Da Db are
ideal, (2) Lm1 = Lm2 = Lm, Lr1 = Lr2 = Lr Lm and Lo1 =
Lo2 = Lo, (3) Cin1 = Cin2 are large enough to be considered
as two voltage sources, (4) turns ratio of transformers T1
and T2 is n = np/ns, (5) Cr1 = Cr2 = Cr3 = Cr4 = Cr, (6) C1, C2 Fig. 2 Key waveforms of the proposed converter

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Fig. 3 Operation modes of the proposed converter during one switching cycle
a Mode 1 f Mode 6
b Mode 2 g Mode 7
c Mode 3 h Mode 8
d Mode 4 i Mode 9
e Mode 5 j Mode 10

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and Cr4 is discharged linearly from Vin/2. from Vin/2.

iLr2 (t0 ) iLr1 (t0 ) iLr2 (t2 ) iLr1 (t2 )

vCr1 (t) (t t0 ), vCr2 (t) (t t2 ),
2Cr 2Cr
(1) Vin iLr2 (t2 ) iLr1 (t2 )
Vin iLr2 (t0 ) iLr1 (t0 ) vCr3 (t) (t t2 ) (5)
vCr4 (t) (t t0 ) 2 2Cr
2 2Cr
The rising slope of the drain-to-source voltage of S2 is limited
Normally, the transformer magnetising inductance is designed by Cr2 and Cr3. Thus, S2 is turned off at ZVS. Since D1 and
to be large enough to neglect the magnetising current. We D2 are both conducting, the ZVS turn-on condition of S3 is
assumed that Lm n2 Lo and the ZVS turn-on condition of given as
S4 is given as

 C V2
Lr i2Lr1 (t2 ) + i2Lr2 (t2 ) r in (6)

 C V2 2
(Lr + n Lo ) i2Lr1 (t0 ) + i2Lr2 (t0 ) r in
2
(2)
2
Only the energy stored in Lr1 and Lr2 are used to discharge
Cr3. This mode ends at t3 when the capacitor voltages
This mode ends at t1 when the capacitor voltages vCr1 = Vin/2 vCr2 = Vin/2 and vCr3 = 0. The time interval of mode 3 is
and vCr4 = 0. The time interval of mode 1 is expressed as expressed as

Cr Vin nC V Cr Vin nCr Vin

Dt01 = t1 t0 = r in (3) Dt23 = t3 t2 = (7)
iLr2 (t0 ) iLr1 (t0 ) iLo, max iLr2 (t2 ) iLr1 (t2 ) iLo, min

The time delay td between S2 and S3 should be greater than the

where iLo,max is the maximum output inductor current. In order time interval t23 in order to achieve ZVS turn-on for S3. In
to ensure ZVS turn-on of S4, the time delay td between S1 and mode 3, the semiconductor losses are the conduction losses
S4 should be greater than the time interval t01. The main of S4, D1 and D2.
power semiconductor losses are the conduction losses of S2 Mode 4 [t3 t < t4, Fig. 3d]: At time t3, vCr3 = 0. Since
and D1. iLr1(t3) iLr2(t3) < 0, the anti-parallel diode of S3 is
Mode 2 [t1 t < t2, Fig. 3b]: At time t1, vCr1 = Vin/2 and conducting. Thus, S3 can be turned on at this moment to
the clamped diode Da is conducting such that the capacitor achieve ZVS. In mode 4, the terminal voltages vAB = Vin,
voltage vCr4 = 0 (since vCss = Vin/2). In this mode, vAB = vBC = vBC = 0, vp1 = Vin/2 and vp2 = Vin/2. Since D1 and D2 are
Vin/2 and vp1 = vp2 = 0. The primary and secondary winding still conducting in this mode, the inductor currents iLo1 and
voltages of T1 and T2 are zero voltage. Thus, D1 and D2 are iLo2 decrease with the slope of Vo/Lo. The inductor
both conducting and the output inductor voltages vLo1 = voltages vLr1 = Vin/2 and vLr2 = Vin/2 such that the primary
vLo2 = Vo. The inductor currents iLo1 and iLo2 both decrease currents and the slopes of the diode currents are given as
with the slope of Vo/Lo in this mode. Diode current iD1
decreases and iD2 increases in mode 2. Thus, the primary Vin
currents and the slopes of the diode currents are given as iLr1 (t) = iLr1 (t3 ) + (t t3 ),
2Lr
Vin
iLr2 (t) = iLr2 (t3 ) (t t3 )
VS2,drop + VDa,drop 2Lr
iLr1 (t) = iLr1 (t1 ) + (t t1 ),
Lr diD1 (t) nV diD2 (t) nVin
= in , = (8)
VS2,drop + VDa,drop dt 2Lr dt 2Lr
iLr2 (t) = iLr2 (t1 ) (t t1 )
Lr
This mode ends at time t4 when the diode current iD1 is equal
to zero. The time interval in this mode is given as
diD1 (t) n(VS2,drop + VDa,drop )
= , 2Lr Io
dt Lr Dt34 = t4 t3 (9)
nVin
diD2 (t) n(VS2,drop + VDa,drop )
= (4)
dt Lr No power is transferred from input voltage source Vin to
output load Ro. Thus, the duty loss in mode 4 is expressed as
where VS2,drop and VDa,drop are the voltage drop on switch S2
and diode Da, respectively. If these drop voltages can be Dt34 2Lr Io fs
dloss,4 = (10)
neglected, then the primary currents iLr1 and iLr2 and diode Ts nVin
currents iD1 and iD2 are unchanged in this mode. In this
mode, the main semiconductor losses are the conduction where Ts and fs are the switching period and switching
losses of S2, S4, D1 and D2. This mode ends at time t2 frequency, respectively. In mode 4, the semiconductor
when S2 is turned off. losses are the conduction losses of S3, S4, D1 and D2.
Mode 3 [t2 t < t3, Fig. 3c]: At time t2, S2 is turned off. Mode 5 [t4 t < t5, Fig. 3e]: At time t4, iD1 = 0.
Since iLr1(t2) < 0 and iLr2(t2) > 0, Cr2 is charged linearly Transformers T1 and T2 are working as the forward type
through Css from zero voltage and Cr3 is discharged linearly transformers. The primary current iLr1 increases linearly and

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iLr2 decreases linearly in this mode conducting, the ZVS turn-on condition of S2 is given as

Vin nVo
iLr1 (t) = iLr1 (t4 ) + (t t4 ),
2Lr + n2 Lo
Vin nVo
iLr2 (t) = iLr2 (t4 ) (t t4 )
2Lr + n2 Lo
Power is delivered from input voltage source Vin to output
load Ro in this mode. In mode 5, the semiconductor losses
are the conduction losses of S3, S4 and D2. This mode ends
at t5 when S4 is turned off.
Mode 6 [t5 t < t6, Fig. 3f]: At time t5, S4 is turned off.
Since iLr1(t5) > 0 and iLr2(t5) < 0, Cr1 is discharged linearly
from Vin/2 and Cr4 is charged linearly from zero voltage
through capacitor Css in this mode. Thus, the rising slope of
the drain-to-source voltage of S4 is limited by Cr1 and Cr4.
Thus, S4 is turned off at ZVS. Since Lo1 and Lo2 are large
enough, the primary currents iLr1 and iLr2 are almost
constant in this mode. The ZVS condition of S1 is given as

 C V2
(Lr + n2 Lo ) i2Lr1 (t5 ) + i2Lr2 (t5 ) r in
2 in mode 9. The inductor voltages vLr1 = Vin/2 and vLr2 =
This mode ends at t6 when vCr1 = 0 and vCr4 = Vin/2. The time
interval of mode 6 is given as

 C V2
Lr i2Lr1 (t7 ) + i2Lr2 (t7 ) r in (15)
(11) 2
This mode ends at t8 when vCr2 = 0 and vCr3 = Vin/2. The time
interval in mode 8 is expressed as
Cr Vin nC V
Dt78 = t8 t7 = = r in (16)
iLr1 (t7 ) iLr2 (t7 ) iLo, min
The time delay td between S2 and S3 should be greater than the
time interval t78. Thus, S2 can be tuned on at ZVS. In mode
8, the semiconductor losses are the conduction losses of S1,
D1 and D2.
Mode 9 [t8 t < t9, Fig. 3i]: After t8, vCr2 = 0. Since
iLr2(t8) iLr1(t8) < 0, the anti-parallel diode of S2 is
conducting. Therefore S2 can be turned on at this moment
to achieve ZVS. In this mode, the voltages vAB = 0, vBC =
Vin, vp1 = Vin/2 and vp2 = Vin/2. Since D1 and D2 are still
(12) conducting, the inductor currents iLo1 and iLo2 both decrease
Vin/2 such that the primary currents and the slopes of the
diode currents are given as

Cr Vin nCr Vin Vin

Dt56 = t6 t5 = (13) iLr1 (t) = iLr1 (t8 ) (t t8 ),
iLr1 (t5 ) iLr2 (t5 ) iLo, max 2Lr
Vin
The time delay td between S1 and S4 should be greater than the iLr2 (t) = iLr2 (t8 ) + (t t8 ),
2Lr
time interval t56. Therefore Cr1 can be decreased to zero
voltage and S1 is turned on at ZVS. In mode 6, the diD1 (t) nVin diD2 (t) nV
= , = in (17)
semiconductor losses are the conduction losses of S3 and D2. dt 2Lr dt 2Lr
Mode 7 [t6 t < t7, Fig. 3g]: At t6, vCr4 = Vin/2 such that
the clamped diode Db is conducting and the capacitor voltage This mode ends at t9 when iD2 = 0. The time interval in mode
vCr1 = 0. In this mode, the terminal voltages vAB = vBC = Vin/2 9 is given as
and vp1 = vp2 = 0. Thus, D1 and D2 are conducting. The output
inductor voltages vLo1 = vLo2 = Vo and the inductor currents
2Lr Io
iLo1 and iLo2 both decrease. Diode current iD1 increases and Dt89 = t9 t8 (18)
iD2 decreases in mode 7. The primary currents iLr1 and iLr2 nVin
and the slopes of the diode currents iD1iD2 are given as
Thus, the duty loss in mode 9 is expressed as
VS3,drop + VDb,drop
iLr1 (t) = iLr1 (t6 ) (t t6 ),
Lr Dt89 2Lr Io fs
dloss,9 = (19)
VS3,drop + VDb,drop Ts nVin
iLr2 (t) = iLr2 (t6 ) + (t t6 )
Lr
In mode 9, the semiconductor losses are the conduction losses
of S1, S2, D1 and D2
diD1 (t) n(VS3,drop + VDb,drop ) Mode 10 [t9 t < t0 + Ts, Fig. 3j]: At t9, iD2 = 0.
= , Transformers T1 and T2 are working as the forward type
dt Lr transformers. The primary current iLr1 decreases linearly and
diD2 (t) n(VS3,drop + VDb,drop ) iLr2 increases linearly in this mode
= (14)
dt Lr
Vin nVo
iLr1 (t) = iLr1 (t9 ) (t t9 ),
In mode 7, the semiconductor losses are the conduction losses 2Lr + n2 Lo
of S1, S3, D1 and D2. This mode ends at time t7 when S3 is Vin nVo
turned off. iLr2 (t) = iLr2 (t9 ) + (t t9 ) (20)
Mode 8 [t7 t < t8, Fig. 3h]: At t7, S3 is turned off. Since 2Lr + n2 Lo
iLr1(t7) > 0 and iLr2(t7) < 0, Cr2 is discharged linearly from
Vin/2 and Cr3 is charged linearly from zero voltage through In mode 10, the semiconductor losses are the conduction
the ying capacitor Css. The rising slope of the losses of S1, S2 and D1. This mode ends at t0 + Ts when S1
drain-to-source voltage of S3 is limited by Cr2 and Cr3. is turned off. Then the circuit operations of the proposed
Thus, S3 is turned off at ZVS. Since D1 and D2 are both converter in a switching period are completed.

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4 Circuit characteristics and (22), the output voltage can be further expressed in (23)

Since the transition intervals at turn-off instant in modes 1, 3,  

Vin 2L I f
6 and 8 are much less than the time intervals in modes 2, 4, 5, Vo = d r o s Vf (23)
7, 9 and 10, the effects of the transition intervals at turn-off n nVin
instant are neglected to derive the DC voltage conversion
ratio of the proposed converter. In modes 2 and 7, we can In (23), the output voltage Vo is a function of , Vin, fs, Lr, n
obtain the average capacitor voltage VCss is equal to Vin/2. and Io. In steady state, the average output inductor currents
Based on the volt-second balance on Lr1 and Lm1, we can ILo1 = ILo2 = Io/2. The ripple currents of Lo1 and Lo2 are
obtain the average blocking capacitor voltage VC1 in (21) given in (24).

VC1 = Vin /2 (21) Vo + Vf

DiLo1 = DiLo2 = (1 d + dloss,4 )Ts
Lo
In the same manner, the average capacitor voltage VC2 =  
Vin/2. The DC voltage gain of the proposed converter can (Vo + Vf ) 2Lr Io fs
= 1d+ (24)
be derived from the volt-second balance on Lo1 and Lo2 Lo fs nVin

V o + Vf d dloss,4 Thus, the maximum and minimum output inductor currents at

= (22)
Vin n steady state are expressed in (25)
 
where Vf is the voltage drop on diode D1 and D2. From (10) Io (Vo + Vf ) 2Lr Io fs
iLo1,max = iLo2,max = + 1d+
2 2Lo fs nVin
Table 1 Parameters and components of the prototype circuit  
Io (Vo + Vf ) 2Lr Io fs
input voltage Vin = 480580 V iLo1,min = iLo2,min = 1d+ (25)
output voltage Vo = 24 V 2 2Lo fs nVin
output power Po = 1 kW
switching frequency fs = 100 kHz
resonant inductances Lr1 = Lr2 = 20 H The minimum output inductance is obtained by the dened
transformers T1, T2 EER-40C core with np/ns = 46 turns/ maximum output ripple current
5 turns and Lm1 = Lm2 = 1 mH
output inductances Lo1 = Lo2 = 40 H with MPP core and 30 A  
current rating (Vo + Vf ) 2Lr Io fs
capacitors electrolytic capacitor Co = 6600 F/50 V
Lo,min = 1d+ (26)
DiLo1, max fs nVin
MPP capacitors C1 = C2 = 0.32 F and Css = 0.94 F
switches S1 S4: IRFP460 (500 V/20 A,
RDS,on = 0.27 ); Since the average currents on capacitor of C1 C2 are all
diodes D1 D2: STPS40H100CW (100 V/40 A);
Da Db: 30ETH06 (600 V/30 A)
zero, the average magnetising currents ILm1 and ILm2 are
equal to zero. The ripple currents of the magnetising

Fig. 4 Basic graphical structure of the complete experimental circuit model

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inductances Lm1 and Lm2 can be obtained in modes 5 and 10. Therefore the maximum and minimum magnetising currents
are given as

Vin (d dloss,4 )Ts dVin Ts Lr Io

DiLm1 = DiLm2 = (27) dVin Ts LI
2Lm 2Lm nLm iLm1,max = iLm2,max = ro ,
4Lm 2nLm
dVin Ts LI
iLm1,min = iLm2,min = + ro (28)
4Lm 2nLm

The average and root-mean-square (rms) currents of the

rectier diodes D1 and D2 are expressed as


ID1,av = ID2,av Io /2, iD1,rms = iD2,rms Io / 2 (29)

In modes 5 and 10, we can obtain the voltage stresses of D1

and D2

vD1,stress = vD2,stress Vin /n (30)

Fig. 5 Measured waveforms of the gate voltages of S1 and S2 and Fig. 6 Measured waveforms of the gate voltage, drain voltage and
the primary side voltages vp1 and vp2 at full load switch current at the nominal input voltage Vin = 530 V and 25%
a Vin = 480 V load
b Vin = 530 V a Switches S1 and S2
c Vin = 580 V b Switches S3 and S4

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At time t0, we can obtain the peak current of switch S1 Based on the three-level DC/DC circuit topology and the
capacitor voltages VCss = VC1 = VC2 = Vin/2, the voltage
stress of S1 S4 is equal to Vin/2. In mode 10, the primary
iS1,max = iS1 (t0 ) = iLr2 (t0 ) iLr1 (t0 ) = iLo2,max /n side inductor currents iLr1(t0) (or iLr1(Ts + t0)) and iLr2(t0) (or
+ iLm2,max (iLo2,max /n + iLm1,min ) iLr2(Ts + t0)) are obtained in (34)
 
Io (Vo + Vf ) 2Lr Io fs
+ 1d+
n nLo fs nVin iLo2,max dV T LI I
iLr1 (t0 ) = iLm1,min = in s + r o o
dVin Ts Lr Io n 4Lm 2nLm 2n
+ (31)  
2Lm nLm (Vo + Vf ) 2L I f
1d+ r o s
2nLo fs nVin
Similarly, the peak currents of S2 S4 can be obtained in (32)

iLo2,max dVin Ts LI I
iS2,max = iS3,max = iS4,max = iS1,max (32) iLr2 (t0 ) = iLm2,max + = ro + o
n 4Lm 2nLm 2n
 
If the ripple currents of active switches can be neglected, the (Vo + Vf ) 2Lr Io fs
+ 1d+ (34)
rms currents of S1 S4 are given as 2nLo fs nVin

I
iS1,rms = iS4,rms iS2,rms = iS3,rms o  (33) In the same manner, the primary side inductor currents iLr1(t2)
n 2

Fig. 7 Measured waveforms of the gate voltage, drain voltage and Fig. 8 Measured waveforms of the gate voltage, drain voltage and
switch current at the nominal input voltage Vin = 530 V and 50% switch current at the nominal input voltage Vin = 530 V and 100%
load load
a Switches S1 and S2 a Switches S1 and S2
b Switches S3 and S4 b Switches S3 and S4

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and iLr2(t2) in mode 2 are given as

(VS2,drop + VDa,drop )Dt12

iLr1 (t2 ) iLr1 (t0 ) +
Lr
dVin Ts LI I
+ ro o
4Lm 2nLm 2n
 
(V + Vf ) 2L I f
o 1d+ r o s
2nLo fs nVin
(VS2,drop + VDa,drop )(0.5 d)
+
Lro fs

Fig. 9 Measured waveforms of the gate voltage vS1,gs the DC

blocking voltages vC1 and vC2 and the ying capacitor voltage vCss
at full load Fig. 10 Measured waveforms of the proposed converter at full
load and Vin = 480 V
a Vin = 480 V
b Vin = 530 V a Primary side currents
c Vin = 580 V b Secondary side currents

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In the same manner, the necessary inductance Lr to achieve
(VS2,drop + VDa,drop )Dt12 ZVS of S2 and S3 is given as
iLr2 (t2 ) iLr2 (t0 )
Lr
  Cr Vin2
dV T LI I (Vo + Vf ) 2L I f Lr
2  (37)
in s r o + o + 1d+ r o s 2 iLr1 (t2 ) + i2Lr2 (t2 )
4Lm 2nLm 2n 2nLo fs nVin
(VS2,drop + VDa,drop )(0.5 d)
(35)
Lr fs
5 Test results
The necessary resonant inductance Lr for ZVS turn-on of S1 Experimental results are demonstrated in this section to verify
and S4 is given as the effectiveness of the proposed converter. The rated power
of the proposed converter is 1 kW with Vo = 24 V. The
Cr Vin2 minimum, nominal and maximum input terminal voltages
Lr
2  n2 Lo (36) are 480 , 530 and 580 V, respectively. The switching
2 iLr1 (t0 ) + i2Lr2 (t0 ) frequency fs = 100 kHz. The assumed circuit efciency at

Fig. 11 Measured waveforms of the proposed converter at full Fig. 12 Measured waveforms of the proposed converter at full
load and Vin = 530 V load and Vin = 580 V
a Primary side currents a Primary side currents
b Secondary side currents b Secondary side currents

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Fig. 13 Measured circuit efciencies of the proposed converter at
the different input voltages and load conditions
rated power is 92%. We assume the maximum duty ratio
max = 0.5 at minimum input voltage and full load condition.
We assume that the maximum duty cycle loss in mode 4 or
9 at minimum input voltage and full load condition is <5%.
Based on the circuit characteristics of the proposed
converter discussed in Section 4, the selected circuit
parameters are shown in Table 1. The basic graphical
structure of the complete experimental circuit model is
shown in Fig. 4 in this revision. The measured waveforms
of the gate voltages of switches S1 and S2 and the primary
side voltages vp1 and vp2 at full load and the different input
voltages are illustrated in Fig. 5. There are three voltage
levels Vin/2, 0 and Vin/2 generated on vp1 and vp2. The
measured gate voltage, drain voltage and switch current of
switches S1 S4 at 25% load and the nominal input voltage
Vin = 530 V are given in Figs. 68 show the measured gate
voltage, drain voltage and switch current of S1 S4 at 50%
and 100% load, respectively. From the measured results in
Figs. 57, S1 S4 are all turned on at ZVS from 25% to
100% loads and the voltage stress of S1 S4 is Vin/2. Fig. 9
gives the measured results of the gate voltage vS1,gs and
capacitor voltages vC1, vC2 and vCss at full load and the
different input voltage conditions. vC1, vC2 and vCf are
almost constant and equal Vin/2. The measured gate
voltages vS1,gs and vS2,gs and the main currents at the
primary side with full load and Vin = 480 V are illustrated in
Fig. 10a. When switches S1 and S2 are in the on-states, iLr1
decreases and iLr2 increases. If switches S1 and S2 are in the
off-state, iLr1 increases and iLr2 decreases. Fig. 10b gives
the measured secondary side diode and inductor currents. The
switch currents, the rectier diode currents and the output
inductor currents are balanced from the measured results in
Fig. 10. Figs. 11 and 12 give the measured waveforms of
the primary side and the secondary side currents at full load
and Vin = 530 and 580 V, respectively. The measured circuit
efciencies of the proposed converter at the different input
voltages and load conditions are shown in Fig. 13.
6 Conclusion
A new three-level DC/DC converter with two series
transformers is presented to achieve ZVS turn-on for all
switches from 25 to 100% load, reduce the voltage stress of
MOSFET at Vin/2 and partially cancel the output ripple
current by current-doubler rectier. Thus, the switching
losses are reduced and the circuit efciency is increased.
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& The Institution of Engineering and Technology 2013
Two three-level circuits with the same active switches are
operated to reduce the ripple current at the input side. The
secondary windings of transformers are connected in series
to ensure that the primary side currents are balanced to
share the load power. A current-doubler rectier is used at
the secondary side to partially cancel the output inductor
ripple current. Phase-shift PWM is adopted to control four
MOSFETs and regulate the output voltage. The system
analysis, operation mode and design example of the
proposed converter are discussed in detail. Finally,
experiments verifying the effectiveness of the converter are
described.
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& The Institution of Engineering and Technology 2013