Junction Field Effect Transistor (JFET)

A JFET is a three terminal semiconductor device in which current conduction is by one type of
carrier i.e. electrons or holes.
Symbol:

The current conduction is controlled by means of an electric field between the gate and the
conducting channel of the device.The JFET has high input impedance and low noise level.
Construction Details:
A JFET consists of a p-type or n-type silicon bar containing two pn junctions at the sides. If the
bar is of p-type, it is called p-channel JFET as shown in fig.1(i) and if the bar is of n-type, it is
called n-channel JFET as shown in fig.1(ii).

The two pn junctions forming diodes are connected internally and a common terminal called gate
is taken out. Other terminals are source and drain taken out from the bar as shown in fig.1. Thus a
JFET has three terminals such as , gate (G), source (S) and drain (D).
Working of JEFT
The working of JFET can be explained as follows:
Case-i:
When a voltage VDS is applied between drain and source terminals and voltage on the gate is zero
as shown in fig.3(i), the two pn junctions at the sides of the bar establish depletion layers.

The electrons will flow from source to drain through a channel between the depletion layers. The
size of the depletion layers determines the width of the channel and hence current conduction
through the bar.
Case-ii:
When a reverse voltage VGS is applied between gate and source terminals, as shown in fig.3(ii),
the width of depletion layer is increased.
This reduces the width of conducting channel, thereby increasing the resistance of n-type bar.
Consequently, the current from source to drain is decreased. On the other hand, when the reverse
bias on the gate is decreased, the width of the depletion layer also decreases. This increases the
width of the conducting channel and hence source to drain current. A p-channel JFET operates in
the same manner as an n-channel JFET except that channel current carriers will be the holes instead
of electrons and polarities of VGS and VDS are reversed.
The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor is a semiconductor
device which is widely used for switching and amplifying electronic signals in the electronic
devices. The MOSFET is a core of integrated circuit and it can be designed and fabricated in a
single chip because of these very small sizes. The MOSFET is a four terminal device with
source(S), gate (G), drain (D) and body (B) terminals. The body of the MOSFET is frequently
connected to the source terminal so making it a three terminal device like field effect transistor.
The MOSFET is very far the most common transistor and can be used in both analog and digital
circuits.
Depletion Mode:
When there is no voltage on the gate, the channel shows its maximum conductance. As the voltage
on the gate is either positive or negative, the channel conductivity decreases.
Enhancement mode:
When there is no voltage on the gate the device does not conduct. More is the voltage on the gate,
the better the device can conduct.

The aim of the MOSFET is to be able to control the voltage and current flow between the source
and drain. It works almost as a switch. The working of MOSFET depends upon the MOS capacitor.
The MOS capacitor is the main part of MOSFET. The semiconductor surface at the below oxide
layer which is located between source and drain terminal. It can be inverted from p-type to n-type
by applying a positive or negative gate voltages respectively. When we apply the positive gate
voltage the holes present under the oxide layer with a repulsive force and holes are pushed
downward with the substrate. The depletion region populated by the bound negative charges which
are associated with the acceptor atoms. The electrons reach channel is formed. The positive voltage
also attracts electrons from the n+ source and drain regions into the channel. Now, if a voltage is
applied between the drain and source, the current flows freely between the source and drain and
the gate voltage controls the electrons in the channel. Instead of positive voltage if we apply
negative voltage , a hole channel will be formed under the oxide layer.
32.b

Truth Table
The registers discussed so far involved only right shift operations. Each right shift operation has
the effect of successively dividing the binary number by two. If the operation is reversed (left
shift), this has the effect of multiplying the number by two. With suitable gating arrangement a
serial shift register can perform both operations.
A bidirectional, or reversible, shift register is one in which the data can be shift either left or
right. A four-bit bidirectional shift register using D flip-flops is shown below

With M = 1 Shift right operation

If M = 1, then the AND gates 1, 3, 5 and 7 are enabled whereas the remaining AND gates 2, 4, 6
and 8 will be disabled. The data at DRis shifted to right bit by bit from FF-3 to FF-0 on the
application of clock pulses. Thus with M = 1 we get the serial right shift operation.
With M = 0 Shift left operation
When the mode control M is connected to 0 then the AND gates 2, 4, 6 and 8 are enabled while
1, 3, 5 and 7 are disabled. The data at DLis shifted left bit by bit from FF-0 to FF-3 on the
application of clock pulses. Thus with M = 0 we get the serial right shift operation.
Parity Checker:
It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even
parity checker or odd parity checker depending on the type of parity generated at the
transmission end. When this circuit is used as even parity checker, the number of input bits must
always be even.
When a parity error occurs, the sum even output goes low and sum odd output goes high. If
this logic circuit is used as an odd parity checker, the number of input bits should be odd, but if
an error occurs the sum odd output goes low and sum even output goes high.
Consider that three input message along with even parity bit is generated at the transmitting end.
These 4 bits are applied as input to the parity checker circuit which checks the possibility of error
on the data. Since the data is transmitted with even parity, four bits received at circuit must have
an even number of 1s.
If any error occurs, the received message consists of odd number of 1s. The output of the parity
checker is denoted by PEC (parity error check).
The below table shows the truth table for the even parity checker in which PEC = 1 if the error
occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no error occurs, i.e., if
the 4-bit message has even number of 1s.

Sequence Detector:
Sequential Circuits:
Sequential circuits works on a clock cycle which may be synchronous or asynchronous. The
figure shows a basic diagram of sequential circuits. Sequential circuits use current inputs and
previous inputs by storing the information and putting back into the circuit on the next clock
cycle. In this model of FSM, the output values are determined both by its current state and the
current inputs. The state diagram of a mealy machine associates an output value with each
transition edge.

Here 1/1, 1/0, 0/1, 0/0 represent input/output and S0, S1, S2 represent the states. Consider a part
of the state diagram S1 -> S2 where 0/1 is written on the arrow. This can be interpreted as,
when the current state of the system is S1 and when input 0 is applied, the system goes into
next state - S2 and the output of the system is 1. Suppose a sequence detector is to be designed
to detect a sequence 1101. Then the state diagram will be: