Examen VHDL Codigo

library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity contador_reloj is
PORT (
clk : IN STD_LOGIC; --Reloj de 1Hz.
reset: IN STD_LOGIC; --Seal de reset.
H1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --Segundo digito de la hora.
H0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --Primer digito de la hora.
M1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --Segundo digito de los minutos.
M0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) --Primer digito de los minutos.
);
end contador_reloj;
architecture Behavioral of contador_reloj is

signal mm1: UNSIGNED(2 downto 0) := "000" ;
signal mm0: UNSIGNED(3 downto 0) := "0000";
signal hh1: UNSIGNED(2 downto 0) := "000" ;
signal hh0: UNSIGNED(3 downto 0) := "0000";
begin
reloj: process (clk, reset) begin
if reset = '1' then
hh1 <= "000" ;
hh0 <= "0000";
mm1 <= "000" ;
mm0 <= "0000";
elsif rising_edge(clk) then
mm0 <= mm0 + 1;
if mm0 = 9 then
mm1 <= mm1 + 1;
mm0 <= "0000";
end if;
-- Al pasar 59 minutos, contar una hora.
if mm1 = 5 AND mm0 = 9 then
hh0 <= hh0 + 1;
mm1 <= "000";
end if;
if hh0 = 9 then
hh1 <= hh1 + 1;
hh0 <= "0000";
end if;
-- Al pasar 23:59, regresar a 00:00.
if hh1 = 2 AND hh0 = 3 AND mm1 = 5 AND mm0 = 9 then
hh1 <= "000";
hh0 <= "0000";
end if;
end if;
end process;
--Asignacin de seales.
H1 <= STD_LOGIC_VECTOR(hh1);
H0 <= STD_LOGIC_VECTOR(hh0);
M1 <= STD_LOGIC_VECTOR(mm1);
M0 <= STD_LOGIC_VECTOR(mm0);
end Behavioral;
library IEEE;
entity clk1Hz is
Port (
entrada: in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end clk1Hz;
architecture Behavioral of clk1Hz is

signal temporal: STD_LOGIC;
signal contador: integer range 0 to 24999999 := 0;
begin
divisor_frecuencia: process (reset, entrada) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(entrada) then
if (contador = 24999999) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
end process;
salida <= temporal;

end Behavioral;
library IEEE;
entity reloj is
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
salida: OUT STD_LOGIC_VECTOR(7 downto 0);
MUX : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end reloj;
architecture Behavioral of reloj is

COMPONENT clk1Hz IS
PORT (
entrada: IN STD_LOGIC;
salida : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT contador_reloj IS
PORT (
clk : IN STD_LOGIC;
reset: IN STD_LOGIC;
H1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
H0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT siete_segmentos_completo IS
PORT (
clk : IN STD_LOGIC;
D0 : IN STD_LOGIC_VECTOR(5 downto 0);
);
END COMPONENT;
signal clk_out : STD_LOGIC := '0';

signal HH1, MM1: STD_LOGIC_VECTOR(2 downto 0);
signal HH0, MM0: STD_LOGIC_VECTOR(3 downto 0);
signal pHH1, pHH0, pMM1, pMM0: STD_LOGIC_VECTOR(5 downto 0);
begin
--PORT MAPs necesarios para habilitar el reloj.
clk_i: clk1Hz PORT MAP(clk, reset, clk_out);
cnt_i: contador_reloj PORT MAP(clk_out, reset, HH1, HH0, MM1, MM0);
seg_i: siete_segmentos_completo PORT MAP(clk, reset, pMM0, pMM1, pHH0, pHH1, salida, MUX);
--Padding de las seales del contador para siete segmentos.

pHH1 <= "000" & HH1;
pHH0 <= "00" & HH0;
pMM1 <= "000" & MM1;
pMM0 <= "00" & MM0;
end Behavioral;
library IEEE;
use IEEE.NUMERIC_STD.ALL;
entity siete_segmentos is
PORT (
entrada: IN STD_LOGIC_VECTOR(5 downto 0);
salida : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end siete_segmentos;
architecture Behavioral of siete_segmentos is

begin
visualizador: process (entrada) begin
case entrada is
when "000000" => salida <= x"C0"; -- 0
when "000001" => salida <= x"F9"; -- 1
when "000010" => salida <= x"A4"; -- 2
when "000011" => salida <= x"B0"; -- 3
when "000100" => salida <= x"99"; -- 4
when "000101" => salida <= x"92"; -- 5
when "000110" => salida <= x"82"; -- 6
when "000111" => salida <= x"F8"; -- 7
when "001000" => salida <= x"80"; -- 8
when "001001" => salida <= x"98"; -- 9
when "001010" => salida <= x"88"; -- A
when "001011" => salida <= x"83"; -- B
when "001100" => salida <= x"C6"; -- C
when "001101" => salida <= x"A1"; -- D
when "001110" => salida <= x"86"; -- E
when "001111" => salida <= x"8E"; -- F
when "010000" => salida <= x"90"; -- G
when "010001" => salida <= x"89"; -- H
when "010010" => salida <= x"E6"; -- I
when "010011" => salida <= x"E1"; -- J
when "010100" => salida <= x"85"; -- K
when "010101" => salida <= x"C7"; -- L
when "010110" => salida <= x"C8"; -- M
when "010111" => salida <= x"AB"; -- N
when "011000" => salida <= x"C0"; -- O
when "011001" => salida <= x"8C"; -- P
when "011010" => salida <= x"98"; -- Q
when "011011" => salida <= x"AF"; -- R
when "011100" => salida <= x"92"; -- S
when "011101" => salida <= x"87"; -- T
when "011110" => salida <= x"E3"; -- U
when "011111" => salida <= x"C1"; -- V
when "100000" => salida <= x"E2"; -- W
when "100001" => salida <= x"8F"; -- X
when "100010" => salida <= x"91"; -- Y
when "100011" => salida <= x"B6"; -- Z
when "100100" => salida <= x"BF"; -- -
when "100101" => salida <= x"F7"; -- _
when "100110" => salida <= x"7F"; -- .
when others => salida <= x"FF"; -- Nada
end case;
end process;
end Behavioral;
library IEEE;
entity siete_segmentos_completo is
PORT (
clk : IN STD_LOGIC;
);
end siete_segmentos_completo;
architecture Behavioral of siete_segmentos_completo is

COMPONENT clk200Hz IS
PORT (
);
END COMPONENT;
COMPONENT siete_segmentos IS
PORT (
);
END COMPONENT;
COMPONENT siete_segmentos_mux IS
PORT (
clk : IN STD_LOGIC;
);
END COMPONENT;

signal digito : STD_LOGIC_VECTOR(5 downto 0);
begin
clk_i: clk200Hz PORT MAP(
clk, reset, clk_out
);
mux_i: siete_segmentos_mux PORT MAP(

clk_out, reset, "000000", "000001", "000010", "000011", digito, MUX
);
seg_i: siete_segmentos PORT MAP(

digito, salida
);
end Behavioral;
library IEEE;
PORT (
clk : IN STD_LOGIC;
);

PORT (
);
END COMPONENT;
PORT (
);
END COMPONENT;
PORT (
clk : IN STD_LOGIC;
);
END COMPONENT;

begin
clk, reset, clk_out
);

);

digito, salida
);
end Behavioral; library IEEE;
PORT (
clk : IN STD_LOGIC;
);

PORT (
);
END COMPONENT;
PORT (
);
END COMPONENT;
PORT (
clk : IN STD_LOGIC;
);
END COMPONENT;

begin
clk, reset, clk_out
);

);

digito, salida
);
PORT (
clk : IN STD_LOGIC;
);

PORT (
);
END COMPONENT;
PORT (
);
END COMPONENT;
PORT (
clk : IN STD_LOGIC;
);
END COMPONENT;

begin
clk, reset, clk_out
);
);

digito, salida
);
PORT (
clk : IN STD_LOGIC;
);

PORT (
);
END COMPONENT;
PORT (
);
END COMPONENT;
PORT (
clk : IN STD_LOGIC;
);
END COMPONENT;

begin
clk, reset, clk_out
);

);

digito, salida
);
end Behavioral;
library IEEE;
PORT (
clk : IN STD_LOGIC;
);

PORT (
);
END COMPONENT;
PORT (
);
END COMPONENT;
PORT (
clk : IN STD_LOGIC;
);
END COMPONENT;

begin
clk, reset, clk_out
);

);

digito, salida
);
PORT (
clk : IN STD_LOGIC;
);

PORT (
);
END COMPONENT;
PORT (
);
END COMPONENT;
PORT (
clk : IN STD_LOGIC;
);
END COMPONENT;

begin
clk, reset, clk_out
);

);

digito, salida
);
end Behavioral;
library IEEE;
PORT (
clk : IN STD_LOGIC;
);

PORT (
);
END COMPONENT;
PORT (
);
END COMPONENT;
PORT (
clk : IN STD_LOGIC;
);
END COMPONENT;

begin
clk, reset, clk_out
);

);

digito, salida
);
PORT (
clk : IN STD_LOGIC;
);

PORT (
);
END COMPONENT;
PORT (
);
END COMPONENT;
PORT (
clk : IN STD_LOGIC;
);
END COMPONENT;

begin
clk, reset, clk_out
);

);

digito, salida
);
end Behavioral;
library IEEE;
entity siete_segmentos_mux is
PORT (
clk : IN STD_LOGIC;
D0 : IN STD_LOGIC_VECTOR(5 downto 0); --Primer d-gito.
D1 : IN STD_LOGIC_VECTOR(5 downto 0); --Segundo d-gito.
D2 : IN STD_LOGIC_VECTOR(5 downto 0); --Tercer d-gito.
D3 : IN STD_LOGIC_VECTOR(5 downto 0); --Cuarto d-gito.
salida: OUT STD_LOGIC_VECTOR(5 downto 0); --Salida del multiplexor (valor a desplegar).
MUX : OUT STD_LOGIC_VECTOR(3 downto 0) --Valor que define cual d-gito se va a mostrar.
);
end siete_segmentos_mux;
architecture Behavioral of siete_segmentos_mux is

type estados is (rst, v0, v1, v2, v3);
signal estado : estados;
begin
visualizadores: process (reset, clk) begin
if (reset = '1') then
estado <= rst;
MUX <= x"F";
salida <= "111111";
elsif rising_edge(clk) then
case estado is
when v0 =>
salida <= D3;
MUX <= "1110";
estado <= v1;
when v1 =>
salida <= D2;
MUX <= "1101";
estado <= v2;
when v2 =>
salida <= D1;
MUX <= "1011";
estado <= v3;
when others =>
salida <= D0;
MUX <= "0111";
estado <= v0;
end case;
end if;
end process;
end Behavioral;

Examen VHDL Codigo

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Examen VHDL Codigo

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library IEEE;

architecture Behavioral of contador_reloj is

architecture Behavioral of clk1Hz is

salida <= temporal;

architecture Behavioral of reloj is

signal clk_out : STD_LOGIC := '0';

--Padding de las seales del contador para siete segmentos.

architecture Behavioral of siete_segmentos is

architecture Behavioral of siete_segmentos_completo is

signal clk_out : STD_LOGIC := '0';

mux_i: siete_segmentos_mux PORT MAP(

seg_i: siete_segmentos PORT MAP(

architecture Behavioral of siete_segmentos_completo is

signal clk_out : STD_LOGIC := '0';

mux_i: siete_segmentos_mux PORT MAP(

seg_i: siete_segmentos PORT MAP(

architecture Behavioral of siete_segmentos_completo is

signal clk_out : STD_LOGIC := '0';

mux_i: siete_segmentos_mux PORT MAP(

seg_i: siete_segmentos PORT MAP(

architecture Behavioral of siete_segmentos_completo is

signal clk_out : STD_LOGIC := '0';

seg_i: siete_segmentos PORT MAP(

architecture Behavioral of siete_segmentos_completo is

signal clk_out : STD_LOGIC := '0';

mux_i: siete_segmentos_mux PORT MAP(

seg_i: siete_segmentos PORT MAP(

architecture Behavioral of siete_segmentos_completo is

signal clk_out : STD_LOGIC := '0';

mux_i: siete_segmentos_mux PORT MAP(

seg_i: siete_segmentos PORT MAP(

architecture Behavioral of siete_segmentos_completo is

signal clk_out : STD_LOGIC := '0';

mux_i: siete_segmentos_mux PORT MAP(

seg_i: siete_segmentos PORT MAP(

architecture Behavioral of siete_segmentos_completo is

signal clk_out : STD_LOGIC := '0';

mux_i: siete_segmentos_mux PORT MAP(

seg_i: siete_segmentos PORT MAP(

architecture Behavioral of siete_segmentos_completo is

signal clk_out : STD_LOGIC := '0';

mux_i: siete_segmentos_mux PORT MAP(

seg_i: siete_segmentos PORT MAP(

architecture Behavioral of siete_segmentos_mux is

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