VLSI LAB 2

RIPPLE CARRY ADDER

(c) Author: Sandeep Konam

Portfolio: http://sandeepkonam.com
Email Id: sandeepkonam2020@gmail.com
VLSI LAB 2 RIPPLE CARRY ADDER

AIM:

To program and simulate the Ripple Carry Adder in ISE Design Suite and observe its
behavioral graph.

RIPPLE CARRY ADDER THEORY:

A ripple carry adder is one in which the carry output of each full-adder is connected to
the carry input of the next higher-order stage. The sum and the output carry of any stage
cannot be produced until the input carry occurs; this causes a time delay in the addition
process. The carry propagation delay for each full-adder is the time from the application of the
input carry until the output carry occurs, assuming that the A and B input are already present.

A2 B2 A1 B1 A0 B0 Cin
A3 B3

FA4 FA3 FA2 FA1

Cout C3 C2 C1

S3 S2 S1 S0

Circuit Diagram of Ripple Carry Adder

FA = Full Adder

Working Principle of Ripple Carry Adder

A = A3A2A1A0

B = B3B2B1B0

SUM = A + B = CoutS3S2S1S0

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VLSI LAB 2 RIPPLE CARRY ADDER

PROGRAM:

module RA(input [3:0]a,b,input cin,output [3:0]sum,output cout);

wire [2:0]w;

FA R1(sum[0],w[0],a[0],b[0],cin);

FA R2(sum[1],w[1],a[1],b[1],w[0]);

FA R3(sum[2],w[2],a[2],b[2],w[1]);

FA R4(sum[3],cout,a[3],b[3],w[2]);

endmodule

module FA(output sum,cout,input a,b,cin);

wire w1,w2,w3;

and (w2,a,b);

xor (w1,a,b);

xor (sum,w1,cin);

and (w3,w1,cin);

or (cout,w2,w3);

endmodule

TEST BENCH:

module test;

reg [3:0] a;
reg [3:0] b;
reg cin;
wire [3:0] sum;
wire cout;
RA uut (.a(a), .b(b), .cin(cin), .sum(sum),.cout(cout));
initial
begin
a = 4;
b = 5;
cin = 0;
end
endmodule

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VLSI LAB 2 RIPPLE CARRY ADDER

RTL SCHEMATIC:

SIMULATION:

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VLSI LAB 2 RIPPLE CARRY ADDER

RESULT:
Ripple Carry Adder is programmed and simulated in the ISE Design Suite and observed
its behavioral graph.