Bootstrapping the Daughter

Board FPGA

Summary This application note describes the process of booting the

Daughter Board FPGA, at power-up, with a design stored in
Application Note
dedicated, on-board Flash Memory.
AP0100 (v1.1) May 25, 2005

The NanoBoard provides the ability to bootstrap the FPGA device located on the currently inserted
Daughter Board, at power-up. Program download to the FPGA is carried out using dedicated Flash
RAM.

Using Flash Memory to program the physical device

An 8MBit Flash RAM device (M25P80) is used to store the programming file required for implementing
the design within the FPGA. This device is component U6 on the parent NanoBoard.
The Flash RAM is controlled by the NanoBoard Controller – a Xilinx Spartan 100 FPGA.

Running the Flash Memory Controller

The procedure for loading the FPGA programming file into the Flash RAM
can be carried out at any time – with or without an FPGA project open and
irrespective of whether a design has currently been programmed into the
target FPGA device (on the Daughter Board).
From the Devices view, simply double-click on the icon for the NanoBoard
Figure 1. NanoBoard
Controller whose associated FPGA Boot Flash RAM you wish to load. The
Controller icon
Instrument Rack for the NanoBoard Controllers will appear as shown in
Figure 2.

Figure 2. NanoBoard Controllers Instrument Rack

Note: If you have multiple NanoBoards daisy-chained together, the NanoBoard Controller chain will
reflect each detected (powered-up) board. Each NanoBoard Controller in the chain will only appear in
the Instrument Rack after its corresponding icon has been specifically double-clicked.

AP0100 (v1.1) May 25, 2005 1

Bootstrapping the Daughter Board FPGA

On the instrument panel of the required NanoBoard Controller, click on the FPGA Boot button. The
Flash RAM Controller For FPGA Boot dialog will appear (Figure 3).
From this dialog, press the Read Electronic Signature button. This tests the communications link
between the NanoBoard Controller and the Flash RAM device. If communications are successful, a
value will be entered into the field to the immediate right of the button and the confirmatory message
“Device Found: M25P80 (8M-Bit Serial Flash RAM)” will be displayed.

Figure 3. Flash Memory Controller for FPGA Boot dialog

Erasing the Flash Memory

Before loading the required programming file into the Flash RAM device, the memory must first be
cleared. To erase the entire 8MBit of flash memory, press the Erase Entire Device button in the Flash
RAM Controller for FPGA Boot dialog. The erasing process will take approximately 5 seconds.

Programming the Flash Memory

Once the Flash RAM has been erased, the programming file can now be downloaded. From the Flash
RAM Controller for FPGA Boot dialog, press the … button (located at the top-right of the dialog). The
Choose FPGA Programming File for Download dialog appears. This dialog allows you to browse for
and open the required programming file. The programming file for a specific target FPGA device can
be found in the corresponding \Out\ConfigurationName subfolder and is either Altera-based
(*.rbf) or Xilinx-based (*.bit).
Note: When using Xilinx FPGA devices, the programming file used will be different for JTAG
programming and Slave-Serial programming. The Flash RAM uses the latter when loading the FPGA
device on the Daughter Board. Therefore, when choosing the programming file, the version of the file
with the _cclk.bit extension should be used (instead of the file with the .bit extension).
After choosing the file and clicking Open, you will be returned to the Flash RAM Controller for FPGA
Boot dialog. The chosen file (including path) will be displayed. To download this file to the Flash RAM,
simply click the Save File To Flash button.

2 AP0100 (v1.1) May 25, 2005

 Bootstrapping the Daughter Board FPGA

The download process will proceed, with progress shown in Altium Designer's Status bar. At the end of
the download, which takes approximately 15-20 seconds for a Xilinx Spartan IIE-300 device, an
information dialog will appear confirming the end of the process.

Verification of download to Flash Memory

After you have downloaded the FPGA programming file to the Flash RAM device, a check should be
made to ensure the integrity of the programming file. To do this, from the Flash RAM Controller for
FPGA Boot dialog, click on the Verify against File button.
The contents of the Flash RAM are read back and compared against the original programming file. The
progress for this process is again shown in Altium Designer's Status bar and, for a Xilinx Spartan IIE-
300 device, typically takes around 15-20 seconds to complete.
An information dialog will appear with details of the verification results. If the download process is
shown to have failed, the verification will report an error count. A large number of errors typically
indicates that the Flash RAM device was not successfully erased prior to download of the programming
file. In this case, try erasing the device again – using the Erase Entire Device button – and then using
the Blank Check button (in the same dialog) to verify that the device's memory has indeed been
successfully erased. The programming file can then be downloaded again.

Booting the FPGA using the Flash RAM

Once the Flash RAM has been successfully programmed with the required FPGA programming file, the
FPGA device on the Daughter Board can now be booted directly from the Flash RAM.
Firstly, turn off the NanoBoard. Then insert a jumper at position JP2 - AUTO LOAD FPGA on the
NanoBoard (the left-most jumper in the sequence of jumpers located below the VGA interface).
When the NanoBoard is powered-up, the FPGA on the Daughter Board will be programmed using the
file resident in the Flash RAM and the design will start running. Depending on the FPGA device used,
this startup process can take between 0.2 – 1.0 seconds

AP0100 (v1.1) May 25, 2005 3

Bootstrapping the Daughter Board FPGA

Revision History

Date Version No. Revision

20-Jan-2004 1.0 New product release

25-May-2005 1.1 Updated for Altium Designer SP4

Software, hardware, documentation and related materials:

Copyright © 2005 Altium Limited.
All rights reserved. You are permitted to print this document provided that (1) the use of such is for personal use
only and will not be copied or posted on any network computer or broadcast in any media and (2) no modifications
of the document is made. Unauthorized duplication, in whole or part, of this document by any means, mechanical or
electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited
without the express written permission of Altium Limited. Unauthorized duplication of this work may also be
prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or
imprisonment. Altium, Altium Designer, CAMtastic, Design Explorer, DXP, LiveDesign, NanoBoard, Nexar, nVisage,
P-CAD, Protel, Situs, TASKING and Topological Autorouting and their respective logos are trademarks or registered
trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein
are the property of their respective owners and no trademark rights to the same are claimed.

4 AP0100 (v1.1) May 25, 2005