9/5/13 VHDL hexadecimal instead of binary

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VHDL hexadecimal instead of binary

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VHDL hexadecimal instead of binary

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02-03-12, 21:25 #1

shaiko
VHDL hexadecimal instead of binary
Advanced Member level 4
PHP Code:
process is
Join Date: Aug 2011
begin
Posts: 1,035 case address_i is
Helped: 110 / 110 when "0100" =>
Points: 4,832
--- do something
when "0101" =>
Level: 16 --- do something else
when others =>
--- do something else
end case ;
end process ;

address_i is defined as an unsigned ( 3 downto 0 ).

instead of writing the long binary address I want to write it in Hex.
x"4" instead of "0100"
x"5" instead of "0101"
What is the correct way to do it ?

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02-03-12, 21:25

02-03-12, 23:01 #2

lucbra
Re: VHDL hexadecimal instead of binary
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9/5/13 VHDL hexadecimal instead of binary
Advanced Member level 1
like you wrote it: x"4" for an address range from 0 to 15 (0 -> F),
x"FF" for an address range of 0 to FF (255).
Achievements: If you want you can use a separator between bytes, like:
x"C0_FF_EE", which is identical to x"C0FFEE".
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Location: Belgium 1 members found this post helpful.
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02-03-12, 23:22 #3

shaiko
Re: VHDL hexadecimal instead of binary
Advanced Member level 4
There's a problem here.
actually "0100" is just an example.
Join Date: Aug 2011 The real address bus I'm dealing with is 15 bits wide ( wich isn't a
Posts: 1,035 multiple of 4 ).
Helped: 110 / 110
Points: 4,832
Level: 16

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02-03-12, 23:22

03-03-12, 09:20 #4

TrickyDicky
Re: VHDL hexadecimal instead of binary
Advanced Member level 5
you could concatenate 3 bits with 3 hex digits.

Join Date: Jun 2010

Code:
Posts: 3,699
Helped: 992 / 992
case addr is
when "000" & x"ABC" =>
Points: 19,001 -- do something
Level: 33

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03-03-12, 09:20

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9/5/13 VHDL hexadecimal instead of binary

03-03-12, 10:25 #5

std_match
Re: VHDL hexadecimal instead of binary
Full Member level 6
I think it is better to do a concatenation in the case expression:

Join Date: Jul 2010

Code:
Location: Sweden
Posts: 398
case '0' & addr is
when x"7890" => do_something
Helped: 155 / 155
Points: 2,848
Level: 12

If you then use a constant higher than x"7FFF" it can never be

true. The highest bit must be '0'.

It compiles correctly, but Modelsim gives the following warning

about the "case '0' & addr":
"Array type case expression must be of a locally static subtype."
I don't really understand this warning. You can ignore it, or avoid it
like this:

Code:
variable tmp_addr: std_logic_vector(15 downto 0);
begin
tmp_addr := '0' & addr;
case tmp_addr is
when x"7890" => do_something

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03-03-12, 22:00 #6

lucbra
Re: VHDL hexadecimal instead of binary
Advanced Member level 1
I would concatenate before the case using a variable like
std_match did
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04-03-12, 00:02 #7

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9/5/13 VHDL hexadecimal instead of binary

K-J Re: VHDL hexadecimal instead of binary

Full Member level 5
Originally Posted by shaiko
Join Date: Jan 2012 There's a problem here.
Posts: 299 actually "0100" is just an example.
Helped: 122 / 122 The real address bus I'm dealing with is 15 bits wide ( wich isn't
Points: 2,072 a multiple of 4 ).
Level: 10

Declare an integer variable of the proper range, convert the vector

to the integer and then use the integer as the case expression

Code:
variable address_integer: natural range 0 to 2**15 - 1
;
...
address_integer := to_integer(address_i)
case address_integer is
when 16#0004# =>
when 16#1234# =>
when 16#2BCD# =>
when 16#7FFF# =>
when others =>
end case;

Kevin Jennings

Last edited by K-J; 04-03-12 at 00:45.

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04-03-12, 00:22 #8

shaiko
Re: VHDL hexadecimal instead of binary
Advanced Member level 4
K-J,
Is writing 16#7FFF# and x"7FFF" is the same ?
Join Date: Aug 2011
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04-03-12, 00:44 #9

K-J
Re: VHDL hexadecimal instead of binary
Full Member level 5

Originally Posted by shaiko

Join Date: Jan 2012 K-J,
Posts: 299 Is writing 16#7FFF# and x"7FFF" is the same ?
Helped: 122 / 122
Points: 2,072
Level: 10 No (but kind of close depending on what you mean by 'same'). In
the context that you're using it here, x"7FFF" is an unsigned vector
(i.e. the type of 'address_i'), whereas 16#7FFF# is an integer
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9/5/13 VHDL hexadecimal instead of binary
constant. VHDL allows you to specify integer literals with a base by
using the # wrapper. The number before the first # sign indicates
the base. The base must be between 2 and 16, so each of these
are valid

123 -- Base 10 implied

10#123# -- Base 10 explicitly specified
16#ABCD# -- Hexadecimal
8#777# -- Octal
5#1234321# -- Base 5

Note that since you're specifying an integer value rather than bits
within a collection, you're not hamstrung by having to have the
right collection of bits as you are currently having with your posted
problem which has 15 bits which isn't a multiple of 4 which means
you have to kludge together the last three bits somehow.

So even though 16#1234# appears to be 4 digit hex number, it

does not have a 'vector' number of bits associated with it so it is
not '16 bits' wide. It is simply a constant integer. That means
though that you can't assign 16#7FFF# to an unsigned, nor can
you assign x"7FFF" to an integer.

my_unsigned <= 16#7FFF# -- Illegal, the right hand side is integer,

the left is unsigned
my_unsigned <= to_unsigned(16#7FFF#, my_unsigned'length); --
Legal

my_integer <= x"7FFF"; -- Illegal, the right hand side is unsigned

(actually ambigous, could be a string), the left is integer
my_integer <= to_integer(unsigned'(x"7FFF")); -- Legal

Kevin Jennings

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04-03-12, 00:54 #10

std_match
Re: VHDL hexadecimal instead of binary
Full Member level 6

Originally Posted by shaiko

Join Date: Jul 2010 K-J,
Location: Sweden Is writing 16#7FFF# and x"7FFF" is the same ?
Posts: 398
Helped: 155 / 155
Points: 2,848 No.
Level: 12 16#7FFF# is a number and the maximum value than can be written
in this way is (normally) 16#7FFFFFFF#.
This means that it can only be used to handle
unsigned/std_logic_vector with a size up to 31 bits.

x"7FFF" is not a number. It corresponds directly to

unsigned/std_logic_vector, and can be used for any size that is a
multiple of 4.

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05-03-12, 08:44 #11

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9/5/13 VHDL hexadecimal instead of binary

TrickyDicky
Re: VHDL hexadecimal instead of binary
Advanced Member level 5
just as a note, VHDL2008 has some string literal enhancements:

Join Date: Jun 2010

Code:
Posts: 3,699
Helped: 992 / 992
variable S : std_logic_vector(5 downto 0);
Points: 19,001 S := 6x"0f"; -- specify width 6
Level: 33 S := 6x"XF"; -- means "XX1111"
S := 6SX"F"; -- "111111" (sign extension)
S := 6Ux"f"; -- "001111" (zero extension)
S := 6sb"11"; -- "111111" (binary format)
S := 6uO"7"; -- "000111" (octal format)

copied from
http://www.doulos.com/knowhow/vhdl_d...ease/#bistring

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