Introduction

• Clock inaccuracy = jitter + skew

• Jitter : the inherent clock inaccuracy in the clock
generation circuitry
• Skew : the clock inaccuracy introduced by the
distribution system
Logic Clock

Logic Output (Evaluate State) (Precharged State)

Actual
Latch Clock
Expected
 Clocking Generation
• PLL (Phase Locked Loops) based designs
• Off-chip based designs
• DLL (Delay Locked Loops)
• Phase splitters
• Clock chopping
 PLL
• Usage : multiply an external reference clock to produce or
synthesize the on chip clock
• Typically the internal chip clock operates at a multiple of
the reference clock and the IO circuits operate at or near
frequency of the reference clock
• Problems
– analog circuits : sensitive to noise
– more advanced technologies, more difficult to design noise
insensitive
– inaccuracy because of process parameters
 Off-Chip Oscillator
• Alternatives to a PLL
• rely on board-level synchronization
– no on-chip circuitry(such as a PLL)
• high frequency oscillators are very stable and have
low jitter
• synchronization of the component chips to the
system board, which can be more expensive and
difficult
 DLL
• Usage
– to correct for the latency of the clock
distribution
– to set the phase of the bus clock relative to the
internal chip clock
• easier to design and analyze compared to a
PLL
• designed using state machines
 Phase Splitters
• Take a single clock phase as an input and
generate two separate phase as outputs
• A key building block for two phase design
styles
• should be tuned to eliminate mid-cycle
clock skew(skew from master to slave
latches)
 Clock Distribution
• Water-Main
Skew=125ps
Skew=80ps
Skew=45ps
Skew=20ps
Skew=5ps
Skew=0ps
Clock Output

– the name arise from the fact that a large “pipe” feeds the clock to
the entire chip
– the clock skew in a water-main system follows a contour across the
chip based on the distance from the feed
– Advantage : low horizontal skew
• H-tree
– “H-tree” arises from the nature
of the clock buffer placement
and wiring
– Buffers can be placed at the end Clock
Generator
of the “H” pattern
– the wire must be extensively
tuned based on the load at each
buffering stage : quite difficult
– the drivers at each point in the
clock tree are not uniform
– the various branches yield a
unique situation to the clock
skew problem
• Grids
– try to solve the routing problem
caused by the water-main
technique by creating more
points for connection like the H-
tree system
– this scheme may tie the output
for one or more intermediate
buffering levels together to
reduce the clock skew
– Due to the increase in the
average distance to the return
current path when the reference
planes are removed, the
inductance increase, and the
transmission-line effects such as
plateaus and reflections become
more pronounced, increasing the
clock skew
• Length-Matched Serpentines
– virtually zero skew for identical loads, as long as coupling and
uncontrolled variables are insignificant
– this topolgy is relatively simple to design, and like symmetric trees,
has virtually zero skew for identical loads, as long as coupling and
uncontrolled variables are insignificant
 Single Phase Clocking
• Single Phase Clock Diagram

Clock Input

Clock Output

Distribution System Delay

• Single-Phase Master-Slave Design
Single-clock Single-clock
Static Static
Master-Slave Master-Slave
Logic Logic
Flip-Flop Flip-Flop

Clock

• Single Phase Separated Latch Design

Positive level Positive level

Dynamic or Dynamic or
storage storage
Static Logic Static Logic
element element

Clock
 Single Phase Separated Latch
• Clock Activates Logic and Opens Subsequent
Latch
Positive level Negative level Negative level Positive level
storage dynamic or static storage dynamic or static
element logic element logic

Clock

• Clock Opens Latch and Activates Subsequence

Logic
Positive level Positive level Negative level Negative level
storage dynamic or static storage dynamic or static
element logic element logic

Clock
 Single Phase Separated Latch
• Advantage
– simple clocking structure
– good flush-through prevention
• Disadvantage
– limited storage element styles
– potentially limited logic styles
– complex interconnection requirements
– poor clock skew tolerance
Single Phase Continuously Latching
• Stores data at every circuit using alternating nmos/pmos
dynamic logic
• Advantage
– simple clocking structure
– good flush-through prevention
• Disadvantage
– limited latch/logic style
– complex interconnection requirement
– poor clock skew tolerance
– performance limited to achievable clock speed
 Multi-Phase Clocking
• Should be done locally at the end of the tree
• reduces skew, wire, power and noise
• Two phase clocking
– high rate of acceptance in the industry
– overlapped two-phase clocking helps to prevent
delay penalties, but exacerbates flush-through
• four phase clocking