I am a beginner in SystemC programming and there is one thing I noticed (looking in

the SystemC official documentation): all types that I used to deal with in vhdl
simulations have not been "ported" to SystemC.

I mean:

Consider std_logic in the vhdl standard library, there is not an equivalent in

SystemC, however, in the sysc documentation, I see many examples using bool.
Consider std_logic_vector, I see no equivalent in sysc. Instead I can see, in many
examples, usage of sc_int.
So I'm thinking that SystemC does not provide types in order to manage single bits
or electric signals, but it provides a higher abstraction like in every common C/C+
+ applications.

Is it so or am I missing something?

c++ c vhdl systemc

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edited Apr 5 '11 at 11:40

HaskellElephant
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asked Apr 5 '11 at 11:27

Andry
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2 Answers
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Consider std_logic in the vhdl standard library, there is not an equivalent in
SystemC, however, in the sysc documentation, I see many examples using bool.
Consider std_logic_vector, I see no equivalent in sysc. Instead I can see, in many
examples, usage of sc_int.
It's not all that correct.

In SystemC you can use sc_logic and sc_lv< T > as std_logic and std_logic_vector
respectively.

You can assign to SC_LOGIC_0 or SC_LOGIC_1 literals to sc_logic.

While you can use integer, hex or even 'bit-specific' literal to assign sc_lv< T >
a value.

For example:

class some_device : sc_module

{
sc_out< sc_lv<32> > address;
sc_out< sc_logic > write_enable;

SC_CTOR (some_device)
{
write_enable.initialize(SC_LOGIC_0);

/* The following three lines do the same thing.

 * Obviously you won't use all three at the same time... */
address.initialize(0b00001111000011110000111100001111);
address.initialize(0x0F0F0F0F);
address.iniziatize(252645135);
}
}