M.

Tech VLSI 2017-2018

S.No PROJECT NAME Design IEEE
A Bit-Plane Decomposition Matrix-Based VLSI Integer
1 Front End 2017
Transform Architecture for HEVC
Probability-Driven Multibit Flip-Flop Integration With Clock
2 Front End 2017
Gating
Area-Time Efficient Architecture of FFT-Based Montgomery
3 Front End 2017
Multiplication
Reliable Low-Latency Viterbi Algorithm Architectures
4 Front End 2017
Benchmarked on ASIC and FPGA
Improved 64-bit Radix-16 Booth Multiplier Based on Partial
5 Front End 2017
Product Array Height Reduction
A Structured Visual Approach to GALS Modeling and
6 Front End 2017
Verification of Communication Circuits
Weighted Partitioning for Fast Multiplierless Multiple-
7 Front End 2017
Constant Convolution Circuit
Low-Latency, Low-Area, and Scalable Systolic-Like Modular
8 Multipliers for GF(2m) Based on Irreducible All-One Front End 2017
Polynomials
9 Probabilistic Error Modeling for Approximate Adders Front End 2017
10 LFSR-Based Generation of Multicycle Tests Front End 2017
Clock-Gating of Streaming Applications for Energy Efficient
11 Front End 2017
Implementations on FPGAs
An Improved DCM-Based Tunable True Random Number
12 Front End 2017
Generator for Xilinx FPGA
RoBA Multiplier: A Rounding-Based Approximate Multiplier
13 Front End 2017
for High-Speed yet Energy-Efficient Digital Signal Processing
14 DLAU: A Scalable Deep Learning Accelerator Unit on FPGA Front End 2017
15 A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices Front End 2017
Design of Efficient Multiplierless Modified Cosine-Based Comb
16 Front End 2017
Decimation Filters: Analysis and Implementation
Efficient Hardware Implementation of Probabilistic Gradient
17 Front End 2017
Descent Bit-Flipping
Design of Efficient BCD Adders in Quantum-Dot Cellular
18 Front End 2017
Automata
19 Overloaded CDMA Crossbar for Network-On-Chip Front End 2017
High-Throughput and Energy-Efficient Belief Propagation
20 Front End 2017
Polar Code Decoder
21 Design of Power and Area Efficient Approximate Multipliers Front End 2017
22 An Efficient O(N) Comparison-Free Sorting Algorithm Front End 2017
 Energy-Efficient VLSI Realization of Binary64 Division With
23 Front End 2017
Redundant Number Systems
A General Digit-Serial Architecture for Montgomery Modular
24 Front End 2017
Multiplication
High-Speed Parallel LFSR Architectures Based on Improved
25 Front End 2017
State-Space Transformations
Scalable Approach for Power Droop Reduction During Scan-
26 Front End 2017
Based Logic BIST
Sign-Magnitude Encoding for Efficient VLSI Realization of
27 Front End 2017
Decimal Multiplication
A Memory-Based FFT Processor Design With Generalized
28 Front End 2017
Efficient Conflict-Free Address Schemes.
29 On the VLSI Energy Complexity of LDPC Decoder Circuits Front End 2017
30 Reconfigurable Constant Multiplication for FPGAs Front End 2017
LLR-Based Successive-Cancellation List Decoder for Polar
31 Front End 2017
Codes With Multibit Decision
Area-Efficient Architecture for Dual-Mode Double Precision
32 Front End 2017
Floating Point Division
Digit-Level Serial-In Parallel-Out Multiplier Using Redundant
33 Front End 2017
Representation for a Class of Finite Fields.
Dual-Quality 4: 2 Compressors for Utilizing in Dynamic
34 Back End 2017
Accuracy Configurable Multipliers
Low-Power Design for a Digit-Serial Polynomial Basis Finite
35 Back End 2017
Field Multiplier Using Factoring Technique
Design of Low-Power High-Performance 2-4 and 4-16 Mixed-
36 Back End 2017
Logic Line Decoders.
37 Register-Less NULL Convention Logic. Back End 2017
Design of Defect and Fault-Tolerant Nonvolatile Spintronic
38 Back End 2017
Flip-Flops
Delay Analysis for Current Mode Threshold Logic Gate
39 Back End 2017
Designs
10T SRAM Using Half-VDD Precharge and Row-Wise
40 Dynamically Powered Read Port for Low Switching Power and Back End 2017
Ultralow RBL Leakage
Pre-Encoded Multipliers Based on Non-Redundant Radix-4
41 Front End 2016
Signed-Digit Encoding
Floating-Point Butterfly Architecture Based on Binary Signed-
42 Front End 2016
Digit Representation
Flexible DSP Accelerator Architecture Exploiting Carry-Save
43 Front End 2016
Arithmetic
A High-Performance FIR Filter Architecture for Fixed and
44 Front End 2016
Reconfigurable Applications
A Method to Design Single Error Correction Codes
45 Front End 2016
With Fast Decoding for a Subset of Critical Bits
46 On Efficient Retiming of Fixed-Point Circuits Front End 2016
47 Concept, Design, and Implementation of Reconfigurable Front End 2016
 CORDIC
Fault Tolerant Parallel FFTs Using Error Correction Codes
48 Front End 2016
and Parseval Checks
Low-Power Parallel Chien Search Architecture Using a Two-
49 Front End 2016
Step Approach
An Efficient Single and Double-Adjacent Error Correcting
50 Front End 2016
Parallel Decoder for the (24,12) Extended Golay Code
Memory-Reduced Turbo Decoding Architecture
51 Front End 2016
Using NII Metric Compression
Multiple Constant Multiplication Algorithm for High-Speed and
52 Front End 2016
Low-Power Design
53 Design and Analysis of Inexact Floating-Point Adders Front End 2016
A Mixed-Decimation MDF Architecture for Radix-2k Parallel
54 Front End 2016
FFT
A Modified Partial Product Generator for Redundant Binary
55 Front End 2016
Multipliers
A Cellular Network Architecture With Polynomial Weight
56 Front End 2016
Functions
A Normal I/O Order Radix-2 FFT Architecture to Process
57 Front End 2016
Twin Data Streams for MIMO
High Speed Hybrid Double Multiplication Architectures Using
58 Front End 2016
New Serial-Out Bit- Level Mastrovito Multipliers
Low-Cost High-Performance VLSI Architecture for
59 Front End 2016
Montgomery Modular Multiplication
A High-Speed FPGA Implementation of an RSD-Based ECC
60 Front End 2016
Processor
61 VLSI Design for Convolutive Blind Source Separation Front End 2016
High-Speed and Energy-Efficient Carry Skip Adder Operating
62 Front End 2016
Under a Wide Range of Supply Voltage Levels
Input-Based Dynamic Reconfiguration of Approximate
63 Front End 2016
Arithmetic Units for Video Encoding
Hardware and Energy-Efficient Stochastic LU Decomposition
64 Front End 2016
Scheme for MIMO Receivers
65 Hybrid LUT/Multiplexer FPGA Logic Architectures Front End 2016
High-Performance Pipelined Architecture of Elliptic Curve
66 Front End 2016
Scalar Multiplication Over GF(2m)
In-Field Test for Permanent Faults in FIFO Buffers of NOC
67 Front End 2016
Routers
Performance/Power Space Exploration for Binary64 Division
68 Front End 2016
Units
69 A High Throughput List Decoder Architecture for Polar Codes Front End 2016
A Novel Coding Scheme for Secure Communications in
70 Front End 2016
Distributed RFID Systems
Arithmetic algorithms for extended precision using floating
71 Front End 2016
point expansions
Digital Multiplierless Realization of Two-Coupled Biological
72 Front End 2016
HindmarshRose Neuron Model
 A Low Power Trainable Neuromorphic Integrated Circuit That
73 Back End 2016
Is Tolerant to Device Mismatch
A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-
74 Back End 2016
Power CMOS
A Low-Power Incremental DeltaSigma ADC for CMOS Image
75 Back End 2016
Sensors
Low-Power ASK Detector for Low Modulation Indexes and
76 Back End 2016
Rail-to-Rail Input Range
A Low-Power Robust Easily Cascaded PentaMTJ-Based
77 Back End 2016
Combinational and Sequential Circuits
PNS-FCR: Flexible Charge Recycling Dynamic Circuit
78 Back End 2016
Technique for Low-Power Microprocessors
Low-Power Variation-Tolerant Nonvolatile Lookup Table
79 Back End 2016
Design
Dual Use of Power Lines for Design-for-TestabilityA CMOS
80 Back End 2016
Receiver Design
One-Cycle Correction of Timing Errors in Pipelines With
81 Back End 2016
Standard Clocked Elements
Graph-Based Transistor Network Generation Method for
82 Back End 2016
Supergate Design
A Single-Ended With Dynamic Feedback Control 8T
83 Back End 2016
Subthreshold SRAM Cell
Full-Swing Local Bitline SRAM Architecture Based on the 22-
84 Back End 2016
nm FinFET Technology for Low-Voltage Operation
85 Design for Testability of Sleep Convention Logic Back End 2016
High - Throughput Finite Field Multipliers Using Redundant
86 Front End 2015
8Basis For FPGA And ASIC Implementations
A8 Generalized Algorithm And Reconfigurable Architecture For
87 Front End 2015
Efficient And Scalable Orthogonal Approximation Of DCT
Fully Reused VLSI Architecture Of Fm0/Manchester Encoding
88 Front End 2015
Using Sols Technique For DSRC Applications
89 Obfuscating DSP Circuits Via High-Level Transformations Front End 2015
Pre-Encoded Multipliers Based On Non-Redundant Radix-4
90 Front End 2015
Signed-Digit Encoding
Flexible DSP Accelerator Architecture Exploiting Carry-Save
91 Front End 2015
Arithmetic
Fault Tolerant Parallel Filters Based On Error Correction
92 Front End 2015
Codes
A Synergetic Use Of Bloom Filters For Error Detection And
93 Front End 2015
Correction
Reliable Low-Power Multiplier Design Using Fixed-Width
94 Front End 2015
Replica Redundancy Block
Recursive Approach To The Design Of A Parallel Self-Timed
95 Front End 2015
Adder
Aging-Aware Reliable Multiplier Design With Adaptive Hold
96 Front End 2015
Logic
97 Fine-Grained Critical Path Analysis And Optimization For Front End 2015
 Area-Time Efficient Realization Of Multiple Constant
Multiplications
Scan Test Bandwidth Management For Ultralarge-Scale
98 Front End 2015
System-On-Chip Architectures
Low-Power And Area-Efficient Shift Register Using Pulsed
99 Front End 2015
Latches
Low-Power Programmable PRPG With Test Compression
100 Front End 2015
Capabilities
One Minimum Only Trellis Decoder For Non Binary Low -
101 Front End 2015
Density Parity - Check Codes
A Low Complexity Scaling Method For The Lanczos Kernel In
102 Front End 2015
Fixed-Point Arithmetic
Low-Latency High-Throughput Systolic Multipliers Over
103 Front End 2015
GF(2m) For NIST Recommended Pentanomials
104 Efficient Coding Schemes For Fault-Tolerant Parallel Filters Front End 2015
105 Partially Parallel Encoder Architecture For Long Polar Codes Front End 2015
Novel Block-Formulation And Area-Delay - Efficient
106 Reconfigurable Interpolation Filter Architecture For multi - Front End 2015
Standard SDR Applications
Algorithm And Architecture For A Low-Power Content-
107 Back End 2015
Addressable Memory Based On Sparse Clustered Networks
A Self-Powered High-Efficiency Rectifier With Automatic
108 Resetting Of Transducer Capacitance In Piezoelectric Energy Back End 2015
Harvesting Systems
Mixing Drivers In Clock-Tree For Power Supply
109 Back End 2015
NoiseReduction
A Closed-Loop Reconfigurable Switched-Capacitor DC-DC
110 Back End 2015
Converter For Sub-mW Energy Harvesting Applications
An Optimized Modified Booth Recoder for Efficient Design of
111 Front End 2014
the Add-Multiply Operator
Data Encoding Techniques for Reducing Energy Consumption
112 Front End 2014
in Network-on-Chip
113 Fast Radix-10 Multiplication Using Redundant BCD Codes Front End 2014
A parallel radix-sort-based VLSI architecture for finding the
114 Front End 2014
first W maximum/minimum values
115 Multifunction Residue Architectures for Cryptography Front End 2014
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter
116 Front End 2014
With Low Adaptation-Delay
32 Bit32 Bit Multiprecision Razor-Based Dynamic Voltage
117 Front End 2014
Scaling Multiplier With Operands Scheduler
Recursive Approach to the Design of a Parallel Self-Timed
118 Front End 2014
Adder
Fully Reused VLSI Architecture of FM0/Manchester Encoding
119 Front End 2014
Using SOLS Technique for DSRC Applications
120 Bit-Level Optimization of Adder-Trees for Multiple Constant Front End 2014
 Multiplications for Efficient FIR Filter Implementation
121 Efficient Integer DCT Architectures for HEVC Front End 2014
Critical-Path Analysis and Low-Complexity Implementation of
122 Front End 2014
the LMS Adaptive Algorithm
123 A Method to Extend Orthogonal Latin Square Codes Front End 2014
Efficient FPGA and ASIC Realizations of a DA-Based
124 Front End 2014
Reconfigurable FIR Digital Filter
On the Systematic Creation of Faithfully Rounded Truncated
125 Front End 2014
Multipliers and Arrays
Low-Latency Successive-Cancellation Polar Decoder
126 Front End 2014
Architectures Using 2-Bit Decoding
Aging-Aware Reliable Multiplier Design With Adaptive Hold
127 Front End 2014
Logic
Low-Complexity Low-Latency Architecture for Matching of
128 Front End 2014
Data Encoded With Hard Systematic Error-Correcting Codes
129 AreaDelayPower Efficient Carry-Select Adder Front End 2014
Restoration-Based Procedures With Set Covering Heuristics for
130 Front End 2014
Static Test Compaction of Functional Test Sequences
Scalable Montgomery Modular Multiplication Architecture with
131 Front End 2014
Low-Latency and Low-Memory Bandwidth Requirement
Input Test Data Volume Reduction for Skewed-Load Tests by
132 Front End 2014
Additional Shifting of Scan-In States
Sharing Logic for Built-In Generation of Functional
133 Front End 2014
BroadsideTests
A Methodology for Optimized Design of Secure Differential
134 Back End 2014
Logic Gates for DPA Resistant Circuits
Design of Efficient Binary Comparators in Quantum-Dot
135 Back End 2014
Cellular Automata
Analysis and Design of a Low-Voltage Low-Power Double-Tail
136 Back End 2014
Comparator
Digitally Controlled Pulse Width Modulator for On-Chip Power
137 Back End 2014
Management
Statistical Analysis of MUX-Based Physical Unclonable
138 Back End 2014
Functions
Low-Power Pulse-Triggered Flip-Flop Design Based on a
139 Back End 2014
Signal Feed-Through Scheme
140 Area-Delay Efficient Binary Adders in QCA Back End 2014

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