Dr.N.G.P.

Institute of Technology Department ECE

Dr. N.G.P. INSTITUTE OF TECHNOLOGY

Coimbatore-641048

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

TWO MARKS WITH ANSWERS

EC6302 / DIGITAL ELECTRONICS

REGULATION: 2013

Prepared by
Ms.C.S.Manju, AP/ECE
Ms.S.Kalaivani, AP/ECE

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EC 6302 DIGITAL ELECTRONICS LT PC

3 003
OBJECTIVES:
To introduce basic postulates of Boolean algebra and shows the correlation between
Boolean expressions
To introduce the methods for simplifying Boolean expressions
To outline the formal procedures for the analysis and design of combinational circuits
and sequential circuits
To introduce the concept of memories and programmable logic devices.
To illustrate the concept of synchronous and asynchronous sequential circuits

UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES 9

Minimization Techniques: Boolean postulates and laws De-Morgans Theorem - Principle
of Duality - Boolean expression - Minimization of Boolean expressions Minterm Maxterm -
Sum of Products (SOP) Product of Sums (POS) Karnaugh map Minimization Dont care
conditions Quine - Mc Cluskey method of minimization. Logic Gates: AND, OR, NOT, NAND,
NOR, ExclusiveOR and ExclusiveNOR Implementations of Logic Functions using gates,
NANDNOR implementations Multi level gate implementations- Multi output gate
implementations. TTL and CMOS Logic and their characteristics Tristate gates

UNIT II COMBINATIONAL CIRCUITS 9

Design procedure Half adder Full Adder Half subtractor Full subtractor Parallel
binary adder, parallel binary Subtractor Fast Adder - Carry Look Ahead adder Serial Adder/
Subtractor - BCD adder Binary Multiplier Binary Divider - Multiplexer/Demultiplexer
decoder - encoder parity checker parity generators code converters - Magnitude Comparator.

UNIT III SEQUENTIAL CIRCUITS 9

Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation
Application table Edge triggering Level Triggering Realization of one flip flop using other flip
flops Serial adder/subtractor- Asynchronous Ripple or serial counter Asynchronous Up/Down
counter- Synchronous counters Synchronous Up/Down counters Programmable counters
Design of Synchronous counters: state diagram- State table State minimization State assignment -
Excitation table and maps-Circuit implementation - Modulon counter, Registers shift registers
Universal shift registers Shift register counters Ring counter Shift counters - Sequence
generators.

UNIT IV MEMORY DEVICES 9

Classification of memories ROM - ROM organization - PROM EPROM EEPROM
EAPROM, RAM RAM organization Write operation Read operation Memory cycle - Timing
wave forms Memory decoding memory expansion Static RAM Cell- Bipolar RAM cell
MOSFET RAM cell Dynamic RAM cell Programmable Logic Devices Programmable Logic
Array (PLA) - Programmable Array Logic (PAL) Field Programmable Gate Arrays (FPGA) -
Implementation of combinational logic circuits using ROM, PLA, PAL

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UNIT V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS 9

Synchronous Sequential Circuits: General Model Classification Design Use of
Algorithmic State Machine Analysis of Synchronous Sequential Circuits Asynchronous Sequential
Circuits: Design of fundamental mode and pulse mode circuits Incompletely specified State
Machines Problems in Asynchronous Circuits Design of Hazard Free Switching circuits. Design
of Combinational and Sequential circuits using VERILOG.

TOTAL: 45 PERIODS
OUTCOMES:
Students will be able to:
Analyze different methods used for simplification of Boolean expressions.
Design and implement Combinational circuits.
Design and implement synchronous and asynchronous sequential circuits.
Write simple HDL codes for the circuits.

TEXT BOOK:
1. M. Morris Mano, Digital Design, 4th Edition, Prentice Hall of India Pvt. Ltd., 2008 /
Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.

REFERENCES:

1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006

2. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2002.
3. Charles H.Roth. Fundamentals of Logic Design, Thomson Learning, 2003.
4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6th Edition,
TMH, 2003.
5. Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education Inc, New Delhi,
2003
6. Donald D.Givone, Digital Principles and Design, TMH, 2003

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UNIT I
MINIMIZATION TECHNIQUES AND LOGIC GATES
1. What is a Logic gate?
A logic gate is an elementary building block of a digital circuit. The electronic gate is a
circuit that is able to operate on a number of binary inputs in order to perform a particular logical
function.
2. Write the names of basic logical operators
The three basic logic gates are:
i) AND
ii) OR
iii) NOT/ INVERTOR.
3. Which gates are called as the universal gates? What are its advantages?
The NAND and NOR gates are called as the universal gates.
These gates are used to perform any type of logic application.
4. Define Digital Systems
Digital systems represent information using a binary system, where data can assume one of only
two possible values: zero or one.
A system which is processing discrete or digital signal is called as Digital System.
5. What is meant by bit and Radix
A binary digit is called bit.
Radix specifies the number of symbols used for corresponding number system. .
6. Define Nibble and Byte.
i). In binary number a group of four bits nibble.
ii). A group of 8 bits are called Byte.
7. List the number systems?
i) Decimal Number system
ii) Binary Number system
iii) Octal Number system
iv) Hexadecimal Number system

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8. Define binary logic?

Binary logic consists of binary variables and logical operations. The variables are designated by
the alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1
and 0. There are three basic logic operations: AND, OR, and NOT.
9. What are the applications of octal number system?
The applications of octal number system are:
i) It is used for entering the binary data and displaying certain informations.
ii) It is very important for the efficient use of microprocessors and other digital circuits.
10. Why is a hexadecimal number system called as an alpha numeric number system?
Hexadecimal number system has the base as 16 and therefore it requires 16 distinct symbols to
represent the numbers. These are numerals 0 to 9 and alphabets A to F. Since both numeric
digitals and alphabets are used to represent the digits in hexadecimal number system, it is also
called as an alphanumeric number system.
11. Define Boolean algebra & Boolean Expression.
Boolean Algebra is used to analyze and simplify the digital (logic) circuits. It uses only the
binary numbers i.e. 0 and 1. It is also called as Binary Algebra or logical Algebra.
The table used to represent the boolean expressionof a logic gate function is commonly called a
Truth Table. A logic gate truth table shows each possible input combination to
the gate or circuit with the resultant output depending upon the combination of these input(s)
12. What are basic properties of Boolean algebra?
The basic properties of Boolean algebra are
i) Commutative property
ii) Associative property
iii) Distributive property.
13. State the associative property of Boolean algebra.
The associative property of Boolean algebra states that the OR ing of several variables results in
the same regardless of the grouping of the variables. The associative property is stated as
follows:
i). A+ (B+C) = (A+B) +C ii). A (B C) = (A B) C
14. State the commutative property of Boolean algebra.
The commutative property states that the order in which the variables are OR ed makes no
difference. The commutative property is: i). A+B=B+A ii). A.B = B.A

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15. State the distributive property of Boolean algebra.

The distributive property states that AND ing several variables and OR ing the result with a
single variable is equivalent to OR ing the single variable with each of the the several variables
and then AND ing the sums. The distributive property is:
i). A+BC = (A+B) (A+C)
ii). A (B+C) = AB + AC
16. State De Morgan's theorem. (May/June 2013, Nov/Dec 2015)
De Morgan suggested two theorems that form important part of Boolean algebra.
They are,
1) The complement of a product is equal to the sum of the complements.
(A . B)' = A' + B'
2) The complement of a sum term is equal to the product of the complements.
(A + B)' = A'B'
17. What are the 2 forms of Boolean expression?
The two forms of Boolean expressions are:
i). Sum of Products Form
ii). Product of Sum Form
18. Define Minterm & Maxterm.
The products of Boolean expression where all possible variables appear once in complement or
uncomplement variables are called Minterm.
A sum terms in a Boolean expression where all possible variables appear once, in complement or
uncomplement form are called Maxterm.
19. What is meant by karnaugh map or K-Map method?
A karnaugh map or k map is a pictorial form of truth table, in which the map diagram is made up
of cells, with each cell representing one minterm or maxterm of the function. This method
provides a simple straight forward procedure for minimizing Boolean function.
20. Define Cell.
The smallest unit of a karnaugh map, corresponding to one rows of a truth table. The
input variables are the cells coordinates and the output variable is the cells contents.

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21. Define Pair, Quad, and Octet.

i). Pair: A group of two adjacent cells in a karnaugh map. A pair cancels one variable in a K-
Map simplification.
ii). Quad: A group of four adjacent cells in a karnaugh map. A quad cancels two variable in a K-
Map simplification.
iii). Octet: A group of eight adjacent cells in a karnaugh map. A pair cancels three variable in a
K-Map simplification.
22. What are called dont care conditions? (May/June 2013)
In some logic circuits certain input conditions never occur, therefore the corresponding output
never appears. In such cases the output level is not defined, it can be either high or low. These
output levels are indicated by X or d in the truth tables and are called dont care conditions or
incompletely specified functions.
23. What is tabulation method?
A method involving an exhaustive tabular search method for the minimum expression to solve a
Boolean equation for more variables is called as a tabulation method.
24. State the limitations of karnaugh map.
i) Generally it is limited to six variable map (i.e.) more then six variable involving expressions
are not reduced.
ii) The map method is restricted in its capability since they are useful for simplifying
only Boolean expression represented in standard form.
25. What is a prime implicant?
A prime implicant is a product term obtained by combining the maximum possible number of
adjacent squares in the map. They cannot be reduced further.
(Or)
A prime implicant is a group of minterms which cannot be combined with any other minterm or
groups.
26. What is an essential prime implicant?
The Essential Prime Implicant is a prime implicant in which one or more minterms are unique, it
contains at least one minterm which is not contained in any other prime implicant.
27. Explain or list out the advantages and disadvantages of K-map method?
The advantages of the K-map method are:
i). It is a fast method for simplifying expression up to four variables.

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ii). It gives a visual method of logic simplification.

iii). Prime implicants and essential prime implicants are identified fast.
iv). Suitable for both SOP and POS forms of reduction.
v). It is more suitable for class room teachings on logic simplification.
The disadvantages of the K-map method are:
i). It is not suitable for computer reduction.
ii). K-maps are not suitable when the number of variables involved exceed four.
iii). Care must be taken to fill in every cell with the relevant entry, such as a 0, 1 (or) dont care
terms.
28. List out the advantages and disadvantages of Quine-Mc Cluskey method?
The advantages are:
i). This is suitable when the number of variables exceed four.
ii). Digital computers can be used to obtain the solution fast.
iii). Essential prime implicants, which are not evident in K-map, can be clearly seen in
the final results.
The disadvantages are:
i). Lengthy procedure than K-map.
ii). Requires several grouping and steps as compared to K-map.
iii). It is much slower.
iv). No visual identification of reduction process.
v). The Quine Mc Cluskey method is essentially a computer reduction method.
29. Define Duality Theorem. (May/June 2012)
The Duality theorem states that starting with a Boolean relation we can derive
another Boolean relation by:
i). Changing OR (operation) i.e., + (Plus) sign to an AND (operation) i.e., (dot) and Vice-versa.
ii). Complement any 0 or 1 appearing in the expression i.e., replacing contains 0 and 1
by 1 and 0 respectively.

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30. List the characteristics of digital ICs

i) Propagation delay
ii) Power dissipation
iii) Fan-in
iv) Fan-out
v) Noise margin
31. What is propagation delay?
It is defined as the time taken for the output of a gate to change after the inputs have changed.
Propagation delay times are defined as follows:
- It is the propagation delay time in going from low level (0) to high level (1).
- It is the propagation delay time in going from High level (1) to high level (0).
Propagation delay - Propagation delay -
32. What is power dissipation?
The electrical energy used by logic circuits in specified period of time. (Expresses in milliwatts
or nanowatts).
Power dissipation = Supply voltage * meant current taken from that supply.
33. Define Fan-in & Fan-out.
Fan-in: The fan-in of a gate is the number of inputs connected to the gate without any
Degradation in the voltage levels.
Fan-out: It is defined as the maximum number of inputs of the same IC family that a gate can
drive maintaining its output levels within the specified limits.
34. What is Noise margin? (May/June 2016)
Noise margin is the maximum external noise voltage added to an input signal that
does not cause an undesirable change in the circuit output.
35. Define Figure of Merit (SPP).
Figure of merit is defined as the product of speed and power. The speed is specified in terms of
propagation delay time expressed in nano seconds.
Figure of merit = Propagation delay time (ns) * Power (mW).

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36. Define Noise Immunity.

The ability of a logic circuit to tolerate the noise without causing any unwanted changes in the
output.
37. Mention the characteristics of MOS transistor?
1. The n- channel MOS conducts when its gate- to- source voltage is positive.
2. The p- channel MOS conducts when its gate- to- source voltage is negative
3. Either type of device is turned off if its gate- to- source voltage is zero.
38. Why totem pole outputs cannot be connected together. (Nov/Dec 2016)
Totem pole outputs cannot be connected together because such a connection might produce
excessive current and may result in damage to the devices.
39. What are the types of TTL logic?
i) Open collector output
ii) Totem-Pole Output
iii) Tri-state output.
40. State advantages and disadvantages of TTL
Advantages:
i) Easily compatible with other ICs
ii) Low output impedance
Disadvantages:
i) Wired output capability is possible only with tristate and open collector types
ii) Special circuits in Circuit layout and system design are required.
41. What happens to output when a tristate circuit is selected for high impedance.
Output is disconnected from rest of the circuits by internal circuitry.
42. What is Operating temperature?
All the gates or semiconductor devices are temperature sensitive in nature. The temperature in
which the performance of the IC is effective is called as operating temperature. Operating
temperature of the IC vary from 0C to 70C.
43. What is High Threshold Logic?
Some digital circuits operate in environments, which produce very high noise signals. For
operation in such surroundings there is available a type of DTL gate which possesses a high
threshold to noise immunity. This type of gate is called HTL logic or High Threshold Logic.

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44. Apply De-Morgans Theorem to (May/Jun 2014)

45.What are the basic Laws of Boolean Algebra. (Nov/Dec 2013)

i) Boolean Addition
ii) Boolean Multiplication
iii) Properties of Boolean Algebra
iv) Principle of Dualtity.
46. What are the methods adopted to reduce Boolean function.
i) Karnaug map
ii) Tabular method or QuineMc-Cluskey method
iii) Variable entered map technique.

47. Simplify the following using De Morgan's theorem [((AB)'C)'' D]'

[((AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)' = A' + B']
= (AB)' C + D'
= (A' + B' )C + D'

48. Simplify the following Boolean expression (Nov/Dec 2014)

= =

49. Simplify the given Boolean expression F= x+xy+xz+xyz (Nov/Dec 2012)

F= x+ xy+ xz+ xyz
= x+ x[ y+ z+ yz]
= x+ x [y+ z(1+y) ] = x + x (y + z) = (x + y + z)
50. Implement the given function using NAND gates f(x,y,z)= (Nov/Dec 2012)

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51. Find the complement of F= wx+yz and show that F.F=0 .(Apr/May 2011)

F.F= ==

= = 0

52. Convert (AB+C)(B+CD) into SUM OF PRODUCTS form . (Apr/May 2011)

(AB+C)(B+CD) =AB+ABCD+BC= AB(C+C)(D+D)+ABCD+BC(A+A)(D+D)

53. Show that positive logic NAND gate is Negative NOR logic. (Apr/May 2011)

54. State the advantages of CMOS logic. (Apr/May 2015)

1. High input impedance.
2. The outputs actively drive both ways
3. The outputs are pretty much rail-to-rail
4. It has good speed to power ratio compared to other logic types.

55. Convert Y= A+BC+AB+ABC into canonical form. (Apr/May 2015)

Y= A+BC+AB+ABC
= A (B + B) (C + C) + BC (A + A) + AB (C + C) + ABC
= ABC + ABC + ABC +ABC + ABC + ABC + ABC
= ABC + ABC + ABC +ABC + ABC + ABC

56. Express the function Y = A + BC in canonical POS (Nov/Dec 2015 )

Y = A + BC
= A (B+B) (C+C) + BC (A+A)
= ABC + ABC + ABC + ABC +ABC + ABC
= ABC + ABC + ABC + ABC + ABC

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= m4 + m5 + m6 + m7 + m1
= m(1, 4, 5, 6, 7)
=M(0, 2, 3)
= (A + B + C) (A + B + C) (A + B + C)

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UNIT II
COMBINATIONAL CIRCUITS
1. Define combinational logic.
When logic gates are connected together to produce a specified output for certain specified
combinations of input variables, with no storage involved, the resulting circuit is called
combinational logic.
2. Explain the design procedure for combinational circuits. (May/June 2016, Nov/Dec 2016)
1. The problem definition
2. Determine the number of available input variables & required O/P variables.
3. Truth Table Construction
4. Obtain simplified Boolean expression for each O/P (using K-Map).
5. Obtain the logic diagram.
3. Define Half adder and full adder (Nov/Dec 2015)
Half Adder: The logic circuit that performs the addition of two bits is a half adder.
Full Adder: The circuit that performs the addition of three bits is a full adder.
4. Define Decoder?
A decoder is a multiple - input multiple output logic circuit that converts coded inputs into coded
outputs where the input and output codes are different.
5. What is binary decoder?
A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2 n outputs lines.
6. Define Encoder?
An encoder has 2 n input lines and n output lines. In encoder the output lines generate the binary
code corresponding to the input value.
7. What is meant by priority Encoder? (May/Jun 2012, Nov/Dec 2015)
A priority encoder is an encoder circuit that includes the priority function. In priority encoder, if
2 or more inputs are equal to 1 at the same time, the input having the highest priority will take
precedence.
8. Define multiplexer?
Multiplexer is a digital switch. If allows digital information from several sources to be
routed onto a single output line.

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9. What is Demultiplexer?
A Demultiplexer is a circuit that receives information on a single line and transmits this
information on one of 2^n possible output lines
10. What is code conversion?
If two systems working with different binary codes are to be synchronized in operation, then we
need digital circuit which converts one system of codes to the other. The process of conversion is
referred to as code conversion.
11. What is code converter?
It is a circuit that makes the two systems compatible even though each uses a different binary
code. It is a device that converts binary signals from a source code to its output code. One
example is a BCD to Ex-3 converter.
12. What do you mean by analyzing a combinational circuit?
The reverse process for implementing a Boolean expression is called as analyzing a
combinational circuit. (ie) the available logic diagram is analyzed step by step and finding the
Boolean function.
13. Give the applications of Demultiplexer.
i) It finds its application in Data transmission system with error detection.
ii) One simple application is binary to Decimal decoder.
14. Mention the uses of Demultiplexer.
Demultiplexer is used in computers when a same message has to be sent to different receivers.
Not only in computers, but any time information from one source can be fed to several places.
15. Give other name for Multiplexer and Demultiplexer.
Multiplexer is otherwise called as Data selector.
Demultiplexer is otherwise called as Data distributor.
18. What is the function of the enable input in a Multiplexer?
The function of the enable input in a MUX is to control the operation of the unit.
19. List out the applications of decoder.
a) Decoders are used in counter system.
b) They are used in analog to digital converter.
c) Decoder outputs can be used to drive a display system.

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20. List the applications of Multiplexer. (Nov/Dec 2013)

1. They are used as a data selector to select one output of many data inputs.
2. They can be used to implement combinational logic circuits
3. They are used in time multiplexing systems.
4. They are used in frequency multiplexing systems.
5. They are used in A/D & D/A Converter.
6. They are used in data acquisition system.
21. List out the applications of comparators?
a. Comparators are used as a part of the address decoding circuitry in computers to select a
specific input/output device for the storage of data.
b. They are used to actuate circuitry to drive the physical variable towards the reference value.
c. They are used in control applications.
22. What is digital comparator?
A comparator is a special combinational circuit designed primarily to compare the relative
magnitude of two binary numbers. Comparators are used in central processing unit s (CPUs)
and microcontrollers (MCUs).
23. What is carry look-ahead addition? (Apr/May 2011)
The speed with which an addition is performed limited by the time required for the carries to
propagate or ripple through all of the stage of the adder. One method of speeding up the process
is by eliminating the ripple carry delay.
24. Difference between Decoder & Demultiplexer. (Apr/May 2011, 2015)
S.No Decoder Demux

Decoder is a many inputs to many Demux is a single input to many

1.
outputs device. outputs.
The selection of specific output line is
There are no selection lines.
2. controlled by the value of selection
lines.

25. Design Half Subtractor using basic gates. (May/June 2013)

Let X and Y be the two input variables and the output variables are D- Difference and B-
Borrow

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Truth Table:
Input
X Y
0 0
0 1
1 0
1 1
Logic Diagram:
Output
Difference Borrow
0 0
1 1
1 0
0 0

26. Draw the logic Diagram of 4 line to 1 multiplexer. (May/June 2013)

27. Draw the logic Diagram of a serial Adder. (Nov/Dec 2012)

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28.Design a three bit even parity Generator. (Nov/Dec 2012)

29. Implement a full adder using two half adder. (Apr/May 2011)

30. What is parity Checker?(Apr/May 2011)

A parity is an extra bit included with a binary message to make the number of 1s either odd
or even in the transmitter. The circuit that checks the parity in the receiver is called as parity
Checker.
31. Draw the two bit comparator circuit using logic gates (Apr/May 2015)

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32. Draw the combinational circuit that converts 2 coded inputs into 4 coded outputs.
(May/June 2016)

33. Draw the logic diagram and truth table of Full adder.

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UNIT-III
SEQUENTIAL CIRCUITS
1. What is sequential circuit?
The output not only depends on the present input but also depends on the past
history input variables. Memory unit is required to store the past history of input variable.
2. Difference between Combinational & Sequential Circuits. (Nov/Dec 2013)

Combinational Circuits Sequential Circuits

The output at all times depends only on the The output not only depends on the present
present combination of input variables. input but also depends on the past history input
variables.
Memory unit is not Required. Memory unit is required to store the past
history of input variable.
Clock input is not needed. Clock input is needed.
Faster in Speed. Speed is Slower.
Easy to design. Difficult to design.
Eg: Mux, Demux, Encoder,Decoder, Adders, Flipflops, counters.
Subtractors.

3. What are the classifications of sequential circuits? (Nov/Dec 2015)

The sequential circuits are classified on the basis of timing of their signals into two types. They
are:
1) Synchronous sequential circuit.
2) Asynchronous sequential circuit.
4. Define Flip flop.
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until
directed by an input signal to change its state.
5. What are the different types of flip-flop?
There are various types of flip flops. Some of them are mentioned below they are:
1. SR flip-flop
2. D flip-flop

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3. JK flip-flop
4. T flip-flop
6. What is edge triggering and level triggering? (Nov/Dec 2015)
Triggering means making an circuit active. In level triggering the circuit will become active
when the gating or clock pulse is on a particular level. In edge triggering the circuit becomes
active at negative or positive edge of the clock signal.
7. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the
output is reset.
8. What is the operation of JK flip-flop?
1. When K input is low and J input is high the Q output of flip-flop is set.
2. When K input is high and J input is low the Q output of flip-flop is reset.
3. When both the inputs K and J are low the output does not change
4. When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output
toggle on the next positive clock edge.
9. What is the operation of T flip-flop?
T flip-flop is also known as Toggle flip-flop.
1. When T=0 there is no change in the output.
2. When T=1 the output switch to the complement state (ie) the output toggles.
10. Define race around condition.
In JK flip-flop output is fed back to the input. Therefore change in the output results change in
the input. Due to this in the positive half of the clock pulse if both J and K are high then output
toggles continuously. This condition is called race around condition.
11. What is edge-triggered flip-flop?
The problem of race around condition can solved by edge triggering flip flop. The term edge
triggering means that the flip-flop changes state either at the positive edge or negative edge of
the clock pulse and it is sensitive to its inputs only at this transition of the clock.
12. What is a master-slave flip-flop?
A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the
other as a slave.
13. Define rise time and fall time.
The time required to change the voltage level from 10% to 90% is known as rise time(tr).

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The time required to change the voltage level from 90% to 10% is known as fall time(tf).
14. Define skew and clock skew.
The phase shift between the rectangular clock waveforms is referred to as skew and the time
delay between the two clock pulses is called clock skew.
15. Define setup time.
The setup time is the minimum time required to maintain a constant voltage levels at the
excitation inputs of the flip-flop device prior to the triggering edge of the clock pulse in order for
the levels to be reliably clocked into the flip flop. It is denoted as tsetup.
16. Define hold time.
The hold time is the minimum time for which the voltage levels at the excitation inputs must
remain constant after the triggering edge of the clock pulse in order for the levels to be reliably
clocked into the flip flop. It is denoted as thold.
17. Define propagation delay.
A propagation delay is the time required to change the output after the application of the input.
18. Define registers.
A register is a group of flip-flops; flip-flop can store one bit information. So an n-bit register has
a group of n flip-flops and is capable of storing any binary information/number containing n-bits.
19. Define shift registers.
The binary information in a register can be moved from stage to stage within the register or into
or out of the register upon application of clock pulses. This type of bit movement or shifting is
essential for certain arithmetic and logic operations used in microprocessors. This gives rise to
group of registers called shift registers.
20. What are the different types of shift type?
There are five types. They are:
1. Serial In Serial Out Shift Register
2. Serial In Parallel Out Shift Register
3. Parallel In Serial Out Shift Register
4. Parallel In Parallel Out Shift Register
5. Bidirectional Shift Register
21. Explain the flip-flop excitation tables for RS FF.
In RS flip-flop there are four possible transitions from the present state to the Next state. They
are:

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1). 0 to 0 transition: This can happen either when R=S=0 or when R=1 and S=0.
2). 0 to 1 transition: This can happen only when S=1 and R=0.
3). 1 to 0 transition: This can happen only when S=0 and R=1.
4). 1to 1 transition: This can happen either when S=1 and R=0 or S=0 and R=0.
22. Define sequential circuit?
In sequential circuits the output variables dependent not only on the present input variables but
they also depend up on the past output of these input variables.
23. What do you mean by present state?
The information stored in the memory elements at any given time defines the present state of the
sequential circuit.
24. What do you mean by next state?
The present state and the external inputs determine the outputs and the next state of the
sequential circuit.
25. Define synchronous sequential circuit
In synchronous sequential circuits, signals can affect the memory elements only at discrete
instant of time.
26. Give the comparison between synchronous & Asynchronous counter. (May/June 2014,
Nov/Dec 2014, May/June 2016)
S.No Asynchronous counters Synchronous counters
1. In this type of counter flip-flops are In this type there is no connection
between output of first flip-flop and
connected in such a way that output
clock input of the next flip - flop
of 1 st flip-flop drives the clock for
the next flip - flop.
2. All the flip-flops are Not clocked All the flip-flops are clocked
Simultaneously simultaneously
3. Logic circuit is very simple even for more Design involves complex logic circuit as
number of states. number of states increases.
4. Counter are low speed Counter are high speed

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27 . List out four basic applications of Flip-Flop. (Apr/May 2011)

1. Used as a memory Element.
2. Used as a Delay Element.
3. Used as a basic building block in sequential circuits such as counters and registers.
4. Data Transfer.
5. Frequency Division & Counting.
28. Write the Design procedure for designing a Synchronous sequential circuit. (Apr/May
2011)
1. State Diagram.
2. State Table.
3. State Assignment.
4. Excitation Table (Based on the Flip Flop given in the question)
5. K-Map
6. Circuit Diagram.
29. Give some applications of clocked RS Flip-flop.
1. Clocked RS flip flops are used in Calculators & Computers.
2. It is widely used in modern electronic products.
30. Draw the truth table of RS flipflop (Apr/May 2015)
It is constructed by feeding the outputs of two NOR gates back to the other NOR gates input.
The inputs R and S are referred to as the Reset and Set inputs, respectively.

31. Define Shift Register Counter.

A shift register can also be used as a counter. A shift register with the serial output connection
back to the serial input is called Shift register counter.

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32. What are the two types of shift register counters?

There are 2 types of shift Register counters are:
i). Ring counter: A ring counter is a circular shift register with only one flip flop being set, at any
particular time, all others are cleared.
ii). Johnson counter: The Johnson counter is a K-bit switch-tail ring counter with 2k decoding
gates to provides outputs for 2 k timing signals.
33. What do you mean by state diagram? (Nov/Dec 2013)
A graphical representation of a state table is called a state diagram.
34. What is the use of state diagram?
i) Behavior of a state machine can be analyzed rapidly.
ii) It can be used to design a machine from a set of specification.
35. What is state table?
A table, which consists time sequence of inputs, outputs and flip-flop states, is called state table.
Generally it consists of three section present state, next state and output.
36. What is a state equation?
A state equation also called, as an application equation is an algebraic expression that specifies
the condition for a flip-flop state transition. The left side of the equation denotes the next state of
the flip-flop and the right side; a Boolean function specifies the present state.
37. What is bi-directional shift register and unidirectional shift register?
A register capable of shifting both right and left is called bi-directional shift register.
A register capable of shifting only one direction is called unidirectional shift register.
38. Draw the state Diagram of JK Flip Flop.

39. The t pd for each flip-flop is 50 ns. Determine the maximum operating frequency for
MOD - 32 ripple counter. (Apr/May 2015)
f max (ripple)
= 5 x 50 ns = 4 MHZ

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40. What is the minimum number of flip flop needed to design a counter of modulus 60?
(Apr/May 2015)
2n>=60
n=6
41. Give the truth table for transparent latch (May/June 2016, Nov/Dec 2016)
D Latch also called transparent Latch
EN D Qn Qn+1 State
1 0 X 0 Reset
1 1 X 1 Set
0 X X Qn No change(NC)

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UNIT IV
MEMORY DEVICES
1.List the Classification of Memories. (Nov/Dec 2012)

Memories are classified as

1. Registers ,Main Memory and Secondary Memory
2. Sequential Access Memory and Random access Memory
3. Static and Dynamic Memory.
4. Volatile Memory and Non-Volatile memory.
5. Magnetic and Semiconductor Memory.
2. Explain ROM
A read only memory(ROM) is a device that includes both the decoder and the OR
gates within a single IC package. It consists of n input lines and m output lines.
Each bit combination of the input variables is called an address. Each bit combination that
comes out of the output lines is called a word. The number of distinct addresses possible
with n input variables is 2n.

3. List the types of ROM.

i) Programmable ROM (PROM)
ii) Erasable ROM (EPROM)
iii) Electrically Erasable ROM (EEROM)
4. Explain PROM.
PROM (Programmable Read Only Memory)
It allows user to store data or program. PROMs use the fuses with material like nichrome and
polycrystalline. The user can blow these fuses by passing around 20 to 50 mA of current for the
period 5 to 20s.The blowing of fuses is called programming of ROM. The PROMs are one time
programmable. Once programmed, the information is stored permanent.
5. Explain EPROM.
EPROM (Erasable Programmable Read Only Memory)
EPROM use MOS circuitry. They store 1s and 0s as a packet of charge in a buried layer of the
IC chip. We can erase the stored data in the EPROMs by exposing the chip to ultraviolet light via
its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip
can be reprogrammed.
6. Explain EEPROM. (Nov/Dec 2016)
EEPROM (Electrically Erasable Programmable Read Only Memory)

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EEPROM also use MOS circuitry. Data is stored as charge or no charge on an insulated layer or
an insulated floating gate in the device. EEPROM allows selective erasing at the register level
rather than erasing all the information since the information can be changed by using electrical
signals.
7. Differentiate ROM & PLDs.
S.No ROM (Read only Memory) PLDS (Programmable
Logic Array)
1. It is a device that includes both the It is a device that includes
decoder and the OR gates with in a both AND and OR gates
signal IC package. within a single IC package.

2. ROM does not full decoding of the PLDs does not provide full
variables and does generate all the decoding of the variable and
minterms goes not generate all
the minterms.

8. What are the different types of RAM?

a). NMOS RAM (Nitride Metal Oxide Semiconductor RAM)
b). CMOS RAM (Complementary Metal Oxide Semiconductor RAM)
c). Schottky TTL RAM
9. What is RAM? (Apr/May 2011)
RAM is Random Access Memory. It is a random access read/write memory. The data can be
read or written into from any selected address in any sequence.
10. Define ROM. (May/Jun 2012)
ROM is a type of memory in which data are stored permanently or semi permanently. Data can
be read from a ROM, but there is no write operation
11. Define address and word:
In a ROM, each bit combination of the input variable is called on address.
Each bit combination that comes out of the output lines is called a word.
12. What is programmable logic array? How it differs from ROM? (May/June 2012,
Nov/Dec 2016)
In some cases the number of dont care conditions is excessive, it is more economical to use a
second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it

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does not provide full decoding of the variables and does not generates all the minterms as in the
ROM.
13. Draw the Logic Diagram of a Static RAM Cell. (Nov/Dec 2012)
Static RAM Cell

14. What is mask programmable ROM?

A type of memory where the stored data are permanently stored into the memory device during
the manufacturing process.
15. What is field programmable logic array?
The second type of PLA is called a field programmable logic array. The user by means of certain
recommended procedures can program the FPLA.
16. Define PLD.
Programmable Logic Devices consist of a large array of AND gates and OR gates that can be
programmed to achieve specific logic functions.
17. What are the different types of programmable Logic devices? (May/Jun 2013, 2016)
PLDs are classified as PROM (Programmable Read Only Memory),
Programmable Logic Array(PLA),
Programmable Array Logic (PAL), and Generic Array Logic(GAL)
18 Define PROM.
PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates connected
to a decoder and a programmable OR array.
19. Define PLA
PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a programmable
AND array and a programmable OR array.

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20. Define PAL

PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR
array with output logic.
21. Why was PAL developed?
It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays
due to additional fusible links that result from using two programmable arrays and more circuit
complexity.
22. Why the input variables of PAL are buffered?
The input variables to a PAL are buffered to prevent loading by the large number
of AND gate inputs to which available or its complement can be connected.
23. What does PAL 10L8 specify?
PAL - Programmable Logic Array
10 - Ten inputs
L - Active LOW Ouput
8 - Eight Outputs.
24. What is CPLD?
CPLDs are Complex Programmable Logic Devices. They are larger versions of PLD with a
centralized internal interconnect matrix used to connect the device macro cells together.
25 .Define bit, byte and word.
The smallest unit of binary data is bit. Data are handled in a 8 bit unit called byte.
complete unit of information is called a word which consists of one or more bytes.
26. How many words can a 16x8 memory can store?
A 16x8 memory can store 16,384 words of eight bits each
27. Define Capacity of a memory.
It is the total number of data units that can be stored.
28. What is Read and Write operation? (Nov/Dec 2015)
The Write operation stores data into a specified address into the memory and the Read operation
takes data out of a specified address in the memory.
29. Why RAMs are called as Volatile?
RAMs are called as Volatile memories because RAMs lose stored data when the power is turned
OFF.

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30. List the two categories of RAMs.

1. Static RAM (SRAM)
2. Dynamic RAM (DRAM).
31. Define Static RAM and dynamic RAM
1. Static RAM use flip flops as storage elements and therefore store data indefinitely as long as
dc power is applied.
2. Dynamic RAMs use capacitors as storage elements and cannot retain data very long without
capacitors being recharged by a process called refreshing.
32. Define Cache memory
It is a relatively small, high-speed memory that can store the most recently used instructions or
data from larger but slower main memory.
33. What is the technique adopted by DRAMs.
DRAMs use a technique called address multiplexing to reduce the number of address lines.
34. Give the feature of UV EPROM
UV EPROM is electrically programmable by the user, but the store data must be erased by
exposure to ultra violet light over a period of several minutes.
35. Give the feature of flash memory.
The ideal memory has high storage capacity, non-volatility; in-system read and write capability,
comparatively fast operation. The traditional memory technologies such as ROM, PROM,
EEPROM individually exhibits one of these characteristics, but no single technology has all of
them except the flash memory.
36. What is a FIFO memory?
The term FIFO refers to the basic operation of this type of memory in which the
first data bit written into the memory is to first to be read out.
37. What are Flash memories?
They are high density read/write memories that are non-volatile, which means data can be stored
indefinitely without power.
38. List the three major operations in a flash memory.
Programming, Read and Erase operation.
39. What is programmable logic array? How it differs from ROM? (Nov/Dec 2015)
In some cases the number of dont care conditions is excessive, it is more economical to use a
second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it

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does not provide full decoding of the variables and does not generates all the minterms as in the
ROM.
40. What are the types of arrays in RAM?
RAM has two type of array namely,
a. Linear array
b. Coincident array
41. What is the basic difference between RAM and ROM circuitry (Apr/May 2015)
RAM ROM
Random Access Memory or RAM is a form of Read-only memory or ROM is also a form of
data storage that can be accessed randomly at data storage that can not be easily altered or
any time, in any order and from any physical reprogrammed.Stores instuctions that are not
location., allowing quick access and nescesary for re-booting up to make the
manipulation. computer operate when it is switched off.They
are hardwired.
RAM allows the computer to read data quickly ROM stores the program required to initially
to run applications. It allows reading and boot the computer. It only allows reading.
writing.
RAM is volatile i.e. its contents are lost when It is non-volatile i.e. its contents are retained
the device is powered off. even when the device is powered off.
The two main types of RAM are static RAM The types of ROM include PROM, EPROM
and dynamic RAM and EEPROM.

42. What are the terms that determine the size of a PAL?
The size of a PLA is specified by the
a. Number of inputs
b. Number of products terms
c. Number of outputs
43. What are the advantages of RAM?
The advantages of RAM are
a. Non-destructive read out
b. Fast operating speed
c. Low power dissipation

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d. Compatibility
e. Economy
44. Differentiate volatile and non-volatile memory?
Volatile Memory: They are memory units which lose stored information when power is turned
off. Eg: SRAM & DRAM
Non-Volatile Memory :It retains stored information when power is turned off. Eg: Magnetic disc
& ROM.
45. Comparison between SRAM & DRAM. (Apr/May 2015)
S.No Static RAM Dynamic RAM

1. Static RAM contains less memory Dynamic RAM contains more memory cells
per unit area. cells as compared to static
RAM per unit area.
2. Its access time is less hence faster Its access time is greater than static
memories.RAMs.
3. Static RAM consists of number of Refreshing Circuitry is required.
Dynamic RAM stores the data as a flip-
flops. Each flip-flop stores change on the
capacitor. It consists of one bit.
MOSFET and the capacitor for each cell.
Refreshing Circuitry is not required.

46. Comparison between PROM, PAL, PLA.(May/Jun 2013)(Nov/Dec 2013)

S.No PROM PAL PLA.

1. PROM AND array is Both AND & OR OR array is fixed and

fixed and OR array is arrays are AND array is
programmable. programmable. programmable.
2. Cheaper and simple to use. Costliest & complex Cheaper and simpler.
than PAL & PROMs.
3. All minterms are AND array can be AND array can be
decoded. programmed to get programmed to get desired
desired minterms. minterms.

47. What is Field Programmable Gate Array (FPGA) device. (Nov/Dec 2014)
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by
the customer or designer after manufacturing field-programmable. The FPGA configuration is
generally specified using a hardware description language (HDL). FPGAs contain programmable

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logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that
allow the blocks to be "wired together" somewhat like a one-chip programmable breadboard.
48. Compare and contrast EEPROM and Flash Memory.
EEPROM Flash Memory
Low Packaging Density High Packaging Density
Higher Cost per bit Lower Cost per bit
Consumes high power Consumes less power
Erasing is done individual byte wise Erasing is done in one bulk operation
Erasing and reprogramming of EEPROM is Erasing and reprogramming of EEPROM is
slower faster

48. How the bipolar RAM cell is different from MOSFET RAM Cell? (May/June 2016)
MOS have less leakage current than BJT. So power consumption is less.
MOS transistor has smaller size than BJT. So it gives high packing density.
MOS fabrication has less number of fabrication steps than BJT. Also fabrication of MOS much
simpler than BJT

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UNIT V
SYNCHRONOUS & ASYNCHRONOUS SEQUENTIAL CIRCUITS
1. What are the fundamental modes of sequential Circuits? (Nov/Dec 2012)
i) Input variable changes if the circuit is stable.
ii) Inputs are levels, not pulsed.
iii) Only one input can be changed at the given time
2. What is mealy and Moore circuit?
Mealy circuit is a network where the output is a function of both present state and input.
Moore circuit is a network where the output is function of only present state.
3. Differentiate Moore circuit and Mealy circuit? (Apr/May 2011)
S.No Moore circuit Mealy circuit
1. It is output is a function of It is output is a function of present
present state only. state as well as the present input.
2. Input changes do not affect the Input changes may affect the output
output. of the circuit.
3. Moore circuit requires more It requires less numbers of states
number of states for for implementing same function.
implementing same function.

4. What are hazards? (May/Jun 2013, Apr/May 2011, Nov/Dec 2015, Nov/Dec 2016)
Hazards are unwanted switching transients that may appear at the output of a circuit because
different paths exhibit different propagation delays.
5. What is static 1 hazard? (Nov/Dec 2015), (May/June 2016)
Output goes momentarily 0 when it should remain at 1.
6. What is static 0 hazard? (May/June 2016)
Output goes momentarily 1 when it should remain at 0.
7. What is dynamic hazard? (May/June 2016)
Output changes 3 or more times when it changes from 1 to 0 or 0 to 1.
8. How can the hazards in combinational circuit be removed?
Hazards in the combinational circuits can be removed by covering any two minterms that may
produce a hazard with a product term common to both. The removal of hazards requires the
addition of redundant gates to the circuit.

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9. Write short notes on Essential hazards. (Apr/May 2011)

An essential hazard occurs due to unequal delays along two or more paths that originate from
the same input. An excessive delay through an inverter circuit in comparison to the delay
associated with the feedback path causes essential hazard.
10. What are the types of asynchronous circuits?
1. Fundamental mode circuits
2. Pulse mode circuits
11. Briefly tell about pulse mode asynchronous sequential circuits? (Nov/Dec 2012)
a). Inputs and output are pulses.
b). width of pulses are long for circuit to respond to the input.
c). pulse width must not be so long that it is still present after the new state is reached.
12. What are the steps for the design of asynchronous sequential circuit?
a). Draw the State Diagram.
b). Construction of primitive flow table.
c). Merger Graph.
d). Reduction of flow table.
e). State assignment or Transition Table is made.
f). K-Map.
g). Circuit Diagram.
13. Define primitive flow table. (Apr/May 2011)
It is defined as a flow table which has exactly one stable state for each row in the table. The
design process begins with the construction of primitive flow table.
14. Give the comparison between state Assignment Synchronous circuit and state
assignment asynchronous circuit.
In synchronous circuit, the state assignments are made with the objective of circuit reduction. In
asynchronous circuits, the objective of state assignment is to avoid critical races.
15. What are races? (Nov/Dec 2016)
When 2 or more binary state variables change their value in response to a change in an input
variable, race condition occurs in an asynchronous sequential circuit. In case of unequal delays, a
race condition may cause the state variables to change in an unpredictable manner.
16. Define non critical race. (Nov/Dec 2016)

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If the final stable state that the circuit reaches does not depend on the order in which the state
variable changes, the race condition is not harmful and it is called a non critical race.
17. What is a critical race condition in asynchronous sequential circuit? (Nov/Dec 2014,
May/June 2016, Nov/Dec 2016)
If the final stable state depends on the order in which the state variable changes, the race
condition is harmful and it is called a critical race.
18. Give the methods used for critical race free state assignment. (May/June 2016)
i) Shared row state assignment
ii) One hot state assignment.
18. What is a cycle?
A cycle occurs when an asynchronous circuit makes a transition through a series of unstable
states. If a cycle does not contain a stable state, the circuit will go from one unstable to stable to
another, until the inputs are changed.
19. List the different techniques used for state assignment.
1. Shared row state assignment
2. One hot state assignment.
20. Define secondary variables.
The delay elements provide a short term memory for the sequential circuit. The present state and
next state variables in asynchronous sequential circuits are called secondary variables.
21. Write short note on shared row state assignment.
Races can be avoided by making a proper binary assignment to the state variables. Here, the state
variables are assigned with binary numbers in such a way that only one state variable can change
at any one state variable can change at any one time when a state transition occurs. To
accomplish this, it is necessary that states between which transitions occur be given adjacent
assignments. Two binary are said to be adjacent if they differ in only one variable.
22. Write short note on one hot state assignment.
The one hot state assignment is another method for finding a race free state assignment. In this
method, only one variable is active or hot for each row in the original Flow table, ie, it requires
one state variable for each row of the flow table. Additional row are introduced to provide single
variable changes between internal state transitions.
23. What are the problems involved in asynchronous circuits?
The asynchronous sequential circuits have three problems namely,
a. Cycles.

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b. Races.
c. Hazards.
24. Define ASM Chart. List its three basic elements (Nov/Dec 2014)
ASM charts resemble the flowchart conventionally used in software design to define the digital
hardware algorithm.
Three basic elements : State Box, Decision Box and the conditional output Box.
25. Recall the term Compatible state.
Two states are compatible if ,for each possible input, they have the same output whenever it is
specified and their next states are compatible if they are specified.
26. List the operators in Verilog HDL.
Boolean Logical
Unary Reduction Logical
Bit wise Logical
Relational Logical
Binary Arithmetic
Unary arithmetic

27. What are the modeling techniques in Verilog HDL.

Gate Level Modeling
Dataflow Modeling
Behavioral modeling

28. Elaborate Sequence detector

The sequence detector is a single input circuit that will accept a stream of bits and genetae an
output 1 whenever the particular sequence is detected.
29. Develop a dataflow description code for2:1 multiplexer
Module mux2 (mout, A, B, select);
Output mout;
Input A,B,select;
Assign mout=(select)? A:B;
Endmodule
30. Specify the use of wire declaration in verilog.
The wire declaration is used for internal connections in a circuit

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31. Define state table.

For the design of sequential counters we have to relate present states and next
states. The table, which represents the relationship between present states and
next states, is called state table.
32. What is pulse mode asynchronous machine?

A pulse mode asynchronous machine has two inputs. If produces an output whenever two
consecutive pulses occur on one input line only. The output remains at 1
until a pulse has occurred on the other input line. Write down the state table for
the machine.
33. What is fundamental Mode?
A transition from one stable state to another occurs only in response to a change
in the input state. After a change in one input has occurred, no other change in
any input occurs until the circuit enters a stable state. Such a mode of operation
is referred to as a fundamental mode.
34. Distinguish between combinational circuit and sequential circuit?( Apr/May 2015)
Combinational Circuit Sequential Circuit
The circuit whose output at any instant The circuit whose output at any instant
depends only on input present at that instant depends not only on the input present but also
only on the past output
No memory unit Having memory unit to store past output
Ex: half adder, full adder, Multiplexer Flipflop. Register , Counter

35. Draw the general model of ASM. (Nov/Dec 2015)

Conditional
Next state Next State Present State Output
Function Memory Function
Inputs (State Conditional
(Combinational (Combinatio Outputs
Register) nal Logic)
Logic)

State time State Output

Function
(Combinational
Logic) State
Outputs
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36. What is the most important consideration in making state assignments for asynchronus
network? ( Apr/May 2015)
In synchronous circuits state assignments are made with the objective of circuit reduction. In
synchronous circuits its objective is to avoid critical races.

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