CDH Le49smart06

SERVICE MENAUAL
-------6M82B-55E510
Content:
1.6M82B SPECIFICATION
2.LIST OF KEY PARTS
3.IC SPECIFICATION
4.BLOCK DIAGRAM
5.CIRCUIT DIAGRAM
6.MAIM PCB DRAWING
7.SERVICE FLOW CHARTS
6M82B Specification
1 Outlook
date 20140520
2 Brief Information
2.1 Product Name LCD TV: 55E510
2.2 Chassis Name 6M82B
2.3 Solution MSD6308RT-Z1-SVJ
2.4 Key functions IPTV/ISDB-T/PAL M,N
2.5 Target Market SOUTH AMERICA
2.6 Product Category
2.7 Product Positioning LOW END IPTV
2.8 Product size \
3 Panel Specification
3.1 Model Number Model Number
3.1.1 Panel Manufacturer SKYWORTH
3.1.2 Model Number 0B55DK004
3.2 Mechanical Mechanical
3.2.1 Panel Size 55"
3.2.2 Dimension 1233.5(H) x712.3(V) x67.9(D)
3.2.3 Visible Area (mm) : H x V 1209.6(H) x 680.4(V)
3.2.4 Pixel Format (H V) 1920 horiz. by 1080 vert. Pixels, RGB vertical stripe
3.2.5 Backlight Type LED
3.2.6 Diagonal Screen Size Typ. 54.64 inch diagonal
3.2.7 Pixel Pitch (mm) 0.63 mm x 0.63 mm
3.3 Electronic Parameter Electronic Parameter
3.3.1 Power consuption TBD
3.3.2 Brightness (cd/m2) 280nits (Center one point, Min.)
3.3.3 Contrast Ratio >600:1
3.3.4 Dynamic Contrast Ratio \
3.3.5 Veiwing Angle Viewing angle free ( R/L 120 , U/D 120)
3.3.6 Response Time (ms) <13mS
3.3.7 Back light Time (Hours) 30000
120Hz(100Hz)/240Hz(200H
3.3.8 No
z)
3.3.9 3D No/PR/SG \
4 Signal Receiving System
4.1 ATV Receiving System ATV Receiving System
4.1.1 PAL BG/I/DK/NTSC-M No
4..1.2 PAL/SECAM BG/DK/I No
4.1.3 PAL M/N NTSC-M Yes
4.2 DTV Receiving System DTV Receiving System
4.2.1 ATSC No
4.2.2 DVB-T No
4.2.3 DVB-T with CI No
4.2.4 DVB-T2 No
4.2.5 DVB-T2 with CI+ No
4.2.6 ISDB-T/SBTVD-T Yes
4.2.7 DTMB No
4.2.8 DVB-C with CA No
4.2.9 DVB-S No
4.2.10 DVB-S2 No
4.3 Antenna input Antenna input
4.3.1 Antenna Input port: 1 (1 No
4.3.2 Antenna Input port: 1 (1 No
4.3.3 Antenna Input port: 2 (1 air Yes
4.3.4 Type of Antenna Input Port IEC169-2 Female
Receiving Frequency range
4.3.5 54MHz864MHz
(ATV)
Receiving Frequency range
4.3.6 VHF 177-213 MHZ, UHF 473-803 MHZ
(DTV)
External Signal
4.4
Receiving System
4.4.1 Composite Input PAL 50Hz/60Hz Yes
4.4.2 SECAM No
4.4.3 NTSC 3.58 Yes
4.4.4 NTSC4.43 Yes
480i /480p/720p/1080i
4.4.5 Component Input Yes/Yes/Yes/Yes
(60Hz)
576i /576p/720p/1080i
4.4.6 Yes/Yes/Yes/Yes
(50Hz)
1080P
4.4.7 Yes/Yes/Yes/Yes/Yes
24Hz/25Hz/30Hz/50Hz/60
4.4.8 PC Input VGA (640 x 480) Yes
4.4.9 S-VGA (800 x 600) Yes
4.4.10 XGA (1024 x 768) Yes
4.4.11 W-XGA (1280 x 768) Yes
4.4.12 W-XGA1360768 Yes
4.4.13 S-XGA (1280 x 1024) Yes
480i /480p/720p/1080i
4.4.14 HDMI Input Yes/Yes/Yes/Yes
(60Hz) (Video Format)
576i /576p/720p/1080i
4.4.15 Yes/Yes/Yes/Yes
(50Hz) (Video Format)
1080P
4.4.16 24Hz/25Hz/30Hz/50Hz/60 Yes/Yes/Yes/Yes/Yes
Hz (Video Format)
4.4.17 VGA (640 x 480) (PC Yes
S-VGA (800 x 600) (PC
4.4.18 Yes
Format)
XGA (1024 x 768) (PC
4.4.19 Yes
Format)
W-XGA (1280 x 768) (PC
4.4.20 Yes
Format)
W-XGA1360768(PC
4.4.21 Yes
Format)
4.4.22 S-XGA (1280 x 1024) (PC Yes
4.4.23 USB Media player formats Please see attached
5 Features
5.1 Picture Picture
5.1.1 Picture Mode Normal/ Movie / Sports / User
5.1.2 Picture Display Size 4:3/Full Screen/Movie/Subtitle/Panoramic /Native
5.1.3 Picture Freeze Yes
5.1.4 Backlight Adjust No
5.1.5 Auto Format No
5.1.6 3:2 Pull Down No
5.1.7 4:3 Stretch Yes
5.1.8 Comfilter 3D
5.1.9 PIP(Single tuner) No
5.1.10 Noise Reduction Off/Low/Middle/High
5.1.11 MPEG Reduction Off/Low/Middle/High
5.1.12 3D No
5.1.13 Color temperature Cool/ Normal/Warm/ User
5.2 Sound Sound
5.2.1 Sound Mode Standard / Music / Film / Sports/ User
For personal
5.2.2 Yes
mode:Treble/Bass/Balance
5.2.3 Surround Yes
5.2.4 Sound Mode Standard / Music / Film / Sports/ User
5.2.5 Equalizer Yes
5.2.6 Audio Output Power 2 X 8W
5.2.7 NICAM No
5.2.8 A2 No
5.2.9 BTSC(MTS) Yes
5.3 Teletext Teletext
5.3.1 FLOF/TOP No
5.3.2 Memory Page No
5.3.3 Character Language No
5.3.4 Teletext Level No
5.4 Program Management Program Management
5.4.1 V-Chip No
5.4.2 Parent Control(Child Lock) Yes
5.4.3 Closed Caption Yes
5.4.4 Subtitle Yes
5.4.5 EPG Yes
5.4.6 Channel list Yes
5.4.7 Faivorate Channel List Yes
5.4.8 Channel Editor Yes
5.4.9 On/Off timer Yes
5.4.10 Sleep timer Yes
5.4.11 Channel Swap timer No
5.4.12 Blue Screen Yes
5.5 AC Input AC Input
5.5.1 AC Input Range 100-240V
5.5.2 AC Plug Type TBD
5.5.3 AC Cable Length 1800mm
5.5.4 Power Consumption 90W
5.5.5 Standby Power 0.5W
5.6 HDMI HDMI
5.6.1 CEC Yes
5.6.2 ARC No
5.6.3 3D No
5.6.4 MHL Yes
5.7 Software Update Software Update
5.7.1 By USB Yes
5.7.2 By Internet No
5.7.3 Internet Auto search TBD
5.7.4 By Over-Air /
5.7.5 By other Service Port /
5.8 PVR PVR
5.8.1 By External USB or HDD Yes
5.8.2 Built in HDD No
5.8.3 Time Shift Yes
5.9 OSD Lauguage OSD Lauguage
5.9.1 OSD Lauguage English/Spanish/Portuguese
5.1O USB File System USB File System
5.10.1 FAT16 Yes
5.10.2 FAT32 Yes
5.10.3 NTFS Yes
5.11 Middleware Middleware
5.11.1 MHEG5 No
5.11.2 Ginga Yes
5.11.3 MHP No
5.12 Wifi Wifi
5.12.1 Wifi Dongle No
5.12.2 Wifl Built in Yes(Optional)
6 Terminals
Teminal Direction (Side
6.1 and Bottom & Side and
Rear)
6.2 Input
6.2.1 Tuner Rear X2
6.2.2 Composite Side X1
6.2.3 S-Video No
6.2.4 Full Scart No
6.2.5 Half Scart No
6.2.6 Component Rear X1
PC input with 3.5mm mini
6.2.7 Rear X1
jack audio input
6.2.8 HDMI Rear X2 & Side X1
6.2.9 USB Rear X1& Side X1
6.2.10 LAN Side X1
6.2.11 CI Slot No
6.2.12 CA Slot No
6.3 Output Output
6.3.1 Video Output No
Audio Output (Fixed & Rear,Share with earphone,(Fixed for line out & Varible for
6.3.2
Variable) Earphone)
6.3.3 Digital Audio Output Rear X1(COAXIAL)
6.3.4 Earphone Rear X1
Diagram of Teminal
6.4 Please see attached
Configuration
7 Mechanical Spec
7.1 Cabinet Cabinet
7.1.1 Cabinet color For front back stand \
Operation Keys / Touch
7.1.2 7
sensor
7.1.3 AC Power Switch Mechanical power switch \
7.1.4 LED Indicator Power on (Green) \
Power on / Standby (Green
7.1.5 Yes
/ Red )
Power on / Standby /
7.1.6 Recording(Green / Red / \
Orange)
Program Timer / Recoding
7.1.7 \
(Green / Red)
On Timer or Program
7.1.8 \
Timer(Green)
Silk Printing / SUS Badge
7.1.9 Logo Style \
(inlet type)
7.1.10 Stand Tilt / Swivel \
7.2 Dimension & Stuffing Dimension & Stuffing
7.2.1 Size (with stand)( mm ) 1233.5*280*773.3
7.2.2 Size (without stand) ( mm ) 1233.5*67.9*723.7
Package Size (with
7.2.3 1400*220*867.5
stand)(mm)
7.2.4 Net Weight(Kg)
7.2.5 Gross Weight
Loading quantity
7.2.6 (20GP/40GP/40GP) with 80\168\168
pallet
Loading quantity
7.2.7 (20GP/40GP/40GP) 84\168\252
without pallet
Stand build in Packing Box
7.2.8
(together or separately )
8 Accessories
8.1 Remote Controller Remote Controller
8.1.1 Type No. HS-2103H-00(Option)
8.1.2 Battery YesTBD)
8.2 Instruction Manual Instruction Manual
8.2.1 Paper size \
8.2.2 Printing Color \
Languages (Refer to Sales
8.2.3 \
Country Sheet)
8.2.4 Total Pages \
8.2 Others Others
8.2.1 3D Glasses \
8.2.2 Camera \
8.2.3 etc \
9 Requested Certification
9.1 CB yes
9.2 UL TBD
9.3 EMC TBD
9.4 FCC TBD
9.5 HDMI TBD
9.6 USB TBD
9.7 CI+ No
9.8 Dolby TBD
9.9 DOLBY + TBD
9.10 Dvix Hometheatre TBD
9.11 DviX HD TBD
9.12 DviX+HD TBD
9.13 MHL TBD
9.14 DLNA TBD
9.15 CTS TBD
9.16 Wifi TBD
9.17 MPES TBD
9.18 Energy Star TBD
9.10 Dvix Hometheatre TBD
9.11 DviX HD TBD
9.12 DviX+HD TBD
9.13 MHL YES
9.14 DLNA YES
9.15 CTS TBD
9.16 Wifi TBD
9.17 MPES TBD
9.18 Energy Star TBD
LIST OF KEY PARTS (6M82B)
- 42E510/55E510-6M82B 2014226

1 4709-K9F2G1-0480 K9F2G08U0C-SCB0 TSOP1 U18 1 256M X 8BIT NAND FLASH
2 471J-SI2150-0280 SI2157-A30-GMR SILICON 28PIN-QFN U17 1 WORLDWIDE DIGITAL AND ANALOG TV TUNER
3 4722-T31100-0280 4722-T31100-0280 TEXAS 28PIN-TSSOPPWP U15 1 15W STEREO OUTPUT/CLASS-D
4 4752-C24080-0080 CAT24C08WI-GT3 CATALYST SOIC-8 U10 1 8K-BIT IIC BUS SERIAL EEPROM)
5 472T-S94351-0080 STM9435 SAMHOP SO-8 U20 1 P-CHANNEL ENHANCEMENT MODE MOSFET
6 4740-B35440-0080 BH3544F-E2 ROHM SOP8 U14 1 HEADPHONE AMP.
7 475C-M63080-3690 MSD6308RT-Z1-SVJ MSTAR FBGA U9 1 DTV PROCESSOR
8 476A-M14940-0080 MP1494DJ-LF-Z MPS TSOT-23-8 U5 1 2A 16V SYNCHRONOUS STEP DOWN CONVERTER
9 476A-M14950-0080 MP1495DJ-LF-Z MPS TOST-23-8 U4U2 2 3A 16V SYNCHRONOUS STEP DOWN CONVERTER
10 47B6-A11174-0300 AS1117L/TR-HF A1 SOT-223 U3 1 1A ADJUSTABLE LDO
11 47C5-A21710-0050 AP2171WG-7 DIODES INCORPORATED SOT-25 U12 1 1A SINGLE CHANNEL POWER SWITCH
12 47DG-L11171-0030 LD1117-3.3 SOT-223 U7,U6 2 3.3V/1A,3-TERMINAL POSITIVE VOLTAGE REGULATOR
13 47FK-P42750-0120 PE42750MLAB-Z QFN U16 1 RF SIGNAL SWITCH
14 47FY-A10130-0060 AZ1013-04S SOT23-6L U19 1 LOW CAPACITANCE ESD PROTECTION
15 616P-049100-0270 73330200 H-TYPE 14.5MM D=6.1MM cn29 1 RF CONNECTOR

PDF "pdfFactory Pro" www.fineprint.cn

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Headphone Amplifiers
Standard
Headphone Amplifiers
BH3541F,BH3544F,BH3547F,BH3548F No.10102EAT02
Description
BH3541F, BH3544F, BH3547F, BH3548F is headphone amplifiers suitable for portable products.
BH3541F has a fixed gain of 0 dB and BH3544F, BH3547F, BH3548F has a fixed gain of 6 dB.
External resistors for gain setting are not needed. Package of BH3541F, BH3544F, BH3547F, BH3548F is pin-to-pin
compatible (SOP8), enable to replace each other easily.
BH3541F, BH3544F, BH3547F, BH3548F also has mute functions that make it easy to prevent pop noise when power
supply turns on/off. Moreover, thermal shutdown function is built-in.
BH3541F, BH3544F, BH3547F can drive 16/32 load, BH3548F can drive 8/16/32 . So, BH3548F is suitable for 8
receiver.
Features
1) Built-in mute function for preventing pop noise when power supply turns on/off
2) Built-in thermal shutdown function
3) BH3541F, BH3544F, BH3547F, BH3548F are pin-to-pin compatible
4) SOP8 small package
Applications
TV, Desktop PC, Notebook PC, Camcorder and other equipment having headphone output
Line up
Part No. BH3541F BH3544F BH3547F BH3548F Unit
Supply voltage +2.8 +6.5 +4.5 +5.5 +4.0 +5.5 V

Quiescent current 7.0 3.7 6.5 mA
Amplifier gain 0 6 dB
Output [RL=16 ] 62 77 62 mW
load impedance 16 / 32 8/16/32
Operating temperature range -25 +75 -40 +85
Absolute maximum ratings(Ta=25C)

Ratings
Parameter Symbol Unit
BH3541F,BH3544F,BH3547F,BH3548F
Applied voltage VCC 7.0 V
*1
Power dissipation Pd 550 mW
Storage temperature Tstg -55 +125 C
*1 Derating is done at 5.5mW/C above Ta=25C. (When mounted on a 70mm70mm1.6mm PCB board, FR4)
Operating conditions (Ta=25C)

Limits
BH3541F,BH3544F BH3547F BH3548F
Supply voltage VCC +2.8 +6.5 +4.5 +6.5 +4.0 +5.5 V
Temperature Range Topr -25 +75 -40 +85
* These product are not designed for protection against radioactive rays.
www.rohm.com
1/8 2010.05 - Rev.A
2010 ROHM Co., Ltd. All rights reserved.

BH3541F,BH3544F,BH3547F,BH3548F Technical Note
Electrical characteristics (Unless otherwise noted, Ta=25C,VCC=5V,RL=32 ,f=1kHz,BW=400 30kHz

BH3541F : VIN=0dBV, BH3544F, BH3547F, BH3548F : VIN =-6dBV)
Limits(TYP.)
Parameter Symbol Unit Conditions
BH3541F BH3544F BH3547F BH3548F
Quiescent current IQ 7 3.7 6.5 mA VIN=0Vrms
Mute pin control voltage H VTMH 1.6< V Mute OFF
Mute pin control voltage L VTML <0.3 V Mute ON
Gain GVC 0 6 dB -
Gain difference between
GVC 0 dB -
channels
Total harmonic distortion THD 0.02 0.05 0.02 % BW=20 20kHz
RL=32 ,THD<0.1%
(BH3541F,BH3544F,BH3548F)
Rated output 1 PO1 31 46 31 mW
RL=32 ,THD 0.3%
(BH3547F)
RL=16 ,THD<0.1%
(BH3541F,BH3544F,BH3548F)
Rated output 2 PO2 62 77 62 mW
RL=16 ,THD 0.5%
(BH3547F)
RL=8 ,THD 0.25%
Rated output 3 PO3 - 120 mW
(BH3548F)
Output noise voltage VNO -93 dBV BW=20 20kHz,Rg=0
Channel separation CS -90 -87 -90 dB Rg=0
Mute attenuation ATT -80 dB Rg=0
Ripple rejection RR -57 dB fRR=100Hz,VRR=-20dBV
Input resistance Rin 180 90 k -
Reference data
BH3541F/BH3544F BH3541F/BH3544F BH3541F/BH3544F
Fig. 1 Quiescent current vs. Fig. 2 in DC current vs. Fig. 3 Output voltage vs.
power supply voltage power supply voltage Mute control voltage
www.rohm.com
2/8 2010.05 - Rev.A

Reference data (Continued)

10 10
Ta 25 C
Ta 25 C
RL 32 RL 32
VCC 5V
VCC 3V
1 1
f 10kHZ f 10kHZ
0.1 0.1
f 1kHZ f 1kHZ
0.01 0.01
f 100HZ
f 100HZ
0.001 0.001
40 30 20 10 0 10 40 30 20 10 0 10
OUTPUT VOLTAGE :VO (dBV) OUTPUT VOLTAGE: VO (dBV)
Fig. 4 Voltage gain vs. frequency Fig. 5 Total harmonic distortion vs. Fig. 6 Total harmonic distortion vs.
output voltage (1) output voltage (2)
Fig. 7 Total harmonic distortion vs. Fig. 8 Total harmonic distortion vs. Fig. 9 Channel separation vs.
output voltage (3) output voltage (4) frequency
Fig. 10 MUTE attenuation vs. frequency Fig. 11 Ripple rejection vs. frequency Fig. 12 Ripple rejection vs.
power supply voltage
www.rohm.com
3/8 2010.05 - Rev.A

Block diagram
V CC OUT2 BIA S IN2
8 7 6 5
B IAS
180 k
0d B (90 k)
(6d B)
TS D 180 k
(9 0k)
0 dB
(6d B)
MUTE
1 2 3 4
OU T1 MUTE IN1 GND
( ) are BH3544F, BH3547F, BH3548F values.
Fig. 13
Measurement circuit
Fig. 14
www.rohm.com
4/8 2010.05 - Rev.A

Terminal Equivalent Circuit / Description
Pin Pin Equivalent circuit

I /O Pin voltage Function
No. Name BH3544F,BH3547F,BH3548F BH3547F
VCC VCC
1 OUT1
2.1V
O Output pin
(VCC=5V)
7 OUT2 1 1
7 10k 7 10k
VCC VCC
0.1V Mute control pin

2 2
2 MUTE I (When open) Mute on:Hi
190k 200k
Mute off:Lo (open)
VCC VCC
3 IN1
2.1V 3 3
I Input pin
(VCC=5V)
5 IN2 5 180k 5 90k
BIAS BIAS
VCC VCC Bias pin
(Since the 47 F
externally attached
60k 70k
2.1V capacitor also serves
6 BIAS I/O
(VCC=5V) 6 6 BIAS as the time constant for
BIAS
60k
64k pop noise
countermeasures,
evaluate adequately
when changing it.)
4 GND I - - - GND pin
8 VCC I - - - Power supply pin
The figure in the pin explanation and input/output equivalent circuit is reference value, it doesnt guarantee the value.
www.rohm.com
5/8 2010.05 - Rev.A

Application circuit
C7
330
+ C5
C6 R5 1
47 VIN2
VCC +
VCC OUT2 BIAS IN2
C8 +
10 8 7 6 5
BIAS
180k
0dB (90k)
(6dB)
TSD 180k
(90k)
0dB
(6dB)
MUTE
C1 1 2 3 4
330
OUT1 MUTE IN1 GND
+ C3
1
VMUTE C2 VIN 1
R2 100k 1
H : Active R3
L : Mute
Fig. 15
Description of external components.

1) Input coupling capacitors (C3, C5)
These are determined according to the lower cutoff frequency fc. Moreover, since lowering the capacitance can cause
the occurrence of pop noise, when changing this, determine it after adequate checking.
Since the input impedance of the BH3541F is 180k and that of the BH3544F,BH3547F,BH3548F is 90k , these are
found by the expressions below, although drift, temperature characteristics, and other considerations are necessary.
(Layered ceramic capacitors are recommended.)
C3(C5)=1/(2 180k fc) [BH3541F]
C3(C5)=1/(2 90k fc) [BH3544 ,BH3547F,BH3548F]
2) Bias capacitor (C6)
When VCC=5V, 47 F is recommended. Since lowering the capacitance too much can cause worsening of electrical
characteristics or the occurrence of pop noise, when changing this, determine it after checking this adequately.
3) Mute pin pop noise countermeasures (R2, C2)
Since the BH3541F,BH3544F,BH3548F has an impedance of 190k against GND and the BH3547F has 200k , it may
be impossible to cancel mute mode if R2 is made too large.
4) Output coupling capacitors (C1, C7)
These are determined by the lower cutoff frequency. If RL is the output load resistance (assuming a resistance RX is
put in for output protection or current restriction), these are found by the expression below.
C1(C7)=1/(2 (RL+R ) fc)
5) Input gain adjustment resistances (R3, R5) (BH3544F,BH3547F)
Externally attached resistances (R3, R5) make input gain adjustment possible. The gain found by the expression
below can be set.
GVC=6+20log(90k /(90k +R3[R5])) [dB]
When input gain is not accommodated, these resistors have no use.
Notes for use

1) Numbers and data in entries are representative design values and are not guaranteed values of the items.
2) Although we are confident in recommending the sample application circuits, carefully check their characteristics further
when using them. When modifying externally attached component constants before use, determine them so that they
have sufficient margins by taking into account variations in externally attached components and the Rohm LSI, not only
for static characteristics but also including transient characteristics.
3) Absolute maximum ratings
If applied voltage, operating temperature range, or other absolute maximum ratings are exceeded, the LSI may be
damaged. Do not apply voltages or temperatures that exceed the absolute maximum ratings. If you think of a case in
which absolute maximum ratings are exceeded, enforce fuses or other physical safety measures and investigate how
not to apply the conditions under which absolute maximum ratings are exceeded to the LSI.
www.rohm.com
6/8 2010.05 - Rev.A

4) GND potential
Make the GND pin voltage such that it is the lowest voltage even when operating below it. Actually confirm that the
voltage of each pin does not become a lower voltage than the GND pin, including transient phenomena.
5) Thermal design
Perform thermal design in which there are adequate margins by taking into account the allowable power dissipation in
actual states of use.
6) Shorts between pins and misinstallation
When mounting the LSI on a board, pay adequate attention to orientation and placement discrepancies of the LSI.
If it is misinstalled and the power is turned on, the LSI may be damaged. It also may be damaged if it is shorted by a
foreign substance coming between pins of the LSI or between a pin and a power supply or a pin and a GND.
7) Operation in strong magnetic fields
Adequately evaluate use in a strong magnetic field, since there is a possibility of malfunction.
8) Pop noise countermeasures
In order to prevent the pop noise that occurs when the power supply turns ON or OFF, make the rise and fall with
reference to the timing diagram shown below.
1)BH3541F/ BH3544F/ BH3548F
Rise time
Rise time
A PLAY period
A
VCC
B C
OUT
MUTE
Fig. 16
(A):Mute period (Use as pop noise countermeasure when power supply turns ON/OFF by makingVMUTE=Lo.)
(B):Mute cancellation period (This has a time constant because it is used by the externally attached C2 and R2 as
a pop noise countermeasure on mute cancellation, so be careful of the timing.)
(C):Mute start time (As on cancellation, this has a time constant.)
2)BH3547F (MUTE period)
(Rise time) (Fall period)

(PLAY period)
VCC (B)
(A)
Vmute
SG
(Input Signal)
OUT
Fig. 17
(A):Before VCC rise (or at the same time as VCC) make mute cancelled (VMUTE=Hi).
(B):Soft mute period (This time can be set by externally attached R2 and C2)
www.rohm.com
7/8 2010.05 - Rev.A

Ordering part number
B H 3 5 4 1 F - E 2
Part No. Part No. Package Packaging and forming specification

3541 F: SOP8 E2: Embossed tape and reel
3544
3547
3548

o
--
p
p p
-

- -

o
-
www.rohm.com
8/8 2010.05 - Rev.A

- -
-
- - --
- - - - - - -
- - --
- - - -
- -- -
- - - -
- - - -
- - -- - - -
- -
- - - -
- - - - -
--
- - - - - --
- -
- -- - - - -
- -
- - -
-- -
- - - -
- - -
- - -- -
- - -- - -
- - - - -- - -
-- -
- - - -
- -

w - -


PRODUCTS TYPE PAGE
Semiconductor Regarding the RoHS Directive 11
IC
RoHS
Regarding the RoHS Directive 2002/95/EC
LSIRoHS

We guarantee that followed LSI product supplied to you are in compliance with the
RoHS Directive prohibiting the use of hazardous substances.

Remark
Type
LSI
LSI all products
RoHS Hazardous substances of RoHS
Lead (Pb)
Cadmium (Cd)
Mercury (Hg)
Hexavalent Chromium (Cr )
PBB Polybrominated Biphenyls (PBBs)
PBDE Polybrominated Diphenyl Ethers (PBDEs)
RoHS

There is something that contains Lead at the internal connection as a die-attach material.
However, they are high-melting point solders (contain Lead more than 85%) and are
excluded from RoHS Directive.
REV.A 2010.06.08 SPECIFICATION No.
TSZ2211104
USB 2.0 4-Port Hub
Data Sheet Rev. B0.7
FE1.1s Revision B
USB 2.0 HIGH SPEED 4-PORT HUB CONTROLLER
Data Sheet
INTRODUCTION FEATURES
The Terminus FE1.1s is an USB 2.0 High Speed 4- Fully compliant with Universal Serial Bus
port hub controller with special features to support Specification Revision 2.0 (USB 2.0);
GSMA Universal Charging Solution, (UCS). It is Upstream Facing Port supports High-
fully compliant to USB-IF Universal Serial Bus Speed (480MHz) and Full-Speed
Specification Revision 2.0 and Battery Charging (12MHz) modes;
Specification Revision 1.1. 4 Downstream Facing Ports support High-
Speed, Full-Speed, and Low-Speed
The FE1.1s is a highly integrated, high quality, and
(12MHz) modes;
high performance solution for USB 2.0 4-port hub.
Compliant with Universal Charging Solution,
With its tiny footprint and extremely low power
and USB Battery Charging Specification 1.1.
consumption, it is the best choice for embedded
Integrated USB 2.0 Transceivers;
application as well as standalone hub.
Integrated upstream 1.5K pull-up,
The high quality of FE1.1s is guaranteed by Design-
downstream 15K pull-down, and serial
For-Testing with comprehensive scan chains and
resisters;
Built-In-Self-Test modes which could exercise all
Integrated 5V to 3.3V and 1.8V regulators;
High, Full, and Low Speed analog front end (AFE)
Integrated Power-On-Reset with power failure
components on the packaging and testing stages.
detection circuit;
FE1.1s could be optionally configured to support Integrated 12MHz Oscillator with feedback
Charging Downstream Ports as defined by USB-IF resister and crystal load capacitors;
Battery Charging Specification. With this feature Integrated 12MHz-to-480MHz Phase Lock
enabled, an USB hub could be easily transformed Loop (PLL);
into a charging station USB Charging Hub for Integrated Portable Device detection circuitry
Universal Charging Solution compliant battery for UCS supporting;
based portable devices. Single Transaction Translator (Single TT)
One TT for all downstream ports;
October 18, 2010 Preliminary, Subject to Change Without Notice 1

USB 2.0 4-Port Hub
The TT could handle 64 periodic Start-

Split transactions, 32 periodic Complete-
Split transactions, and 6 none-periodic
transactions;
Ganged Power Control and Global Over-
Current Detection support;
EEPROM configured options
Vendor ID, Product ID, & Device Release
Number; and
Number of Downstream Ports;
Automatic re-enumeration when hub switches
from self-powered mode to bus-powered mode;
Board configured comprehensive Port
Indicators support:
Four Downstream Port Enabled indicator
LED (Green, one for each port), plus one
Active/Suspend indicator LED (Red); or
One joint Downstream Port Enabled
indicator LED (Green, one for all ports),
plus one Active/Suspend indicator LED
(Red); or
One joint Downstream Port Enabled
indicator LED (Green, one for all ports),
plus one Charging Request/Portable
Device Detection indicator LED (Blue);
Board configure support of portable device
detection mechanism for Universal Charging
Solution on all 4 downstream ports.

USB 2.0 4-Port Hub
BLOCK DIAGRAM
To Downstream To Upstream
Devices Host/Hub
Down- Down- Down- Down-

Upstream
stream stream stream stream
PHY
PHY #1 PHY #2 PHY #3 PHY #4
Routing Switch
USB Multi-port Transceiver Macro Cell

3.3V & 1.8V Regulator Data Recovery
PLL Data
&
12MHz (x40) Transmit
OSC POR Elastic Buffer
Crystal
Over Current
Detection Downstream Port
Serial Upstream
Interface Port
Power Switch Controllers
Engine Controller
Control EEPROM,
Transaction Translator Hub Activity LED,
Transaction Translator Hub
Full/Low-Speed
High-Speed Handler Controller
Port Indicator LED,
Handler Charging Request
LED,
USB 2.0
Unified Transaction Hub
Translator Buffer (2KB)
Controller
Fig. 1: Block Diagram

USB 2.0 4-Port Hub
PACKAGE I
28-Pin SSOP
(Body Size: 10mm x 4mm, Pitch: 0.64mm)
PIN ASSIGNMENT
VSS 1 28 NC
XOUT 2 27 TESTJ
XIN 3 26 OVCJ
DM4 4 25 PWRJ
DP4 5 24 LED2
DM3 6 23 LED1
DP3 7 FE1.1s 22 DRV
DM2 8
(Rev. B) 21 VD33F
DP2 9 20 VDD5
DM1 10 19 BUSJ
DP1 11 18 VBUSM
NC 12 17 XRSTJ
NC 13 16 DPU
REXT 14 15 DMU
Fig. 2: 28-Pin SSOP Pin Assignment

USB 2.0 4-Port Hub
PACKAGE II
24-Pin WQFN
(Body Size: 4mm x 4mm, Pitch: 0.5mm)
(Exposed Pad: 2.8mm x 2.8mm)
PIN ASSIGNMENT
VBUSM
XRSTJ
REXT
BUSJ
DMU
DPU
18 13
VDD5 19 12 DP1
VD33F DM1
DRV FE1.1s DP2
LED1 (Rev. B) DM2
LED2 DP3
25 VSS
PWRJ 24 7 DM3
1 6
XOUT
XIN
TESTJ
DM4
DP4
OVCJ
Fig. 3: 24-Pin WQFN Pin Assignment

USB 2.0 4-Port Hub
PIN DESCRIPTION TABLE
Pin Name Pin No. Type Function Note

SSOP QFN
VSS 1 25 P Ground (pin 25 of WQFN is the underbelly exposed pad)
XOUT 2 3 OSC 12MHz Crystal Oscillator output. 1
XIN 3 4 OSC 12MHz Crystal Oscillator input/External 12MHz clock input. 1
DM4 4 5 UTD The D- pin of the 4th Downstream Facing Port.
DP4 5 6 UTD The D+ pin of the 4th Downstream Facing Port.
DM3 6 7 UTD The D- pin of the 3rd Downstream Facing Port.
DP3 7 8 UTD The D+ pin of the 3rd Downstream Facing Port.
DM2 8 9 UTD The D- pin of the 2nd Downstream Facing Port.
DP2 9 10 UTD The D+ pin of the 2nd Downstream Facing Port.
DM1 10 11 UTD The D- pin of the 1st Downstream Facing Port.
DP1 11 12 UTD The D+ pin of the 1st Downstream Facing Port.
NC 12 P These 2 pins were 1.8V power before Revision B. Though backward
18 compatible, it is strongly recommended to be left as No-Connection
in new designs.
They could still be used in this version for testing internal 1.8V level.
NC 13 P This pin was 3.3V power input before Revision B. It could be either
left as No-Connection for new design or connected to pin 21 (VD33)
through the PCB board as backward compatible.
REXT 14 13 External Bias Resister
A 2.7K ( 1%) resister should be connected to VSS to provide
internal bias reference.
DMU 15 14 UTU The D- pin of the Upstream Facing Port.
DPU 16 15 UTU The D+ pin of the Upstream Facing Port.
XRSTJ 17 16 OD- External Reset
PU The chip is reset by driving this input low for a minimum pulse of 10
s. For normal applications, it should be left as No-Connection.
VBUSM 18 17 I Upstream Port Power (VBUS) Monitor
This pin monitors the power state of VBUS from upstream facing
port. High level indicates that the host is powered up and the hub
should function normally. Low level indicates that the host is
powered down, and the hub should be in power-down state.
BUSJ 19 18 I Bus Power Sense
This pin identify the primary power source of the hub. High level
indicates the hub is Self-Powered and has enough strength to support
High-Power devices on its downstream ports. Otherwise, it is Bus-
Powered and each downstream ports are presumed to supply 100mA
of power only.

USB 2.0 4-Port Hub
VDD5 20 19 P 5V Power Input

This is the 5V power input for integrated 5V 3.3V regulator.
However, if external 3.3V source is used, this pin should be No-
Connection.
VD33F 21 20 P 3.3V output filter capacitor for embedded 5V 3.3V regulator, or
3.3V input from external source.
DRV/ 22 21 I/O LED Drive Control/Charging Hub Enable
CHRGEN During power-on-reset, this pin is used as Charging Hub Enable. If it
is tied to high, the battery charging function will be enabled.
Otherwise, it is a normal hub and this pin functions as LED driving
control pin.
LED1/ 23 22 I/O LED Control 1/External EEPROM Clock
EESCL Port 1 and Port 3 device connected indicator (LED) control; or, when
LED2 is tied to high during power-on-reset, it is the joint indicator
for all ports. At the same time, it could also be used as the clock
(SCL) of external EEPROM.
LED2/ 24 23 I/O LED Control 2/Joint LED Indicator Enable
JLEDEN Port 2 and Port 4 device connected indicator (LED) control. During
power-on-reset, it is a configuration input for enabling Joint Port
Indicator by tying to 3.3V.
PWRJ 25 24 OD Power Enable
This is an active low, open-drain output signal for controlling power
to the downstream devices in Ganged Power Switching mode. It is
enabled and disabled by the host hub driver to reduce the in-rush
current or in response to Over-Current Detection.
OVCJ 26 1 I Over Current Sense
Active low input from external current monitor indicating over
current condition for Global Over-Current Protection.
TESTJ/ 27 2 OD- Test Mode Enable/External EEPROM Serial Data
EESDA PU Active low, open drain signal with internal pull-up resistor. When
tied to low during power-on-reset, the chip will be set in test mode.
The test mode is for factory test only, for all applications, this pin
should be either left as No-Connection or connected to the Serial
Data/Address (SDA) pin of external 2-wire EEPROM.
Type Abbreviation
I: Schmitt Trigger Input, 3.3V 5V-Tolerant;
O: Output (driving strength: 8mA);
OD: Output, Open Drain (sink current: 4mA);
OD-PU: 3.3V Input/Output, Open Drain with Internal Pull-Up (sink current: 4mA);
I-PU: 3.3V Input with Internal Pull-Up;
UTD: USB Downstream Facing Port Transceiver (supporting High/Full/Low-Speed);

USB 2.0 4-Port Hub
UTU: USB Upstream Facing Port Transceiver (supporting High/Full-Speed);

OSC: Crystal Oscillator (with integrated feedback resister, and crystal load capacitor);
P: Power/Ground.
Note 1 Crystal Requirements

Frequency accuracy: 12MHz 50ppm
Load capacitance: 16pF ~ 20pF

USB 2.0 4-Port Hub
APPLICATION ALTERNATIVES
The FE1.1s can be configured through board design options in one of three modes Individual
Port Active Indicator mode, Joint Port Active Indicator mode, and USB Charging Hub mode. Each
mode could incorporate an optional external serial EEPROM for customizing Vendor ID, Product
ID, Device Release Number, and number of ports. The detailed layout of EEPROM contents is
explained in the following section. All these options are implemented through four pins: DRV,
LED1, LED2, and TEST.
Individual Port Active Indicator Mode
In this mode, as shown by Fig. 3, FE1.1s supports 5 LED indicators one green LED for each
downstream port, and one red LED for hub active/suspend indication. The green light turns on
whenever a device is properly attached to its corresponding port, and turns off when the device is
disconnected or failed, or the hub itself being suspended. The red light turns on when the hub is
configured by the USB host, and turns off when it is detached or switched into suspend mode. All
LED's are optional and could be safely omitted without any side effects. The external EEPROM is
optionally hooked on TESTJ and LED1.
TESTJ SDA A0
SCL A1
Port 1 Indicator EEPROM A2
Gree n
LED1 Gre en
Port 3 Indicator
FE1.1s
Port 2 Indicator
Gree n
LED2 Gre en
Port 4 Indicator
DRV
Hub Active/Suspend
Red
Indicator
Fig. 4: Individual Port Indicator Configuration

USB 2.0 4-Port Hub
Joint Port Active Indicator Mode
The four downstream port indicators can be summarized into one single LED, as depicted in Fig. 4,
by tying LED2 to 3.3V. In this mode, the Joint Port Indicator will turn on whenever there is at least
one device attached to any of its downstream ports. The behavior of the Hub Active/Suspend
Indicator and the external serial EEPROM are remained the same.
3.3V
Gre en
Joint Port Indicator
TESTJ SDA A0
SCL A1
EEPROM A2
LED1
FE1.1s
LED2
DRV
Hub Active/Suspend
Re d
Indicator
Fig. 5: Joint Port Indicator Configuration
USB Charging Hub Mode
The major changes of FE1.1s Revision B from its predecessors are the new capabilities to support
GSMA Universal Charging Solution and USB-IF Battery Charging Specification Revision 1.1.
With the charging support enabled, the FE1.1s will be ready to respond to the charging requests
from portable devices no matter whether it is not connected to the host, the host being powered

USB 2.0 4-Port Hub
down, in normal operation, or in suspend. In other words, as long as the hub itself is adequately
powered, the charging function is independent to the status of the upstream port or the host
controller. Thus make it a full function USB Charging Hub. Figure 4 illustrates how the FE1.1s
being configured as USB Charging Hub mode by tying the DRV pin to 3.3V.
3.3V
Gree n Joint Port Indicator
TESTJ SDA A0
SCL A1
EEPROM A2
LED1
FE1.1s
LED2
Blue
DRV
Charging Request
Indicator
Fig. 6: USB Charging Hub
In this mode, the LED1 is the Joint Port Indicator which turns on whenever there are at least one
device connected to any of its downstream ports. And it turns off when all devices has been
disconnected, or itself is switched into suspend mode.
The LED2 will be the Charging Request Indicator which turns on when Charging Request is
detected on any of its downstream ports, or charging request handshake has been completed
successfully. It turns off when either all portable charging devices have been disconnected, or the
hub itself lost its adequate power source for charging the portable devices.

USB 2.0 4-Port Hub
The connect/disconnect status of the portable devices is detected through standard USB procedure.
That is, for Full/Low Speed devices, both D+ and D- of the corresponding downstream port been
detected as Single Ended Zero (SE0) for more than 2.5 s. For High Speed, through the detection
of removal of termination of D+ and D-. The status of power source for charging is indicated by
BUSJ. When BUSJ is low, the hub is Bus Powered, and presumably has been provided 500ma only,
which is barely enough to sustain the normal USB function of the hub plus 4 more Low Power
Device (100mA). In this case, Charging is certainly not allowed. When BUSJ is high, the hub is
Self Powered, and presumably has its own power source and has enough power for portable devices
to charge.
An optional external Serial EEPROM could still be hooked on LED1 and TESTJ to provide
alternate Product ID, Vendor ID, Device Release Number, and number of downstream ports if the
system designer would like some number less than 4.

USB 2.0 4-Port Hub
EEPROM CONTENTS
Address Contents Note

0x00 0x40 Constant, low byte of check code.
0x01 0x1A Constant, high byte of check code.
0x02 Vendor ID (Low) Low byte of Vendor ID, idVendor field of Standard Device Descriptor.
0x03 Vendor ID (High) High byte of Vendor ID.
0x04 Product ID (Low) Low byte of Product ID, idProduct field of Standard Device Descriptor.
0x05 Product ID (High) High Byte of Product ID.
0x06 Device Release (Low) Low byte of Device Release Number, must be Binary Coded Decimal,
bcdDevice field of Standard Device Descriptor.
0x07 Device Release (High) High byte of Device Release Number, must be Binary Coded Decimal.
0x08 ~ Filling All 0x00.
0x19
0x1A Port Number Number of Downstream Ports, bNbrPorts field of Hub Descriptor.
0x1B ~ Filling All 0x00.
0x1E
0x1F Check Sum The 8-bit sum of all value from 0x00 to 0x1E.
The first two bytes are the check code from the existence of EEPROM, their value must be 0x1A40.
Any other value would cause the EEPROM loading mechanism of FE1.1s to conclude that the
contents of this EEPROM is unusable, and use the default value instead.
The last byte, 0x1F, is a checksum made up of the sum of all value from 0x00 to 0x1E. The number
must match to render the contents of the EEPROM usable. Otherwise, the loading mechanism of
FE1.1s would discard the value from EEPROM and use default value instead.

USB 2.0 4-Port Hub
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min. Max. Unit

Storage Temperature TS -55 +150 C
Power Supply Voltage VDD5 -0.5 +6.0 V
VD33 -0.5 +4.0
ESD Human Body Mode -2000 +2000 V
ESD Machine Mode -200 +200 V
ESD Charged Device Mode -500 +500 V
Latch Up -200 +200 mA
Recommanded Operating Ranges

Parameter Symbol Min. Typ. Max. Unit
Operating Temperature TA 0 70 C
Operating Voltage VDD5 4.5 5.0 5.5 V
VD33 3.0 3.3 3.6
LOW level voltage of digital input VIL -0.3 0.8 V
HIGH level voltage of digital input VIH 2.0 5.5 V
Threshold voltage of digital input VTH 1.45 1.58 1.74 V
Low-to-High level of Schmitt-trigger input VT+ 1.44 1.5 1.74 V
High-to-Low level of Schmitt-trigger input VT- 0.89 0.94 0.99 V
LOW level voltage of digital output @4mA VOL 0.4 V
HIGH level voltage of digital output @4mA VOH 2.4 V
XIN input capacitance Cin 32 F
Internal Pull-Up Resister Range RPU 39 65 116 K

USB 2.0 4-Port Hub
POWER CONSUMPTION
ABSOLUTE MAXIMUM RATINGS

Symbol Condition Typical Unit
Active Host Devices
I_suspend Suspend 800 A
I_suspend_cm Suspend in Charging Mode 1300 A
Icc 4 High-Speed 4 x High-Speed 84 mA
High-Speed 4 x Full-Speed 41 mA
Full-Speed 4 x Full-Speed 28 mA
3 High-Speed 3 x High-Speed 73 mA
No Active High-Speed None 40 mA
Full-Speed None 28 mA
Note: The power consumption is measured when the bus is in IDLE state there is no activities
other than the Start-Of-Frame (SOF) and INTERRUPT-IN packets for the hub itself on the bus.
The peak power consumption varies depending upon the system configuration, type of operations,
and over-all bus utilization.

USB 2.0 4-Port Hub
PACKAGE I
28-pin SSOP (Body Size: 10x4 mm, Pitch: 0.64mm)

USB 2.0 4-Port Hub
PACKAGE II
24-pin WQFN (Body Size: 4x4 mm, Pitch: 0.5mm, Exposed Pad: 2.8x2.8mm)
Terminus Technology Inc.

1052, 10F, No. 3-2, YuanQu St., NanGang
Taipei City 115, TAIWAN, R.O.C.
www.terminus-tech.com

S i2 1 5 7- A3 0
W ORL DWIDE D IGITAL AND A NALO G TV TUNER
Features
Worldwide hybrid TV tuner Best-in-class real-world reception
Analog TV: NTSC, PAL/SECAM Exceeds MOPLL-based tuners
Digital TV: ATSC/QAM, DVB- Lowest phase noise
T2/T/C2/C, ISDB-T/C, DTMB High Wi-Fi and LTE immunity
42-1002 MHz frequency range Low power consumption
Industry-leading margin to A/74, 3.3 V and 1.8 V power supplies
NorDig, DTG, ARIB, EN55020, 3.3 V single-supply option
OpenCable Integrated power-on reset circuit
Lowest BOM for a hybrid TV tuner Single or separate output pins for
No balun at RF input ALIF/DLIF connection to SoC Ordering Information:
Integrated tracking filters requiring no Standard CMOS process See page 25.
external inductors or SAW filters 4 x 4 mm, 28-pin QFN package
Increased ESD protection on 6 pins RoHS compliant
Applications Pin Assignments
Hybrid -NIM tuner module Hybrid PVR and BDR recorder Si2157
iDTV (Integrated Digital TV) PC-TV accessories (Top View)
Hybrid terrestrial and cable STB
Description
The Si2157 is Silicon Labs' fifth-generation ion hybrid TV tuner supporting all
worldwide terrestrial and cable TV standards. Requiring no external balun, SAW
filters, wirewound inductors or LNAs, the
he Si2157 offers the lowest-cost BOM for a
hybrid TV tuner. Also included are an integrated power-on reset circuit and an
option for single power supply operation. As with prior-generation Silicon Labs TV
tuners, the Si2157 maintains very high linearity
earity and low noise to deliver superior
picture quality and a higher number of received stations when compared to other
silicon tuners and discrete MOPLL-based tuners. The Si2157 also incorporates a
harmonic-rejection mixer to deliver excellent Wi-Fi and LTE immunity. For the best
performance with next-generation digital TV standards such as DVB-T2/C2, the
Si2157 delivers industry-leading phase noise performance.
Functional Block Diagram

Patents pending
Confidential Rev. 0.2 1/13 Copyright 2013 by Silicon Laboratories Si2157-A30

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).

Si 2 1 5 7 -A 3 0
2 Confidential Rev. 0.2

Si21 57-A 30
T ABLE OF C ONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.1. Typical Hybrid TV Tuner Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2. Hybrid TV Receiver Application Using the Si2167/68/69 DVB-T2/T/C/S/S2
Demodulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.2. Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.3. Reference Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.4. Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.5. Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.7. Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.8. General Purpose Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.9. Reset, Powerup, Powerdown, and Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4. Programming Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2. Conceptual Example of a Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
8. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9.1. Si2157 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
10. Additional Reference Resources ces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Confidential Rev. 0.2 3

Si 2 1 5 7 -A 3 0
1. Electrical Specifications
Table 1. Recommended Operating Conditions*
Parameter Symbol Min Typ Max Unit

Analog High Supply Voltage VDD_H 3.15 3.3 3.6 V
Analog Low Supply Voltage VDD_L 1.7 1.8 1.9 V
Digital Supply Voltage VDD_D 1.7 1.8 1.9 V
I/O Supply Voltage VDD_IO 3.15 3.3 3.6 V
Ambient Temperature TA 20 25 85 C
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions
unless otherwise stated. Typical values apply at VDD_H = VDD_IO = 3.3 V, VDD_L = VDD_D = 1.8 V, and TA = 25 C.
Parameters are tested in production unless otherwise stated. Production firmware patch TBD or higher must be used
to guarantee all specifications.

Si21 57-A 30
Table 2. DC Characteristics1
(TA = 20 to 85 C)
Parameter Symbol Test Condition Min Typ Max Unit

2
Total Power Consumption PD ATV Mode, 0.509 TBD W
XOUT Enabled
ATV Mode, 0.496 TBD W
XOUT Disabled
DTV Mode, 0.497 TBD W
XOUT Enabled
DTV Mode, 0.484 TBD W
XOUT Disabled
High Voltage Supply Active Current2 IH XOUT Enabled 107 TBD mA
XOUT Disabled 103 TBD mA
Low Voltage Supply Active Current2 IL ATV Mode 87 TBD mA
DTV Mode 81 TBD mA
High Voltage Supply Standby Current3 ISH LNA on, XOUT 13 TBD mA
Enabled
LNA on, XOUT 9 TBD mA
Disabled
LNA off, XOUT 9 TBD mA
Enabled
LNA off, XOUT 5 TBD mA
Disabled
Low Voltage Supply Standby Current3 ISL 13 TBD mA
High Voltage Supply Powerdown Current4 IPDH 0.5 TBD mA
Low Voltage Supply Powerdown Current4 IPDL 0.1 TBD mA
I/O High Level Input Voltage5,6 VIH 0.7 x VIO VIO + 0.3 V
I/O Low Level Input Voltage5,6 VIL 0.3 0.3 x VIO V
I/O High Level Input Current5,7 IIH VIN = VIO = 3.6 V 10 10 A
I/O Low Level Input Current5,7 IIL VIN = 0 V, 10 10 A
VIO = 3.6 V
I/O High Level Output Voltage5,8 VOH IOUT = 500 A 0.8 x VIO V
I/O Low Level Output Voltage5,8 VOL IOUT = 500 A 0.2 x VIO V
Notes:
1. High Voltage Supply combines VDD_H and VDD_IO and is tested at 3.3 V for Typ and at 3.6 V for Max. Low Voltage
Supply combines VDD_L and VDD_D, and is tested at 1.8 V for Typ and at 1.9 V for Max.
2. Active currents are tested while the GET_REV command is issued continuously, which performs both writes and reads
over the I2C interface.
3. Measured after issuing the STANDBY command. LNA is enabled. GPIO1 and GPIO2 are disabled.
4. Measured after issuing the POWER_DOWN_HW command. XOUT, GPIO1 and GPIO2 are disabled.
5. VH, VL, VD, and VIO are the concise representations of VDD_H, VDD_L, VDD_D, and VDD_IO, respectively.
6. For input pins GPIO1, GPIO2, AGC1, AGC2, SCL, SDA, RSTB.
7. For input pins GPIO1, GPIO2, AGC1, AGC2, SCL, SDA.
8. For output pins GPIO1, GPIO2.

Si 2 1 5 7 -A 3 0
Table 3. Hybrid Tuner CharacteristicsTerrestrial Mode 1
(V H = 3.3 , VL = 1.8 V, VD = 1.8 V, TA = 20 to 85 C)

RF Input Frequency Range2,3 fIN 42 870 MHz
Input Return Loss RL 3 dB
4,5
Noise Figure NF VHF-L1, max gain 5.1 TBD dB
VHF-L2, max gain 3.7 TBD dB
VHF-H, max gain 3.7 TBD dB
UHF, max gain 3.8 TBD dB
In-Band IIP36 IIP3IB VHF-L1, VHF-L2, N1, 2 TBD 6 dBm
VHF-H, N1, 2 TBD 6 dBm
UHF, N1, 2 TBD 6 dBm
Out-of-Band IIP36 IIP3OOB VHF-L1, VHF-L2, N6, 12 TBD 4 dBm
VHF-H, N6, 12 TBD 3 dBm
UHF, N6, 12 TBD 2 dBm
VHF-L1, VHF-L2, N18, 36 +2 dBm
VHF-H, N18, 36 +5 dBm
UHF, N18, 36 +11 dBm
Adjacent Channel Attenua- N1 80 dB
tion7
Notes:
1. At the F-connector input of the Si2157 reference design, including all losses from connector and PCB, and excluding
CB trap and ESD/surge protection components. ZSOURCE= 75 . Refer to AN753: Si2157/47/27 Programming Guide
for details regarding programmable ranges and selection of terrestrial and cable modes. Frequency bands correspond
to: 42 to 103 MHz for VHF-L1, 104 to 190 MHz for VHF-L2, 191 to 470 MHz for VHF-H, and 471 to 870 MHz for UHF.
Measured with two series 270 nH ceramic multilayer chip inductors
in ductors in place of L1 and L2 in application circuit of
Figure 4.
2. From the lower edge of the lowest channel to the higher edge of the highest channel.
3. 43 to 870 MHz guaranteed by test, 42 MHz guaranteed by characterization.
4. Typ values reflect the average across each band under normal operating conditions. Max values indicate highest
noise figure point within each band under worst ca
case
se temperature, voltage, and process conditions.
5. Max values at worst case frequencies within the band. Guaranteed by production test.
6. Performed with AGC frozen at maximum RF gain and minimum minimum IF gain (zero RF gain backoff) using 6 MHz channel
spacing. Min values measured at worst case frequencies.
7. Attenuation of on-chip brickwall filter from RFIN to DLIF output, relative to a tone at center of desired channel (N).
Refer to Figure 7 on page 18 for a typical representation of the frequency response.
8. Guaranteed by characterization.
9. DTV modes.
10. Measured at DLIF_P/N pins. Alternatively, the DLIF output signal can be routed to the ALIF_P/N pins. Refer to
"AN753: Si2157/47/27 Programming Guide" for details.
11. Guaranteed by design.
12. Measured at ALIF_P/N pins.
13. Vppd amplitude, ATV_LIF_OUT:AMP property = 140, external AGC enabled with AGC voltage adjusted for 2 Vppd IF
amplitude.

Si21 57-A 30
Table 3. Hybrid Tuner CharacteristicsTerrestrial Mode (Continued)1
(V H = 3.3 , VL = 1.8 V, VD = 1.8 V, TA = 20 to 85 C)

LO Phase Noise at PNLO 1 kHz offset 100 TBD dBc/Hz
860 MHz8,9
10 kHz offset 100 TBD dBc/Hz
100 kHz offset 105 TBD dBc/Hz
1 MHz offset 132 TBD dBc/Hz
LO Integrated Phase Noise at PNint DSB: 125 Hz to 4 MHz Offset 0.25 TBD rms
860 MHz8,9 (47) (dBc)
DTV RSSI Measurement RSSID Input between 5 dBm and 3 dB
Accuracy 75 dBm; read 400 ms after
tune complete
DTV Tuner Output Driver10

DLIF Output Center LIF channel BW = 6 MHz 4 to 7 MHz
Frequency
channel BW = 7 MHz 4.5 to MHz
6.5
channel BW = 8 MHz 5 to 6 MHz
Differential Output VOD ac-coupled output 0.5 to Vppd
Voltage Swing 2.0
Load Resistance (each pin)11 RL ac-coupled output 1 k
Load Capacitance (each pin)11 CL ac-coupled output 50 pF
Notes:
in ductors in place of L1 and L2 in application circuit of
Figure 4.
noise figure point within each band under worst ca
case
se temperature, voltage, and process conditions.
7. Attenuation of on-chip brickwall filter from RFIN to DLIF output, relative to a tone at center of desired channel (N).
9. DTV modes.
10. Measured at DLIF_P/N pins. Alternatively, the DLIF output signal can be routed to the ALIF_P/N pins. Refer to
amplitude.

Si 2 1 5 7 -A 3 0
Table 3. Hybrid Tuner CharacteristicsTerrestrial Mode (Continued)1
(V H = 3.3 , VL = 1.8 V, VD = 1.8 V, TA = 20 to 85 C)
ATV Tuner Output Driver12

ALIF Output Center LIF channel BW = 6 MHz 4 to 7 MHz
Frequency
channel BW = 7 MHz 4.5 to MHz
6.5
channel BW = 8 MHz 5 to 6 MHz
Analog IF Spurious ALIFspur S=P, 4 MHz ALIF center TBD 72 dBc
Distortion13 frequency, inverted spectrum,
system M, Pd = 29 dBm,
40 pF CLOAD
Differential Output Voltage VOD ac-coupled output 0.5 to Vppd
Swing 2.0
Load Resistance (each pin)11 RL ac-coupled output 1 k
Load Capacitance (each pin)11 CL ac-coupled output 50 pF
Notes:
ductors in place of L1 and L2 in application circuit of
Figure 4.
noise figure point within each band under worst casese temperature, voltage, and process conditions.
7. Attenuation of on-chip brickwall filter from RFIN to DLIF output, relative to a tone
tone at center of desired channel (N).
9. DTV modes.
10. Measured at DLIF_P/N pins. Alternatively, the DLIF output
output signal can be routed to the ALIF_P/N pins. Refer to
amplitude.

Si21 57-A 30
Table 4. Hybrid Tuner RF CharacteristicsCable Mode1

(VH = 3.3 V, VL = 1.8 V, VD = 1.8 V, TA = 20 to 85 C)

2,3
RF Input Frequency Range fIN 42 1002 MHz
4
Input Return Loss RL 8 dB
5
Noise Figure NF VHF-L1, max gain 6.6 TBD dB
VHF-L2, max gain 5.0 TBD dB
VHF-H, max gain 5.2 TBD dB
UHF, max gain 5.3 TBD dB
UHF-C, max gain 6.4 TBD dB
Composite Triple Beat6 CTB Per OpenCable OCSP- 68 TBD dBc
6 HOST2.0-CFRIO3-050121
Composite Second Order CSO 68 TBD dBc
Cross Modulation6 XMODOC 62 TBD dBc
Notes:
1. Supersedes Table 3 when in Cable Mode. All other values in Table 3 apply to both Terrestrial and Cable Mode.
4. Across full frequency range.
5. Typ values reflect the average across each band under normal operating conditions. Max values indicate highest noise
figure point within each band under worst case temperature, voltage, and process
process conditions. Frequency bands
correspond to 42 to 103 MHz for VHF-L1, 104 to 190 MHz for VHF-L2, 191 to 470 MHz for VHF-H, 471 to 870 MHz for
UHF, and 871 to 1002 MHz for UHF-C.

Si 2 1 5 7 -A 3 0
Table 5. Reset Timing Characteristics

1
RSTB Pulse Width tSRST 5 s
2
Power-on Reset Enable Threshold VPOR_EN 1.7 V
2
Power-on Reset Disable Threshold VPOR_DI 2.9 V
Notes:
1. Internal power-on reset is disabled.
2. Threshold on VDD_IO.
tSRST
70%
30%
Figure 1. Reset Timing Parameter

Si21 57-A 30
Table 6. Control Interface Timing Characteristics1,2

SCL Frequency fSCL 0 400 kHz
SCL Low Time tLOW 1.3 s
SCL High Time tHIGH 0.6 s
SCL Input to SDA Setup (START) tSU:STA 0.6 s
SCL Input to SDA Hold (START) tHD:STA 0.6 s
SDA Input to SCL Setup tSU:DAT 100 ns
SDA Input to SCL Hold3,4 tHD:DAT 0 900 ns
SCL input to SDA Setup (STOP) tSU:STO 0.6 s
STOP to START Time t BUF 1.3 s
SDA Input, SCL Rise/Fall Time tf:IN 300 ns
tr:IN
SDA Output Fall Time tf:OUT 250 ns
SDA Capacitive Load Cb 50 pF
Input Filter Pulse Suppression tSP 50 ns
Notes:
1. The user must ensure that an I2C start condition (falling edge of SDA while SCL is high) does not occur within 300 ns
before the rising edge of RSTB.
2. The user must ensure that SCL is high during the rising edge of RSTB and stays high until after the first start condition.
3. The Si2157 delays SDA by a minimum of 300 ns from the VIH threshold of SCL to comply with the minimum tHD:DAT
specification.
4. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 kHz, tHD:DAT may be violated
as long as all other timing parameters are met.

Si 2 1 5 7 -A 3 0
tSU:STA tHD:STA tLOW tHIGH tr:IN tf:IN tSP tSU:STO tBUF
70%
SCL 30%
70%
SDA
30%
START tHD:DAT tSU:DAT tf:IN,

tr:IN STOP START
tf:OUT
Figure 2. Control Interface Read and Write Timing Parameters
SCL
A6-A0,
SDA D7-D0 D7-D0
R/W
START ADDRESS + R/W ACK DATA ACK STOP

Figure 3. Control Interface Read and Write Timing Diagram

Si21 57-A 30
Table 7. Crystal Oscillator and Output Clocks Characteristics
Parameter1 Symbol Test Condition Min Typ Max Unit
Crystal Oscillator Frequency fOSC 24 MHz

2
XOUT Output Amplitude VOUT 1.0 Vpp
XOUT Output Frequency fXOUT 24 MHz
RCLK Input Frequency f RCLK 24 MHz
RCLK Frequency Tolerance3 fRCLK 100 100 ppm
RCLK Input Amplitude VRCLK Sinusoidal clock 400 1200 mVpp
RCLK Jitter3,4 JRCLK 125 Hz to 12 MHz 2 ps rms
RCLK Input Capacitance CRCLK 3 pF
Notes:
1. Refer to AN652: Si21x8 Layout and Design Guidelines for details regarding clock schemes and requirements.
2. The XOUT signal is sinusoidal and measured with CL = 15 pF. XOUT may be used to drive the RCLK input of a
secondary tuner or an external demodulator.
3. Specifications for external clock source.
4. Total jitter on RCLK should be lower than 2 ps rms for less than 4 dB impact on synthesizer total phase noise.
Table 8. Thermal Conditions
Parameter Symbol Test Condition Value Unit
JA 34 C/W
Thermal Resistance*, Typical QFN-28
JC 5 C/W
Maximum Junction Temperature QFN-28 TJ Continuous 125 C
Storage Temperature TSTG 55 to +150 C
*Note: The thermal resistance values assume that the recommended printed circuit board layout guidelines are followed
correctly. The specified performance requires that the exposed
exposed pad be soldered to an exposed copper surface of at
least equal size and that a sufficient number of vias are added to enable ma
maximum
ximum heat transfer between the top-side
copper surface and a large internal/bottom copper plate.

Si 2 1 5 7 -A 3 0
Table 9. Absolute Maximum Ratings1
Parameter Symbol Min Max Unit

Analog High Supply Voltage VDD_H 0.3 3.9 V
Analog Low Supply Voltage VDD_L 0.3 2.0 V
Digital Supply Voltage VDD_D 0.3 2.0 V
I/O Supply Voltage VDD_IO 0.3 3.9 V
2
I/O Input Voltage VIN_IO 0.3 VDD_IO + 0.3 V
ADDR Pin Input Voltage VIN_A 0.3 VDD_H + 0.3 V
XTAL_I/RCLK Input Voltage3 VIN_RCLK 0.3 2.2 V
4
Input Current IIN 10 10 mA
HBM ESD Tolerance: (150pF, 330 )5 VHBM 2 2 kV
HBM ESD Tolerance: JS-001A-HBM-2011
VHBM 2 2 kV
(100 pF, 1.5 k 6
CDM ESD Tolerance: JESD22-C101E VCDM 750 750 V
MM ESD Tolerance: JESD22-A115C-MM VMM 200 200 V
Notes:
1. Permanent device damage may occur if the absolute maximum mum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
2. For input pins GPIO1, GPIO2, AGC1, AGC2, SCL, SDA, RSTB.
3. Other supplies must be active.
4. For input pins GPIO1, GPIO2, AGC1, AGC2, SCL, SDA.
5. For pins ALIF_P/N, DLIF_P/N, SDA, SCL.
6. For all pins except ALIF_P/N, DLIF_P/N, SDA, SCL.

Si21 57-A 30
2. Typical Application Schematics
Refer to "AN652: Si21x8 Layout and Design Guidelines" for additional details on application schematics, bill of
materials, and design/PCB guidelines.
2.1. Typical Hybrid TV Tuner Application
Figure 4. Hybrid TV Tuner Application Schematic
Table 10. Hybrid TV Tuner Application Bill of Materials

Component(s) Description Supplier(s)
C1 Capacitor, 47 pF, 5%, COG Various
C3, C4, C13 Capacitor, 180 pF, 5%, COG Various
C2, C5, C6, C7, C9, C10, C11 Capacitor, 1.2 nF, 20%, X7R Various
C8 Capacitor, 0.1 F, 20%, X7R Various
L1, L2 Multilayer chip inductor, 560 nH, or Various
Multilayer chip inductors, 2 x 270 nH in series
L3 Multilayer chip inductor, 180 nH Various
R1 Resistor, 0 Various
Y1 24 MHz crystal, 8 pF CLOAD Various
U1 Si2157 Worldwide Digital and Analog TV Tuner Silicon Laboratories

Si 2 1 5 7 -A 3 0
2.2. Hybrid TV Receiver Application Using the Si2167/68/69 DVB-T2/T/C/S/S2
Demodulators
Figure 5. Hybrid TV Receiver Application Schematic (Using the Si2167/68/69)
Table 11. Hybrid TV Receiver Application Bill of Materials (Using the Si2167/68/69)
Component(s) Description Supplier(s)
C3, C4, C13 Capacitor, 180 pF, 5%, COG Various
C2, C5, C6, C7, C9, C10, C11 Capacitor, 1.2 nF, 20%, X7R
Capacitor, Various
C8, C14, C15, C16, C17, C18, C19, Capacitor, 0.1 F, 20%, X7R Various
C20, C21, C22
L1, L2 Multilayer chip inductor, 560 nH, or Various
Multilayer chp inductors, 2 x 270 nH in series
L3 Multilayer chip inductor, 180 nH Various
R1 Resistor, 0 Various
R2, R3 Pull-up resistor, 4.7 k 5% Various
R4 Pull-down resistor, 10 k , 5% Various
Y1 24 MHz crystal, 8 pF CLOAD Various
U1 Si2157 Worldwide Digital and Analog TV Tuner Silicon Laboratories
U2 Si2167/68/69 DVB-T2/T/C/S/S2 Demodulator Silicon Laboratories

Si21 57-A 30
3. Functional Description
Figure 6. Functional Block Diagram

3.1. Overview The integrated LNA requires no external balun and
works in conjunction with an automatically-tuned,
The Si2157 is a complete hybrid TV tuner supporting all
integrated, high-Q tracking filter and RF AGC to provide
worldwide terrestrial and cable TV standards for digital
gain only within the passband of the tracking filter and to
and analog TV reception. The Si2157 requires no
minimize desensitization in the presence of strong out-
external balun and offers the lowest-cost BOM for a
of-band interferers. The tracking filter is completely
hybrid TV tuner. By combining Silicon Labs' proven
integrated within the Si2157 and is automatically tuned
digital low-IF architecture with a 4th-generation RF
for consistent performance across the RF input
front-end, the Si2157 maintains the highest
frequency range, temperature, aging, and component
performance that exceeds MOPLL-based tuners,
variation.
including industry-leading 2nd-order distortion
performance. A fully-integrated frequency synthesizer generates a
quadrature local oscillator for the harmonic and image
The Si2157 offers low power consumption as well as an
reject mixer, which downconv
downconverts the filtered RF input
option for single or dual power supply operation. Also
signal to a low-IF of approximately 3 MHz. The Si2157
included is an internal power-on reset circuit, eliminating
supports 6, 7, and 8 MHz channel bandwidths for all
the need for external brownout protection components
ATV and DTV modes. The Si2157 is also compliant with
or additional pins in module applications.
margin to Nordig 2.2.1 specifications for 1.7 and 5 MHz
The Si2157 is pin-compatible with the Si2178 hybrid TV DVB-T2 channel bandwidths. To use the Si2157 with
tuner with analog demodulator, providing customers 1.7 and 5 MHz DVB-T2 channel bandwidths, the Si2157
y. For module applications,
unparalleled design flexibility. should be configured for 6 MHz operation. All low-IF
the Si2157 offers high ESD protection on the pins processing and channel filtering is performed on-chip,
ALIF_P/N, DLIF_P/N, SDA and SCL. This improves eliminating the need for exter
external SAW filters. The final
ESD tolerance to 150 pF, 330 model tests without the channel filter is implemented with digital signal
need for additional external shunt diode components processing (DSP) and is programmable for customized
inside the module. response. The Video Filter Tool (VFT) enables rapid
3.2. Tuner customization of the integrated channel filter response
through an easy-to-use GUI application. Refer to the
The RF front-end is optimized for high linearity and low Si217x Video Filter Tool User's Guide for details. The
noise to achieve superior performance. Incorporating filter responses for ASTC/QAM, ISDB-T, DVB-T (7
worldwide field testing experience from three previous MHz), and DVB-T (8 MHz) and DTMB are shown in
tuner generations in high-volume production, the Figure 7.
Si2157 delivers the highest tolerance to real-world,
crowded field reception conditions.

Si 2 1 5 7 -A 3 0
The Si2157 autonomously controls RF and IF AGC to 3.4. Output Interface
optimize dynamic range. The time constants are
For digital TV (DTV), the output interface offers low-IF
selectable to support various AGC speeds. Both the
(LIF) differential connections to a DTV demodulator or
digital TV low-IF and analog TV low-IF output
SoC via the pins DLIF_P/DLIF_N. For analog TV (ATV),
amplitudes at the differential DLIF pins and ALIF pins,
the output interface offers low-IF (LIF) differential
respectively, are software programmable. Alternatively,
connections to an ATV demodulator of SoC via the pins
if the digital or analog demodulator requires the tuner to
ALIF_P/ALIF_N. A programming option allows both the
close its AGC loop, the DLIF or ALIF output amplitude
digital and the analog LIF signals to share the ALIF_P/N
can be adjusted with optional external analog inputs on
output pins enabling a single differential connection to
the AGC1 and AGC2 pins.
the ADC inputs of an SoC.
3.3. Reference Clock Generation 3.5. Supply Voltages
The Si2157 creates its own reference clock with an
The Si2157 has four internal supply domains. However,
integrated crystal oscillator, which requires only a low-
only two supply voltages are needed: 3.3 V and 1.8 V.
cost 24 MHz crystal. Discrete tuning capacitors should
The analog portions of the device are powered by high
not be used on the PCB. Instead, software-
and low voltage domains, VDD_H and VDD_L,
programmable on-chip tuning capacitors center the
respectively. The VDD_D supply powers the digital core.
crystal oscillator to compensate for different PCB
The digital input/output interface supply, VDD_IO,
parasitic capacitances.
provides voltage to the RSTB, GPIO1, GPIO2, AGC1,
For dual-tuner applications, the primary Si2157 can AGC2, XOUT, SDA and SCL pins.
provide a reference clock on its XOUT pin directly to the
A single 3.3 V voltage supply should be shared by the
XTAL_I pin of the secondary Si2157, thus saving the
VDD_IO and VDD_H pins. For single-supply operation,
cost and PCB area of one crystal. For these
the LDO_ADJ pin of the Si2157 can drive an external
applications, a capacitor of >300 pF should be
PNP transistor to provide 1.8 V to the VDD_D and
connected in series between the XOUT pin of the
VDD_L pins from the 3.3 V supply without the need for
primary tuner and the XTAL_I pin of the secondary
an external voltage regulator. The Si2157 may also be
tuner. The XOUT pin may also be used as a clock
powered with separate external power supplies for
source to a digital demodulator, analog demodulator or
3.3 V and 1.8 V. If an external 1.8 V power supply is
host processor.
Figure 7. Integrated Channel Filters (Eliminate External IF SAW Filters)

Si21 57-A 30
3.6. Control Interface For write operations, the user then sends an 8-bit data
2 byte on SDA, which is captured by the device on rising
An I C serial interface is provided for configuration and
edges of SCL. The Si2157 acknowledges each data
monitoring of the chip. The Si2157 supports a 7-bit
byte by driving SDA low for one cycle on the next falling
device addressing procedure. Individual data transfers
edge of SCL. The user may write any number of data
to and from the device are 8-bits. The device always
bytes in a single I2C transaction. The first byte is a
operates as a bus slave. In order for the I2C interface to
command, and the next bytes are arguments.
be active, the VDD_IO supply must be turned on.
For read operations, after the Si2157 has
The I2C bus uses the serial clock line (SCL) and serial
acknowledged the control byte, it drives an 8-bit data
data line (SDA) pins. The SDA and SCL pins are
byte on SDA, changing the state of SDA on the falling
powered by VDD_IO and support 3.3 V operation only. A
edge of SCL. The user acknowledges each data byte by
transaction begins with the START condition, which
driving SDA low for one cycle, on the next falling edge
occurs when SDA falls while SCL is high. Next, the user
of SCL. If a data byte is not acknowledged, the
drives an 8-bit control word serially on SDA, which is
transaction ends. The user may read any number of
captured by the device on rising edges of SCL. The
data bytes in a single I2C transaction. These bytes
control word consists of a seven bit device address
contain the response data from the Si2157.
followed by a read/write bit (read = 1, write = 0). The
Si2157 acknowledges the control word by driving SDA An I2C transaction ends with the STOP condition, which
low on the next falling edge of SCL. occurs when SDA rises while SCL is high.
The Si2157 responds to a single device address that The SDA and SCL pins do not include internal pull-up
can be changed with the ADDR pin. Four addresses are resistors and must always be pulled-high with external
available, allowing up to four Si2157 devices to share pull-up resistors to pin VDD_IO.
the same I2C serial bus. The 7-bit device address The Si2157 I2C control bus implements a fast I2C
consists of a fixed part (5 MSBs) followed by a interface (400 kHz).
programmable 2-bit part. The LSB of the device address Since the internal I2C state machine runs from the SCL
signals whether a read or write operation occurs. clock, there is no need for a high-speed clock. The I2C
The voltage on the ADDR pin is used to set the control interface always remains
remains active, even if the
programmable 2-bit part of the device address. The device is in powerdown mode. However, only a few
ADDR pin embeds both internal pull-down and pull-up commands are accessible during powerdown mode.
resistors to ground and VDD_H. The various I2C device For further details on the command interface, see
addresses can be selected with a single external "4. Programming Interface Description" on page 21.
resistor as summarized in Table 12.
3.7. Programming Interface
Table 12. I2C Device Address Selection The Si2157 uses a high level command API through the
I2C serial interface (the physi
physical layer in this case) to
device_address[7:0]
7:0] External ADDR Termination communicate with the host processor. This API is used
instead of basic register reads/writes to control the
[7:3] [2:1] [0]
device and set its operating modes. Details are provided
11000 11 R=1 ADDR tied directly to VDD_H in "4. Programming Interface Description" on page 21.
W=0
3.8. General Purpose Input/Output Pins
11000 10 R=1 ADDR tied to VDD_H Two multi-purpose pins (GPIO1 and GPIO2) are
W=0 through 220 k pull-up provided and can be configured using the
11000 01 R=1 ADDR tied to GND CONFIG_PINS command as inputs or as outputs
W=0 through 220 k pull-down driving Logic0 or Logic1 values. When configured as an
input, each GPIO pin maintains a 150 k pull-up to
11000 00 R=1 ADDR tied directly to GND VDD_IO. GPIO2 can also be programmed to operate as
W=0 a hardware interrupt pin that triggers on several internal
* Note: 5% resistor tolerance is sufficient.
events. Configuration of GPIO2 for the interrupt function
precludes its use as a GPIO.

Si 2 1 5 7 -A 3 0
3.9. Reset, Powerup, Powerdown, and The Si2157 contains a hardware powerdown mode that
Standby is enabled via a software API command. In hardware
powerdown mode, most of the analog and digital
Upon powerup, the Si2157 enters hardware reset circuitry is disabled, all of the programming interface
mode. At any time the Si2157 can also be placed into registers are reset to their default values, and only the
hardware reset mode by holding the level on the RSTB I2C bus remains active. With the Si2157 in hardware
pin low or through a software API command. Reset powerdown mode, a specific powerup software
mode disables the analog and digital circuitry and resets command must be issued over the I2C bus to power up
the registers to their default settings. When in hardware the device. At that point, the device enters powerup
reset mode, the crystal oscillator and XOUT pin remain mode and can respond to subsequent commands.
active, but all other I/O pins output 150 k pull-up to
VDD_IO. The Si2157 also supports a software standby mode. In
standby mode, most of the analog and digital circuitry is
The Si2157 contains an internal power-on reset (POR) disabled, but the LNA can be programmed on or off and
circuit that automatically places the Si2157 into the XOUT clock can be programmed on or off
hardware reset when the VDD_IO voltage falls below a individually using software commands. In software
predetermined threshold. The POR may be overridden standby mode, all of the registers retain their current
by driving the RSTB pin high or low. The RSTB pin must settings. The software standby mode is enabled and
be driven with an impedance of less than 2K ohms in disabled by issuing commands over the programming
order to override the POR circuit. If the POR circuit is interface.
not used, the RSTB pin must be set high after being
held low for a minimum time of tSRST. Refer to
Figure 1, Reset Timing Parameter, on page 10. Use of
the RSTB pin is optional and this pin should be left
floating if unused.
The Si2157 remains in hardware reset mode until a
software API command is issued to release the
hardware reset. The hardware reset mode cannot be
released until the POR circuit detects the appropriate
power supply voltage levels or the RSTB pin is driven
high.

Si21 57-A 30
4. Programming Interface 4.2. Conceptual Example of a Command
Description In order to illustrate the usage and format of a typical
command, a conceptual example command,
The Si2157 provides a simple yet powerful software GENERIC_COMMAND, is described below (note that
command API programming interface to program the GENERIC_COMMAND is not an actual command). The
various modes and blocks of the chip, reducing format of this description of GENERIC_COMMAND
development time while offering maximum flexibility. shown below is similar to what is used in "AN753:
The device is programmed using API commands. Si2157/47/27 Programming Guide for all commands
and properties.
4.1. Programming with Commands
The 8-bit OPCODE of the command,
To perform an action, the user writes a command GENERIC_COMMAND, is N. GENERIC_COMMAND
OPCODE byte followed by its associated fields (packed contains three argument bytes and two response bytes.
in byte-sized arguments). This will cause the chip to The three argument bytes contain four fields (FIELD_A,
execute the given command. Commands control FIELD_B, FIELD_C, and FIELD_D) as shown in the
actions, such as powering up the device, shutting down Command table on page 22. The field definitions and
the device, or tuning to a channel. Fields are specific to values are described in the second table. The response
a given command and are used to alter the behavior of for GENERIC_COMMAND contains a STATUS byte,
the command. For example, the TUNER_TUNE_FREQ which is always the same for all commands. The
command uses fields to define the center frequency of response contains two bytes (specific to
the desired channel. Every command posts a response GENERIC_COMMAND) in the form of two fields
that can be retrieved to check the status. At a minimum, (FIELD_E and FIELD_F), as shown in the third table on
all commands provide a one-byte reply containing fields page 22. The response field definitions and values are
describing status information. described in the last table.
While commands issue immediate actions, static
configuration information is set using properties.
Properties modify the default chip operation, but
immediate execution is not guaranteed. To set a
property, the host needs to issue the SET_PROPERTY
command, which will load the given property into the
chip. This new property will subsequently be taken into
account when the chip or another command requires
the information related to that property.
An example of a property is DTV_MODE, which has a
field that defines the channell bandwidth to be 6, 7, or
8 MHz.
A list of all commands and properties, their full
descriptions, and their detailed usage is explained in the
application note "AN753: Si2157/47/27 Programming
Guide.

Si 2 1 5 7 -A 3 0
Command 0xN GENERIC_COMMAND
GENERIC_COMMAND performs the following function.

<detailed description of command including description of fields>
Command Arguments: Three
Response Bytes: Two
Command
Bit D7 D6 D5 D4 D3 D2 D1 D0
CMD N7 N6 N5 N4 N3 N2 N1 N0
ARG1 0 0 0 0 0 FIELD_B FIELD_A
ARG2 0 0 0 0 FIELD_C
ARG3 FIELD_D
Bit Name Function

<Title of FIELD_A>
0 = <description of value>
ARG1
FIELD_A[1:0] 1 = <description of value>
1:0
2 = ...
<Description of FIELD_A>
<Title of FIELD_B>
ARG1
FIELD_B <description of values>
2
<Description of FIELD_B>
<Title of FIELD_C>
ARG2
FIELD_C[3:0] <description of values>
3:0
<Description of FIELD_C>
<Title of FIELD_D>
ARG3
FIELD_D <description of values>
7:0
Description of FIELD_D>
<Description FIELD_D>
Response
Bit D7 D6 D5 D4 D3 D2 D1 D0
STATUS standard response for all commands for STATUS>
<standard
RESP1 X X X X FIELD_E
RESP2 FIELD_F
Bit Name Function

<Title of FIELD_E>
RESP1
FIELD_E[3:0] <description of values>
3:0
<Description of FIELD_E>
<Title of FIELD_F>
RESP2
FIELD_F[7:0] <description of values>
7:0
<Description of FIELD_F>

Si21 57-A 30
5. Pin Descriptions

Si 2 1 5 7 -A 3 0
Table 13. Si2157 Pin Descriptions

Pin Number(s) Name I/O Description
1* GPIO1 I/O General purpose input/output #1
2* GPIO2 I/O General purpose input/output #2
3* AGC2 I ALIF/DLIF output amplitude control input #2 (optional)
4 SCL I I2C clock input
5 SDA I/O I2C data input/output
6 VDD_IO S I/O supply voltage, 3.3 V
7 GND S Ground. Connect GND pins to GND_PAD.
8 VDD_D S Digital supply voltage, 1.8 V
9* DLIF_N O DLIF differential output to DTV demodulator (negative)
10 VDD_H S Analog high supply voltage, 3.3 V
11* DLIF_P O DLIF differential output to DTV demodulator (positive)
12* ALIF_N O ALIF differential output to SoC or ATV demodulator (negative)
13* ALIF_P O ALIF differential output to SoC or ATV demodulator (positive)
14 VDD_L S Analog low supply voltage, 1.8 V
15* LDO_ADJ O Control output for external PNP transistor used for single-supply opera-
tion
16* XOUT O Output reference clock to secondary tuner or receiver
17 XTAL_I I Crystal pin 1 (or RCLK input driven by XOUT of another tuner or
receiver)
18* XTAL_O O Crystal pin 2 (leave floating if XTAL_I is driven by XOUT of another
tuner or receiver)
19 GND S Ground. Connect GND pins to GND_PAD.
22 RF_REF O RF reference voltage output
23 RF_IP I RF input (positive)
24 RF_IN I RF input (negative)
25 RF_SHLD S RF input shield
26 ADDR I I2C address select
27* RSTB I Hardware reset (active low)
28* AGC1 I ALIF/DLIF output amplitude control input #1 (optional)
*Note: Pin should be left floating if unused.

Si21 57-A 30
6. Ordering Guide
Part Number* Description Package Operating

Type Temperature
Si2157-A30-GM Worldwide Digital and Analog Tuner for NTSC, -pin QFN, 20 to 85 C
PAL/SECAM, ATSC/QAM, DVB-T2/T/C2/C, ISDB-T/C, RoHS-compliant
DTMB
*Note: Add an R at the end of the device part number to denote tape and reel option. The "A" denotes product revision A
and "30" denotes firmware version 3.0. Production firmware TBD or higher must be used to guarantee all
specifications.

Si 2 1 5 7 -A 3 0
7. Package Outline
Figure 8 illustrates the package details for the Si2157. Table 14 lists the values for the dimensions shown in the
illustration.
PIN#1 I .D.
(LAS ER M ARK)
Pin #1 ID
4X cxc
e
B eee C A B
C
S EAT ING PLA NE DETAIL "A"
ddd C A B
Figure 8. 28-Pin Quad Flat No-Lead (QFN)
Table 14. Package Dimensions

Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A 0.80 0.85 0.90 E2 2.40 2.50 2.60
A1 0.00 0.02 0.05 f 3.50 BSC
b 0.18 0.25 0.30 L 0.30 0.40 0.50
c 0.27 0.32 0.37 aaa 0.10
D 4.00 BSC bbb 0.10
D2 2.40 2.50 2.60 ccc 0.08
e 0.50 BSC ddd 0.10
E 4.00 BSC eee 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Si21 57-A 30
8. PCB Land Pattern
Figure 9 illustrates the PCB land pattern details for the Si2157. Table 15 lists the values for the dimensions shown
in the illustration.
Figure 9. PCB Land Pattern
Table 15. PCB Land Pattern

Symbol Millimeters Symbol Millimeters
Nom Max Nom Max
P1 2.6 C1 3.9
P2 2.6 C2 3.9
W 0.43 E 0.5
X1 0.3 F1 3.61
Y1 0.85 F2 3.61
Notes:
General
1. All dimensions shown are in millimeters
mill imeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center
ground pad.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.

Si 2 1 5 7 -A 3 0
9. Top Marking
9.1. Si2157 Top Marking
9.2. Top Marking Explanation
Mark Method Laser

Font Size: 0.60 mm (24 mils)
Line 1 Marking Device Number 2157
ZZ = Firmware Revision
Line 2 Marking TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form.
Line 3 Marking Circle = 0.5 mm Diameter Pin 1 identifier
(Bottom-left justified)
YY = Year Assigned by the Assembly Hous
House.e. Corresponds to the year
WW = Work Week and work week of the mold date.

Si21 57-A 30
10. Additional Reference Resources
Si2157 Evaluation Board GUI User Manual
AN753: Si2157/47/27 Programming Guide
AN652: Si21x8 Layout and Design Guidelines
AN737: Si21xx Tuner Test Procedures
Si217x Video Filter Tool Users Guide
Si2169 Multi-Media DVB-T2/T/C/S/S2 Demodulator Data Sheet
Si2168 Multi-Standard DVB-T2/T/C Demodulator Data Sheet
Si2167 Multi-Media DVB-T/C/S/S2 Demodulator Data Sheet
Si215x Customer Support Email: DTVinfo@silabs.com.

Si 2 1 5 7 -A 3 0
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: DTVinfo@silabs.com
Internet: www.silabs.com
Patent Notice
Silicon Labs invests in research and development to help our cust
customers
omers differentiate in the market with innovative low-power, ssmall size, analog-
intensive mixed-signal solutions.
ons. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-clas
world-class engineering team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran-
ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intend-
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application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

Rev. 0.2, May. 2010
K9F2G08U0C
Advance
2Gb C-die NAND Flash

Single-Level-Cell (1bit/cell)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2010 Samsung Electronics Co., Ltd. All rights reserved.
-1-
Advance Rev. 0.2
K9F2G08U0C datasheet FLASH MEMORY

Revision History
Revision No. History Draft Date Remark Editor
0.0 1. Initial issue Aug. 12, 2009 Advance -
0.1 1. DC Parameter is chagned Dec. 09, 2009 Advance -

2. Typo is modified
0.2 1. Max tR value has changed from 35us to 40us May. 03, 2010 Advance H.K.Kim
2. Min tRC/ tWC value has changed from 30ns to 25ns
3. Chapter 2.9, 2.10 AC parameters revised
4. Chapter 2.3 ISB2 MAX value has changed from 50 to 80
5. Chapter 7.0 2plane Erase NOT supported.
6. Chapter 2.8 tDBSY value has changed.
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact
the SAMSUNG branch office near your office.
-2-
Rev. 0.2

Table Of Contents
1.0 INTRODUCTION ........................................................................................................................................................ 4
1.1 Product List.............................................................................................................................................................. 4
1.2 Features ...........................................................................................................................................................4
1.3 General Description................................................................................................................................................. 4
1.4 Pin Configuration (TSOP1) ...................................................................................................................................... 5
1.4.1Package Dimensions ......................................................................................................................................... 5
1.5 Pin Configuration (FBGA) ........................................................................................................................................ 6
1.5.1Package Dimensions ......................................................................................................................................... 7
1.6 Pin Description ........................................................................................................................................................ 8
2.0 PRODUCT INTRODUCTION...................................................................................................................................... 9
2.1 Absolute Maximum Ratings ..................................................................................................................................... 10
2.2 Recommended Operating Conditions ..................................................................................................................... 10
2.3 DC And Operating Characteristics(Recommended operating conditions otherwise noted.) ................................... 10
2.4 Valid Block............................................................................................................................................................... 11
2.5 AC Test Condition ................................................................................................................................................... 11
2.6 Capacitance(TA=25C, VCC= 3.3V, f=1.0MHz) ...................................................................................................... 11
2.7 Mode Selection........................................................................................................................................................ 11
2.8 Program / Erase Characteristics ........................................................................................................................12
2.9 AC Timing Characteristics for Command / Address / Data Input ............................................................................ 12
2.10 AC Characteristics for Operation........................................................................................................................... 13
3.0 NAND FLASH TECHNICAL NOTES .......................................................................................................................... 14
3.1 Initial Invalid Block(s) ............................................................................................................................................... 14
3.2 Identifying Initial Invalid Block(s) ............................................................................................................................. 14
3.3 Error In Write Or Read Operation ............................................................................................................................ 15
3.4 Addressing for Program Operation .......................................................................................................................... 17
4.0 SYSTEM INTERFACE USING CE DONT-CARE. ..................................................................................................... 18
4.1 Command Latch Cycle ............................................................................................................................................ 19
4.2 Address Latch Cycle................................................................................................................................................ 19
4.3 Input Data Latch Cycle ............................................................................................................................................ 20
4.4* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)....................................................................................... 20
4.5 Status Read Cycle .................................................................................................................................................. 21
4.6 Read Operation ....................................................................................................................................................... 21
4.7 Read Operation(Intercepted by CE) ........................................................................................................................ 22
4.8 Random Data Output In a Page ............................................................................................................................. 23
4.9 Page Program Operation......................................................................................................................................... 24
4.10 Page Program Operation with Random Data Input ............................................................................................... 25
4.11 Copy-Back Program Operation With Random Data Input .................................................................................... 26
4.12 Two- Plane Page Program operatoin .................................................................................................................... 27
4.13 Block Erase Operation........................................................................................................................................... 28
4.14 Read ID Operation................................................................................................................................................. 28
5.0 DEVICE OPERATION ................................................................................................................................................ 31
5.1 Page Read............................................................................................................................................................... 31
5.2 Page Program ......................................................................................................................................................... 33
5.3 Copy-back Program................................................................................................................................................. 34
5.4 Read Status............................................................................................................................................................. 35
5.5 Read ID ................................................................................................................................................................... 36
5.6 Reset ....................................................................................................................................................................... 36
5.7 READY/BUSY ......................................................................................................................................................... 37
6.0 DATA PROTECTION & POWER UP SEQUENCE.................................................................................................... 38
7.0 BACKWARD COMPATIBILITY INFORMATION......................................................................................................... 39
-3-
Advance Rev. 0.2

1.0 INTRODUCTION
1.1 Product List
Part Number Vcc Range Organization PKG Type
K9F2G08U0C-S 2.7 ~ 3.6v x8 TSOP1
K9F2G08U0C-H 2.7 ~ 3.6v x8 63 FBGA
1.2 Features
Voltage Supply Fast Write Cycle Time
- 3.3V device(K9F2G08U0C): 2.70V ~ 3.60V - Page Program time : 250s(Typ.)
Organization - Block Erase Time : 2ms(Typ.)
- Memory Cell Array : (256M + 8M) x 8bit Command/Address/Data Multiplexed I/O Port
- Data Register : (2K + 64) x 8bit Hardware Data Protection
Automatic Program and Erase - Program/Erase Lockout During Power Transitions
- Page Program : (2K + 64)Byte Reliable CMOS Floating-Gate Technology
- Block Erase : (128K + 4K)Byte -Endurance & Data Retention : Refor to the gualification report
Page Read Operation -ECC regnirement : 1 bit / 528bytes Command Driven Operation
- Page Size : (2K + 64)Byte Unique ID for Copyright Protection
- Random Read : 40s(Max.) Package :
- Serial Access : 25ns(Min.) - K9F2G08U0C-SCB0/SIB0 : Pb-FREE PACKAGE
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F2G08U0C-HCB0/HIB0 : Pb-FREE PACKAGE
63 - ball FBGA (9 x 11 / 0.8 mm pitch)
1.3 General Description

Offered in 256Mx8bit, the K9F2G08U0C is a 2G-bit NAND Flash Memory with spare 64M-bit. Its NAND cell provides the most cost-effective solution for
the solid state application market. A program operation can be performed in typical 250s on the (2K+64)Byte page and an erase operation can be per-
formed in typical 2ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for
address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repeti-
tion, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F2G08U0Cs
extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F2G08U0C is
an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
-4-
Advance Rev. 0.2

1.4 Pin Configuration (TSOP1)
K9F2G08U0C-SCB0/SIB0
N.C 1 48 N.C
N.C 2 47 N.C
N.C 3 46 N.C
N.C 4 45 N.C
N.C 5 44 I/O7
N.C 6 43 I/O6
R/B 7 42 I/O5
RE 8 41 I/O4
CE 9 40 N.C
N.C 10 39 N.C
N.C 11 48-pin TSOP1 38 N.C
Vcc 12 37 Vcc
Vss 13 Standard Type 36 Vss
N.C 14 35 N.C
N.C 15 12mm x 20mm 34 N.C
CLE 16 33 N.C
ALE 17 32 I/O3
WE 18 31 I/O2
WP 19 30 I/O1
N.C 20 29 I/O0
N.C 21 28 N.C
N.C 22 27 N.C
N.C 23 26 N.C
N.C 24 25 N.C
1.4.1 Package Dimensions

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F Unit :mm/Inch
MAX
20.000.20
0.004
0.10
0.7870.008
+0.003
0.008-0.001
+0.07
#1
0.20 -0.03
#48
( 0.25 )
0.010
0.488 MAX
12.00
0.472
12.40
0.0197
0.50
#24 #25
1.000.05 0.05
0.0390.002 0.002 MIN
1.20
0.010 TYP
+0.075
18.400.10 0.047MAX
0.125 0.035
+0.003
0.005-0.001
0.7240.004
0.25
0~8
0.45~0.75
0.018~0.030 ( 0.50 )
0.020
-5-
Advance Rev. 0.2

1.5 Pin Configuration (FBGA)
K9F2G08U0C-HCB0/HIB0
Top View
1 2 3 4 5 6
N.C N.C N.C N.C
N.C N.C N.C

A
/WP ALE Vss /CE /WE R/B
B
NC /RE CLE NC NC NC
C
NC NC NC NC NC NC
D
NC NC NC NC NC NC
E
NC NC NC NC NC NC
F
NC I/O0 NC NC NC Vcc
G
NC I/O1 NC Vcc I/O5 I/O7
H
Vss I/O2 I/O3 I/O4 I/O6 Vss
N.C N.C N.C N.C
N.C N.C N.C N.C
-6-
Advance Rev. 0.2

1.5.1 Package Dimensions
63-Ball FBGA (measured in millimeters)
Top View Bottom View

9.000.10 A
0.80 x 9= 7.20
0.80 x 5= 4.00
9.000.10 0.80 B
(Datum A) 6 5 4 3 2 1
0.80
#A1
A
B
(Datum B) C
0.80 x11= 8.80

0.80 x7= 5.60
11.000.10
11.000.10
D
E
2.80
F
G
H
63-0.450.05
0.20 M A B 2.00
1.00(Max.)
0.25(Min.)
Side View
9.000.10
0.10MAX
0.450.05
-7-
Advance Rev. 0.2

1.6 Pin Description
Pin Name Pin Function
DATA INPUTS/OUTPUTS
I/O0 ~ I/O7 The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to
high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
CLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are
latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising
edge of WE with ALE high.
CHIP ENABLE
CE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does
not return to standby mode in program or erase operation.
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the fall-
ing edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
WRITE PROTECT
WP The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is
reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read
R/B
operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z con-
dition when the chip is deselected or when outputs are disabled.
POWER
Vcc
VCC is the power supply for device.
Vss GROUND
NO CONNECTION
N.C
Lead is not internally connected.
NOTE :
Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
-8-
Advance Rev. 0.2

2.0 PRODUCT INTRODUCTION
NAND Flash Memory has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities
by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low.
Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address
respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc. require just one cycle
bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution..
Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the
three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific
commands of the K9G2G08U0C.
[Table 1] Command Sets

Function 1st Cycle 2nd Cycle Acceptable Command during Busy
Read 00h 30h
Read for Copy Back 00h 35h
Read ID 90h -
Reset FFh - O
Page Program 80h 10h
Copy-Back Program 85h 10h
Two-Plane Page Program(2) 80h---11h 81h---10h
Block Erase 60h D0h
Random Data Input (1) 85h -
Random Data Output (1) 05h E0h
Read Status 70h - O
Read Status 2 F1h - O
NOTE :
1) Random Data Input/Output can be executed in a page.
2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
Caution :
Any undefined command inputs are prohibited except for above command set of Table 1.
-9-
Advance Rev. 0.2

2.1 Absolute Maximum Ratings
Parameter Symbol Rating Unit
VCC -0.6 to +4.6
Voltage on any pin relative to VSS VIN -0.6 to +4.6 V
VI/O -0.6 to Vcc + 0.3 (< 4.6V)
K9F2G08U0C-XCB0 -10 to +125
Temperature Under Bias TBIAS C
K9F2G08U0C-XIB0 -40 to +125
K9F2G08U0C-XCB0
Storage Temperature TSTG -65 to +150 C
K9F2G08U0C-XIB0
Short Circuit Current IOS 5 mA
NOTE :
1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.2 Recommended Operating Conditions

(Voltage reference to GND, K9F2G08U0C-XCB0 :TA=0 to 70C, K9F2G08U0C-XIB0:TA=-40 to 85C)
3.3V
Min Typ. Max
Supply Voltage VCC 2.7 3.3 3.6 V
Supply Voltage VSS 0 0 0 V
2.3 DC And Operating Characteristics(Recommended operating conditions otherwise noted.)

3.3V
Parameter Symbol Test Conditions Unit
Min Typ Max
Page Read with Serial tRC=25ns
ICC1
Operating Access CE=VIL, IOUT=0mA
Current - 20 35
Program ICC2 - mA
Erase ICC3 -
Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC - - 1
Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=0V/VCC - 10 80
Input Leakage Current ILI VIN=0 to Vcc(max) - - 10 A
Output Leakage Current ILO VOUT=0 to Vcc(max) - - 10
Input High Voltage VIH(1) - 0.8xVcc - Vcc+0.3
Input Low Voltage, All inputs V IL(1) - -0.3 - 0.2xVcc
K9F2G08B0C: IOH=-100A V
Output High Voltage Level VOH 2.4 - -
K9F2G08U0C: IOH=-400A
K9F2G08B0C: IOL=100A
Output Low Voltage Level VOL - - 0.4
K9F2G08U0C: IOL=2.1mA
K9F2G08B0C: VOL=0.1V
Output Low Current(R/B) IOL(R/B) 8 10 - mA
K9F2G08U0C: VOL=0.4V
NOTE :
1) VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
2) Typical value is measured at Vcc= 3.3V, TA=25C. Not 100% tested.
- 10 -
Advance Rev. 0.2

2.4 Valid Block
Parameter Symbol Min Typ. Max Unit
K9F2G08U0C NVB 2,008 - 2,048 Blocks
NOTE :
1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both
cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the
attached technical notes for appropriate management of invalid blocks.
2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.
3) The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.
2.5 AC Test Condition

(K9F2G08U0C-XCB0 :TA=0 to 70C, K9F2G08U0C-XIB0:TA=-40 to 85C, K9F2G08U0C: Vcc=2.7V~3.6V unless otherwise noted)
Parameter K9F2G08U0C
Input Pulse Levels 0V to Vcc
Input Rise and Fall Times 5ns
Input and Output Timing Levels Vcc/2
Output Load 1 TTL GATE and CL=50pF
2.6 Capacitance(TA=25C, VCC= 3.3V, f=1.0MHz)

Item Symbol Test Condition Min Max Unit
Input/Output Capacitance CI/O VIL=0V - 10 pF
Input Capacitance CIN VIN=0V - 10 pF
NOTE :
Capacitance is periodically sampled and not 100% tested.
2.7 Mode Selection

CLE ALE CE WE RE WP Mode
H L L H X Command Input
Read Mode
L H L H X Address Input(5clock)
H L L H H Command Input
Write Mode
L H L H H Address Input(5clock)
L L L H H Data Input
L L L H X Data Output
X X X X H X During Read(Busy)
X X X X X H During Program(Busy)
X X X X X H During Erase(Busy)
X X (1) X X X L Write Protect
X X H X X 0V/VCC(2) Stand-by
NOTE :
1) X can be VIL or VIH.
2) WP should be biased to CMOS high or CMOS low for standby.
- 11 -
Advance Rev. 0.2

2.8 Program / Erase Characteristics
Program Time tPROG - 250 750 s
Dummy Busy time for Two-Plane Page Program tDBSY - 2.5 3 s
Number of Partial Program Cycles Nop - - 4 cycles
Block Erase Time tBERS - 2 10 ms
NOTE :
1) Typical value is measured at Vcc=3.3V, TA=25C. Not 100% tested.
2) Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25C temperature.
2.9 AC Timing Characteristics for Command / Address / Data Input

CLE Setup Time t CLS(1) 12 - ns
CLE Hold Time tCLH 5 - ns
CE Setup Time t CS(1) 20 - ns
CE Hold Time tCH 5 - ns
WE Pulse Width tWP 12 - ns
ALE Setup Time tALS(1) 12 - ns
ALE Hold Time tALH 5 - ns
Data Setup Time tDS(1) 12 - ns
Data Hold Time tDH 5 - ns
Write Cycle Time tWC 25 - ns
WE High Hold Time tWH 10 - ns
Address to Data Loading Time tADL(2) 100 - ns
NOTE :
1) The transition of the corresponding control pins must occur only once while WE is held low
2) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle
- 12 -
Advance Rev. 0.2

2.10 AC Characteristics for Operation
Data Transfer from Cell to Register tR - 40 s
ALE to RE Delay tAR 10 - ns
CLE to RE Delay tCLR 10 - ns
Ready to RE Low tRR 20 - ns
RE Pulse Width tRP 12 - ns
WE High to Busy tWB - 100 ns
Read Cycle Time tRC 25 - ns
RE Access Time tREA - 20 ns
CE Access Time tCEA - 25 ns
RE High to Output Hi-Z tRHZ - 100 ns
CE High to Output Hi-Z tCHZ - 30 ns
CE High to ALE or CLE Dont Care tCSD 10 - ns
RE High to Output Hold tRHOH 15 - ns
CE High to Output Hold tCOH 15 - ns
RE High Hold Time tREH 15 - ns
Output Hi-Z to RE Low tIR 0 - ns
RE High to WE Low tRHW 100 - ns
WE High to RE Low tWHR 60 - ns
Device Resetting Time(Read/Program/Erase) tRST - 5/10/500(1) s
NOTE :
1) If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5s.
- 13 -
Advance Rev. 0.2

3.0 NAND FLASH TECHNICAL NOTES
3.1 Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information
regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices
with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it
is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via
address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte
ECC.
3.2 Identifying Initial Invalid Block(s)

All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s)
status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at
the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has
been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create
the initial invalid block table via the following suggested flow chart(Figure 1). Any intentional erasure of the original initial invalid block information is pro-
hibited.
Start
Set Block Address = 0
Increment Block Address

Check "FFh" at the column address 2048
* of the 1st and 2nd page in the block
Create (or update) No
Check "FFh"
Initial
Invalid Block(s) Table
Yes
No
Last Block ?
Yes
End
[Figure 1] Flow chart to create initial invalid block table
- 14 -
Advance Rev. 0.2

NAND Flash Technical Notes (Continued)
3.3 Error In Write Or Read Operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following pos-
sible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replace-
ment should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block
replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest
of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verifica-
tion failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those
reclaimed blocks.
Failure Mode Detection and Countermeasure sequence

Erase Failure Status Read after Erase --> Block Replacement
Write
Program Failure Status Read after Program --> Block Replacement
Read Single Bit Failure Verify ECC -> ECC Correction
ECC : Error Correcting Code --> Hamming Code etc.

Example) 1bit correction & 2bit detection
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ? No
or R/B = 1 ?
Yes
* No
Program Error I/O 0 = 0 ?
Yes
Program Completed
: If program operation results in an error, map out

* the block including the page in error and copy the
target data to another block.
- 15 -
Advance Rev. 0.2

NAND Flash Technical Notes (Continued)
Erase Flow Chart Read Flow Chart
Start Start
Write 60h Write 00h
Write Block Address Write Address
Write D0h Write 30h
Read Status Register Read Data
ECC Generation
I/O 6 = 1 ? No
or R/B = 1 ?
No
Yes Reclaim the Error Verify ECC
* No
Yes
Erase Error I/O 0 = 0 ?
Page Read Completed

Yes
Erase Completed
: If erase operation results in an error, map out

* the failing block and replace it with another block.
Block Replacement
Block A
1st
{

(n-1)th 1
nth an error occurs.
(page) Buffer memory of the controller.
Block B
1st
{

2
(n-1)th
nth
(page)
* Step1
When an error happens in the nth page of the Block A during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block B)
* Step3
Then, copy the nth page data of the Block A in the buffer memory to the nth page of the Block B.
* Step4
Do not erase or program to Block A by creating an invalid block table or other appropriate scheme.
- 16 -
Advance Rev. 0.2

3.4 Addressing for Program Operation
Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages
of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed.
Therefore, LSB doesn't need to be page 0.
Page 63 (64) Page 63 (64)
: :
Page 31 (32) Page 31 (1)

: :
Page 2 (3) Page 2 (3)

Page 1 (2) Page 1 (32)
Page 0 (1) Page 0 (2)
Data register Data register
From the LSB page to MSB page Ex.) Random page program (Prohibition)
DATA IN: Data (1) Data (64) DATA IN: Data (1) Data (64)
- 17 -
Advance Rev. 0.2

4.0 SYSTEM INTERFACE USING CE DONT-CARE.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are
utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle
time on the order of -seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.
CLE

CE dont-care
CE

WE

ALE

I/Ox 80h Address(5Cycles) Data Input Data Input 10h
tCS tCH tCEA

CE CE
tREA
tWP RE
WE
I/O0~7 out
[Figure 2] Program Operation with CE dont-care.
CLE

CE dont-care
CE

RE
ALE

R/B tR

WE
I/OX 00h Address(5Cycle) 30h Data Output(serial access)
[Figure 3] Read Operation with CE dont-care.
NOTE :
I/O DATA ADDRESS

Device
I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
K9F2G08U0C I/O 0 ~ I/O 7 2,112byte A0~A7 A8~A11 A12~A19 A20~A27 A28
- 18 -
Advance Rev. 0.2

4.1 Command Latch Cycle
CLE
tCLS tCLH
tCS tCH
CE
tWP
WE
tALS tALH
ALE
tDS tDH
I/Ox Command
4.2 Address Latch Cycle

tCLS
CLE
tCS
tWC tWC tWC tWC
CE
tWP tWP tWP tWP

WE
tWH tWH tWH tWH
tALH tALS tALH tALS tALH tALS tALH tALS tALH
tALS
ALE
tDH tDH tDH tDH tDH
tDS tDS tDS tDS tDS
I/Ox Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
- 19 -
Advance Rev. 0.2

4.3 Input Data Latch Cycle
tCLH
CLE

tCH
CE

tWC
ALE

tALS

tWP tWP tWP
WE
tWH
tDH tDH tDH
tDS tDS tDS

I/Ox DIN 0 DIN 1 DIN final
4.4* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
CE tRC

tCHZ
tREH
tREA tREA tREA tCOH

RE
tRHZ tRHZ
tRHOH

I/Ox Dout Dout Dout
tRR

R/B
NOTE :
Transition is measured at 200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
tRHOH starts to be valid when frequency is lower than 33MHz.
- 20 -
Advance Rev. 0.2

4.5 Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCEA tCHZ
tWHR tCOH
RE
tDH tREA tRHZ

tDS tIR
tRHOH
I/Ox 70h/F1h Status Output
4.6 Read Operation

tCLR
CLE
CE
tWC
WE tCSD
tWB
tAR
ALE
tRHZ
tR tRC
RE

tRR

I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h Dout N Dout N+1 Dout M
Column Address Row Address
R/B Busy
- 21 -
Advance Rev. 0.2

4.7 Read Operation(Intercepted by CE)
tCLR
CLE
CE
tCSD
WE tCHZ
tWB tCOH
tAR
ALE
tR tRC
RE
tRR
I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h Dout N Dout N+1 Dout N+2
R/B Busy
- 22 -
K9F2G08U0C
CLE
tCLR
4.8 Random Data Output In a Page
CE
WE
tWB
tAR tRHW tWHR
ALE
- 23 -
tR tRC tREA
RE
datasheet
tRR
I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h Dout N Dout N+1 05h Col Add1 Col Add2 E0h Dout M Dout M+1
Column Address Row Address Column Address
R/B Busy
FLASH MEMORY
Advance Rev. 0.2
Advance Rev. 0.2

4.9 Page Program Operation
CLE
CE
tWC tWC tWC

WE
tAD tWB tPROG
tWHR
ALE
RE

Din Din
I/Ox 80h Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3
N M
10h 70h I/O0
SerialData 1 up to m Byte Program Read Status
Input Command Serial Input Command Command
R/B

I/O0=0 Successful Program
I/O0=1 Error in Program
NOTE :
tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
- 24 -
K9F2G08U0C
CLE
CE
tWC tWC tWC

WE

tADL tADL tWB tPROG
tWHR
ALE
- 25 -
4.10 Page Program Operation with Random Data Input
RE
Din Din Din Din

80h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 85h Col. Add1 Col. Add2 10h 70h I/O0
I/Ox N M J K

datasheet
Serial Data Program Read Status

Column Address Row Address Serial Input Random Data Column Address Serial Input
Input Command Input Command Command Command
R/B

NOTE :
tADL is h time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
FLASH MEMORY
Advance Rev. 0.2
K9F2G08U0C
CLE
CE
tWC
WE tWB
tPROG
tWB tWHR
ALE
tR
RE tADL
- 26 -
I/Ox 00h Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 35h 85h Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Data 1 Data N 10h 70h I/Ox

4.11 Copy-Back Program Operation With Random Data Input
Column Address Row Address Column Address Row Address Read Status Command
datasheet
R/B

Busy Busy
I/O0=0 Successful Program
Copy-Back Data
I/O0=1 Error in Program
Input Command
NOTE :
tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
FLASH MEMORY
Advance Rev. 0.2
K9F2G08U0C
CLE
CE
tWC

WE
tDBSY tWB tPROG
tWB
tWHR
ALE
RE
4.12 Two- Plane Page Program operatoin
Din Din Col Add1 Col Add2 Row Add1 Row Add2 Row Add3
Din Din
80h Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 11h 81h 10h 70h/F1h I/O
I/Ox N M N M

Serial Data Column Address Program Program Confirm Read Status Command
Page Row Address 1 up to 2112 Byte Data Command Command
Input Command Serial Input (Dummy) (True)
R/B

- 27 -
tDBSY : typ. 2.5us
max. 3us
Ex.) Two-Plane Page Program

datasheet
R/B tDBSY tPROG
I/O0~7 80h Address & Data Input 11h 81h Address & Data Input 10h 70h/F1h
Note
Col Add1,2 & Row Add 1,2,3 Col Add1,2 & Row Add 1,2,3
2112 Byte Data 2112 Byte Data
A0 ~ A11 : Valid A0 ~ A11 : Valid
A12 ~ A17 : Fixed Low A12 ~ A17 : Valid
A18 : Fixed Low A18 : Fixed High
A19 ~ A29 : Fixed Low A19 ~ A29 : Valid

NOTE:
Any command between 11h and 81h is prohibited except 70h and FFh.
FLASH MEMORY
Advance Rev. 0.2
Advance Rev. 0.2

4.13 Block Erase Operation
CLE
CE
tWC
WE
tWB tBERS
tWHR
ALE
RE
I/Ox 60h Row Add1 Row Add2 Row Add3 D0h 70h I/O 0
Row Address
R/B Busy

Auto Block Erase Erase Command I/O0=0 Successful Erase
Setup Command Read Status I/O0=1 Error in Erase
Command
4.14 Read ID Operation

CLE
CE
WE
tAR
ALE
RE
tREA
I/Ox 00h ECh
Device 3rd cyc. 4th cyc. 5th cyc.
90h Code
Read ID Command Address 1cycle Maker Code Device Code
Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle
K9F2G08U0C DAh 10h 15h 44h
- 28 -
Advance Rev. 0.2

ID Definition Table
Description
1st Byte Maker Code
2nd Byte Device Code
3rd Byte Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc
4th Byte Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum
5th Byte Plane Number, Plane Size
3rd ID Data
Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1 0 0
2 0 1
Internal Chip Number
4 1 0
8 1 1
2 Level Cell 0 0
4 Level Cell 0 1
Cell Type
8 Level Cell 1 0
16 Level Cell 1 1
1 0 0
Number of
2 0 1
Simultaneously
4 1 0
Programmed Pages
8 1 1
Interleave Program Not Support 0
Between multiple chips Support 1
Not Support 0
Cache Program
Support 1
4th ID Data
1KB 0 0
Page Size 2KB 0 1
(w/o redundant area ) 4KB 1 0
8KB 1 1
64KB 0 0
Block Size 128KB 0 1
(w/o redundant area ) 256KB 1 0
512KB 1 1
Redundant Area Size 8 0
( byte/512byte) 16 1
x8 0
Organization
x16 1
50ns/30ns 0 0
25ns 1 0
Serial Access Minimum
Reserved 0 1
Reserved 1 1
- 29 -
Advance Rev. 0.2

5th ID Data
1 0 0
2 0 1
Plane Number
4 1 0
8 1 1
64Mb 0 0 0
128Mb 0 0 1
256Mb 0 1 0
Plane Size 512Mb 0 1 1
(w/o redundant Area) 1Gb 1 0 0
2Gb 1 0 1
4Gb 1 1 0
8Gb 1 1 1
Reserved 0 0 0
- 30 -
Advance Rev. 0.2

5.0 DEVICE OPERATION
5.1 Page Read
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. There-
fore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are trans-
ferred to the data registers in less than 40s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B
pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially pulsing RE. The repetitive high to
low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address
of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated
multiple times regardless of how many times it is done in a page.
CLE

CE

WE

ALE

R/B t

RE
I/Ox 00h Address(5Cycle) 30h Data Output(Serial Access)
Col. Add.1,2 & Row Add.1,2,3
Data Field Spare Field
[Figure 4] Read Operation
- 31 -
Advance Rev. 0.2
R/B t
RE
Address Address
I/Ox 00h 5Cycles 30h Data Output 05h 2Cycles E0h Data Output
Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2
Data Field Spare Field Data Field Spare Field
[Figure 5] Random Data Output In a Page
- 32 -
Advance Rev. 0.2

5.2 Page Program
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112, in a
single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation
must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data
loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded
data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data
loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address
for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be
operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process.
Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically exe-
cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts,
the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by
monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while program-
ming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 6). The internal write verify detects only
errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command
is written to the command register.
tPROG
R/B
"0"
I/Ox 80h Address & Data Input 10h 70h I/O0 Pass
Col. Add.1,2 & Row Add.1,2,3

"1"
Data
Fail
[Figure 6] Program & Read Status Operation
tPROG
R/B
"0"
I/Ox 80h Address & Data Input 85h Address & Data Input 10h 70h I/O0 Pass
Col. Add.1,2 & Row Add1,2,3 Col. Add.1,2 "1"

Data Data
Fail
[Figure 7] Random Data Input In a Page
- 33 -
Advance Rev. 0.2

5.3 Copy-back Program
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-loading when the bit
error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvi-
ous when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a
sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the
address of the source page moves the whole 2,112-byte data into the internal data buffer. A bit error is checked by sequential reading the data output. In
the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-
Input command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the
program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the com-
pletion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the
Write Status Bit(I/O 0) may be checked(Figure 8 & Figure 9). The command register remains in Read Status command mode until another valid com-
mand is written to the command register.
During copy-back program, data modification is possible using random data input command (85h) as shown in Figure 9.
tR tPROG
R/B
"0"
I/Ox 00h Add.(5Cycles) 35h 85h Add.(5Cycles) 10h 70h I/O0 Pass
Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 & Row Add.1,2,3
"1"
Source Address Destination Address
Fail
NOTE :
Copy-Back Program operation is allowed only within the same memory plane.
[Figure 8] Page Copy-Back Program Operation
tPROG
tR
R/B
I/Ox 00h Add.(5Cycles) 35h 85h Add.(5Cycles) Data 85h Add.(2Cycles) Data 10h 70h
Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2
Source Address Destination Address
There is no limitation for the number of repetition.
[Figure 9] Page Copy-Back Program Operation with Random Data Input
- 34 -
Advance Rev. 0.2

5.4 Read Status
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase
operation is completed successfully. After writing 70h/F1h command to the command register, a read cycle outputs the content of the Status Register to
the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple
memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 2 for specific Sta-
tus Register definitions and Table 3 for specific F1h Status Register definitions. The command register remains in Status Read mode until further com-
mands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read
cycles.
[Table 2] Read Status Register Definition for 70h Command

I/O Page Program Block Erase Read Definition
I/O 0 Pass/Fail Pass/Fail Not use Pass : "0" Fail : "1"
I/O 1 Not use Not use Not use Dont -cared
I/O 2 Not use Not use Not use Dont -cared
I/O 3 Not Use Not Use Not Use Dont -cared
I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1"
I/O 7 Write Protect Write Protect Write Protect Protected : "0" Not Protected : "1" "1"otected
NOTE :
I/Os defined Not use are recommended to be masked out when Read Status is being executed.
[Table 3] Read Status 2 Register Definition for F1h Command

I/O No. Page Program Block Erase Read Definition
I/O 0 Chip Pass/Fail Chip Pass/Fail Not use Pass : "0" Fail : "1"
I/O 1 Plane0 Pass/Fail Plane0 Pass/Fail Not use Pass : "0" Fail : "1"
I/O 2 Plane1 Pass/Fail Plane1 Pass/Fail Not use Pass : "0" Fail : "1"
I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1"
I/O 7 Write Protect Write Protect Write Protect Protected : "0" Not Protected : "1" "1"otected
NOTE :
I/Os defined Not use are recommended to be masked out when Read Status is being executed.
- 35 -
Advance Rev. 0.2

5.5 Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles
sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID
mode until further commands are issued to it. Figure 10 shows the operation sequence.
CLE tCLR
tCEA
CE
WE
tAR
ALE
tWHR
RE
tREA Device
I/OX 90h 00h ECh Code 3rd Cyc. 4th Cyc. 5th Cyc.
Address. 1cycle Maker code Device code
[Figure 10] Read ID Operation
Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle
K9F2G08U0C DAh 10h 15h 44h
5.6 Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or
erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially
programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high.
If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the
Reset command is written. Refer to Figure 11 below.
tRS
R/B
I/OX FFh
[Figure 11] RESET Operation
After Power-up After Reset

Operation mode Mode 00h Command is latched Waiting for next command
- 36 -
Advance Rev. 0.2

5.7 READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/
B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address
loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs
to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the fol-
lowing reference chart(Figure 12). Its value can be determined by the following guidance.
Rp
ibusy
VCC
3.3V device - VOL : 0.4V, VOH : 2.4V

Ready Vcc
R/B
open drain output VOH
CL
VOL
Busy
tf tr
GND
Device
[Figure 12] Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25C , CL = 50pF

2.4
Ibusy 200
200n 2m
tr,tf [s]
Ibusy [A]
150
1.2
100n 100 1m
0.8
tr
50 0.6
3.6 tf 3.6 3.6 3.6
1K 2K 3K 4K
Rp(ohm)
Rp value guidance
VCC(Max.) - VOL(Max.) 3.2V

Rp(min, 3.3V part) = =
IOL + IL 8mA + IL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
- 37 -
Advance Rev. 0.2

6.0 DATA PROTECTION & POWER UP SEQUENCE
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions
whenever Vcc is below about 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-
down. A recovery time of minimum 1ms is required before internal circuit gets ready for any command sequences as shown in Figure 13. The two step
command sequence for program/erase provides additional software protection.

~ 2.3V ~ 2.3V
VCC
High

WP

WE
Dont care
5 ms max
Operation
1ms

Ready/Busy
Invalid Dont care
[Figure 13] AC Waveforms for Power Transition
- 38 -
Advance Rev. 0.2

7.0 BACKWARD COMPATIBILITY INFORMATION
The below table shows key parameters which are different with previous product, so that the host could use make or modify its firmware without misun-
derstanding of compatibility. But the below table dont have all the difference with previous product, but only key parameters changing which can be
defined to have an effect on developing NAND firmware or hardware.
Previous Generation Product Current Generation Device
Part ID K9F2G08U0B K9F2G08U0C
1. tR: 25us / tPROG(200us typ, 700us Max) 1. tR: 40us / tPROG(250us typ, 750us Max)
tERS(1.5ms Typ, 10ms Max) tERS(2ms Typ, 10ms Max)
2. tRC/tWC: 25ns 2. tRC/tWC: 25ns
Features & Operations 3. 2 Plane Program: support 3. 2 Plane Program: support
4. 2Plane Copy-back Program: Support 4. 2Plane Copy-back Program: N/A
5. 2Plane Erase: Support 5. 2Plane Erase: N/A
6. EDO: Support 6. EDO: N/A
1. ICC1 : 15mA(typ)/ 30mA(max) 1. ICC1 : 20mA(typ)/ 35mA(max)
AC & DC Parameters 2. ICC2 : 15mA(typ)/ 30mA(max) 2. ICC2 : 20mA(typ)/ 35mA(max)
3. ICC3 : 15mA(typ)/ 30mA(max) 3. ICC3 : 20mA(typ)/ 35mA(max)
Technical Notes
- 39 -
12V PANEL
12V U2:MP1494 2A
VCC_Pannel /1A
MP1495 3A 5V PANEL U20:MOS
U11
U2_EN U2:MP1494/1495 +5V_NORMAL_1 5V_USB1/500mA
12V U13:USB HUB
120mA 5V_USB2/500mA
U12
MHL 5V_MHL/1A
U4_EN
12V U4:MP1495 1.15V/3A
+5V STB 3.3V_STBY/320MA
U7:AMS1117-3.3V
+5V STB_2
+5V STB_2 MSDXXX
1.5V_DDR/220MA
U3:1117ADJ
+5V STB_1 U8 5V_Normal

12V U5:MP1494/1495 U1:1117ADJ
1.2V_DEMO/282MA
1442+900MA 3.3V_Normal/150MA
U6:AMS1117-3.3V
3.3V_TUNER/110MA
U17:SI2157
POWER IN
DTMB
12V
12V AMP
EARPHONE
U14:3544
5V_WIFI/340MA
WIFI
HDMI1
HDMI INx3
MHL HDMI2 NAND_FLASH
2GBITS
HDMI3
SPI
VGA INx1 VGA I2C EEPROM
MSD6308
YUV
YUV INx1 LVDS PANLE
VIDEO INx1 AV1
L L_OUT
USB1 TPA3110
USB INx2 R R_OUT
USB2
L
EARPHONE
NET INPUT RJ45 R
AV_L/R
YUV_L/R
VGA_L/R
L/R_OUT
IF1
IF2
TUNE INPUT AUDIO INPUTX2 AUDIO AND REMOTE CONTROL
EARPHONE AND LED
OUTPUT
Power system and Block diagram of 6M82B

5 4 3 2 1
12V PANEL
12V U2:MP1494 2A
VCC_Pannel /1A
MP1495 3A 5V PANEL U20:MOS
U11
U2_EN U2:MP1494/1495 +5V_NORMAL_1 5V_USB1/500mA
12V U13:USB HUB
120mA 5V_USB2/500mA
D D
U12
MHL 5V_MHL/1A
U4_EN 1.15V/3A
12V U4:MP1495
+5V STB 3.3V_STBY/320MA
U7:AMS1117-3.3V
+5V STB_2
+5V STB_2
1.5V_DDR/220MA
MSDXXX
U3:1117ADJ
+5V STB_1 U8 5V_Normal

12V U5:MP1494/1495 U1:1117ADJ
1.2V_DEMO/282MA
1442+900MA 3.3V_Normal/150MA
U6:AMS1117-3.3V
3.3V_TUNER/110MA
U17:SI2157
POWER IN
DTMB
C C
12V
12V AMP
EARPHONE
U14:3544
5V_WIFI/340MA
WIFI
HDMI1
HDMI INX3
MHL HDMI2 NAND_FLASH
2GBITS
Note: The marks before values
HDMI3
b:for panel.
SPI FLASH
b0:for panel0,backlight adjust connect to power poard.
B 16MBITS b1:for panel1,120Hz or other panels. B
b2:for panel 3D.
VGA INX1 VGA I2C EEPROM d:for DTMB.
32KBITS dd:for No_DTMB.
YUV
MSDXXX j:for others
YUVI INX1 LVDS PANLE k:for two tuner.
VIDEO INX1 AV1 kkfor single tuner.
m:for 6M30_120Hz panel.
USB1
L
MSD9010
L_OUT t:for DVB-T2
USB INX2 R R_OUT w:for wifi
USB2
ww:for No_Wifi.
L y:for power board
EARPHONE
NET INPUT RJ45 R y1:for power board1 without 5V standby.
y2:for power board2 with 5V standby.
AV_L/R
YUV_L/R
VGA_L/R
L/R_OUT
A A
IF1
IF2
TUNE INPUT AUDIO INPUTX2 AUDIO AND REMOTE CONTROL
SCHEMATIC DIAGRAM FOR 6M82 MAIN BOARD
EARPHONE AND LED Title
OUTPUT SYSTEM
Size Document Number Rev

B 1.0
Date: Friday, February 21, 2014 Sheet 0 of 13

5 4 3 2 1
5 4 3 2 1
+3.3V_Standby
+5V_Standby +5V_Standby
Inverter controler H :Power on +12V_NOR TO +5V_NOR3A
R4 R1
R2
4.7K
L :Power off T2 demod power 1.2V
1K 10K
STANDBY R5
PWR_ON/OFF +12V_PWR FB1
4
PWR_ON/OFF
100
3
+5V_Normal_1
1 R6
OUT
Q1 60/100MHz U1
+5V_Standby_1 U2 j MP1495DJ-LF-Z
KMBT3904
3
10K R8 C1 L1 t AS1117L-1.2/TR-HF
R3 4 5
1 +5V_Normal GND BST
2
3 6 100nF 10uH
22
OUT
ADJ
Q2 3 2 SW EN/SYNC
10K 2 7
IN
KMBT3904 1 IN VCC 8 R9
C36
2
D U8 R17 AAM FB 20K D
y1 220nF/?? y1 AO3401A 100K
3
R30 R10 33K C113
R122
1
y1 10K EN2 100uF +1.2V_DEMOD
R31 C6 C7
1K/?? C210
+
3
y1 100K/?? NC/220nF/?? R12 10uF 100nF
R32 1 Q5 R11 3.65K
y1 KMBT3904 82K +5V_Normal
y1 10K
C3 C5 C8 C9 C10 C11 C12
2
10uF 100nF 100nF
C4
10uF R13 t 2.2uF t 100nF t 2.2uF t 100nF
10K
+3.3V_Standby
R7
j NC/4.7K
U2_EN
U2_EN 1.5V Power for DDR3
EN2
1.15V 2A for VDDC
3
1 BL-ON/OFF R112 1 Q20
2 BL/ADJUST spi_sck j NC/KMBT3904
j NC/10K
3 spi_mosi
1.15V MAX 3A
2
4 STANDBY R295
4
+12V_PWR U3
5 spi_miso j 0/NC
AS1117L/TR-HF
OUT
6 spi_csb EN1 +1.15V_VDDC
7 FB2 U4 MP1495DJ-LF-Z
60/100MHz
3
8 4 5 R16 L2 10uH R14
R128 C17
9 1 GND BST 100
OUT
Q19
ADJ
3 6 100nF
10 SW EN/SYNC 22
IN
+12V_PWR 10K KMBT3904 2 7 R18
11 IN VCC
R110 1 8 1.05K
2
12 AAM FB
3
100K +1.5V_DDR
EN1 R104
CN5 C211
1K/??
BL-ON/OFF
R103 C21 C22 C23 VCC_DDR D1

y1 NC/CN-M 604 D17
STANDBY
5400-92112S-1000 NC/220nF/?? R20 10uF 10uF NC/100nF

BL-ADJ
+5V_Normal SS14 SS14

82K R19
MOSI
MISO
+12V
C14 C16
CSB
C18 C20 100K R15 C13

+5V_Normal VCC_DDR 22 10uF
10uF 100nF C24
C19 100nF 100nF
100nF R21
10uF
1
1
1
1
1
1
R24 3.65K
C15
R126 R125 NC/10K
y1 1K +3.3V_Standby NC/2.2uF
y1 1K
1 BL-ON/OFF 1 BL-ON/OFF +5V_Normal
C BL-ON/OFF C
2 spi_sck 2 BL/ADJUST spi_sck R265
3 3 spi_sck
spi_mosi spi_mosi y1 4.7K
3
4 STANDBY 4 STANDBY spi_mosi R123 R130
5 spi_miso 5 spi_miso BL/ADJUST y1 12K 1 VBL_CTRL
VBL_CTRL
6 spi_csb 6 +5V_Standby_2 spi_csb spi_miso Q28 y1 10K
spi_csb BL/ADJUST y1 KMBT3904 +3.3V_Normal
7 7 R127
2
3
b0 NC/1K
8
9
10
+12V_PWR
8
9
10
+12V_PWR
R169 Q9
1 R262
b0 NC/4.7K
3.3V_Normal
3
C117
11 11 bb NC/2.2uF y1 12K b0 NC/KMBT3904 R129
1 BL_ADJUST
2
12 12 Vsync BL_ADJUST
13 13 FB26 Q17 b0 NC/10K
12V1 12V1
4
b0 NC/KMBT3904
14 14
2
b NC/100/100MHz U6
15 15
OUT
Vsync LD1117-3.3
16 16 Vsync
17
OUT
ADJ
+5V_Standby
IN
CN23 CN2
y1 CN_M y2 CN_M +5V_Standby_1 +5V_Standby_2 +3.3V_Normal
3
5400-92112S-1400
FB9
y2 NC/100/100MHz
FB10
+5V_Normal
y1 100/100MHz
C32 C33 C34 C35
2.2uF 100nF 2.2uF 100nF
y2 NC/60/100MHz
Test Point & MARK VCC_PANEL
C220
FB18
U20
+12V_Panel
+12V_PWR TO +5V_stb2A 3.3V_STB
b 2.2uF??
1 S1 D4 8
+
H1 H3 2 S2 D3 7 C125
+12V_PWR
b 100/100MHz 100nF
4
R270
1
5 9 5 9 FB19 C131 FB3

+12V_PWR 10K 100uF +5V_Standby_1
H5 H4 3 S3 D2 6
OUT
U5
4 8 4 8 NC NC 100/100MHz j MP1494DJ-LF-Z U7
b 100/100MHz R271
FB22 4 G D1 5 LD1117-3.3
1
R23 L3
1
+5V_Standby_1 4 5
3 7 3 7 3 GND BST 6
b 10K/?? 22 C25 10uH
OUT
ADJ
B R22 2 SW EN/SYNC 7 100nF
B
100K
IN
2 6 2 6 C216 C219 IN VCC R25
H9 H10 y1 STM9435 1 8 20K
100nF 2.2uF AAM FB +3.3V_Standby
NC NC NC NC
3
R26
1
C27 33K
+5V_Standby C26 C28
10uF 10uF 100nF R27 C30
R28 C29 C121
H11 82K 3.65K 10uF 100nF 10uF
+5V_Standby
H2 H0 NC +3.3V_Standby R272 C37 C38 C39 C40
1
C31
y1 33K 100nF
1
5 9 5 9 2.2uF 100nF 2.2uF 100nF

3
R29
4 8 4 8 L :Power off 10K
H :Power on 1 Q23
R274
3
y1 KMBT3904
3 7 3 7 y1 4.7K R273 1
PANEL_ON/OFF
2
Q22
2 6 2 6 y1 1K y1 KMBT3904
2
NC NC
A A

Title
SYSTEM POWER

D 1.0

5 4 3 2 1
5 4 3 2 1
video Close to MST IC

NAND & CI & TS & Front End
RGB Interface with wide trace
AUDIO & VIDEO
VGA
VGA-R
VGA-G
VGA-B
HSYNC0
R33
R34
R35
R36
33
75
33
33
C41
C42
C43
C44
47nF
47nF
47nF
47nF
RIN0
GIN0N
GIN0
BIN0
MSD MIU AVDD_DRAM
T19
T21
T20
U9B
PCM_D0
PCM_D1
TS0_D0
TS0_D1
W14
U16
T16
TS1_D0
TS1_D1
TS1_D2
TS1_D0
TS1_D1
POWER&GND U9F +1.5V_DDR
U9A TS1_D2
VGA-HSYNC PCM_D2 TS0_D2
VSYNC0 R118 Y18 Y13 TS1_D3 A14 B16
VGA-VSYNC TS1_D3
TS IN
AA18 PCM_D3 TS0_D3 AA15 TS1_D4 B14 VDDC AVDD_DDR_CMD0 J10
1K +1.15V_VDDC
W19 PCM_D4 TS0_D4 Y15 TS1_D5 TS1_D4 C13 VDDC AVDD_DDR_CMD0
Y17 PCM_D5 TS0_D5 Y14 TS1_D6 TS1_D5 C14 VDDC A16
PCM_D6 TS0_D6 TS1_D6 VDDC AVDD_DDR_DATA0
MIU0
A19 DDR3_RESETB AA19 V15 TS1_D7 E14 J11
DDR3_RESETB A20 PCM_D7 TS0_D7 W15 D_TSCLK TS1_D7 F13 VDDC AVDD_DDR_DATA0 J12
DDR3_CKE
U9E DDR3_CKE TS0_CLK D_TSCLK VDDC AVDD_DDR_DATA0
B19 V19 W16 TS1_VLD G9 K12
ZQ PCM_A0 TS0_VLD TS1_VLD VDDC AVDD_DDR_DATA0
U20 V16 TS1_SYNC G10
PCM_A1 TS0_SYNC TS1_SYNC VDDC
RIN0 H3 B9 MDI_RN W20 G11 A17
GIN0N G2 RIN0P RN C9 MDI_RP MDI_RN Y16 PCM_A2 AA13 G12 VDDC AVDD_DRAM B17
PHY
GIN0M RP MDI_RP PCM_A3 TS1_D0 VDDC AVDD_DRAM
VGA
R37 33 C47 47nF RIN1 GIN0 G1 B8 MDI_TN R114 R120 P19 W13 H9
YPBPR-R BIN0 G3 GIN0P TN C8 MDI_TP MDI_TN 240 1K R20 PCM_A4 TS1_D1 U13 J9 VDDC
HSYNC0 G4 BIN0P TP MDI_TP T18 PCM_A5 TS1_D2 V13 VDDC M8
R40 75 C45 47nF GIN1N HSYNC0 PCM_A6 TS1_D3 VDDP VDDP
TS OUT
VSYNC0 G5 MSD6308RT U19 T12 B13 N8
YPBPR-G R41 33 C48 47nF GIN1 VSYNC0 Y19 PCM_A7 TS1_D4 T15 H10 DVDD_DDR VDDP
YPBPR-G PCM_A8 TS1_D5 DVDD_DDR
PCM
W21 U15 N9
R38 33 C46 47nF BIN1 PCM_A9 TS1_D6 AVDD_PLL AVDD_PLL
YPBPR
YPBPR-B RIN1 K3 W17 U14
YPBPR GIN1N J1 RIN1P Y20 PCM_A10 TS1_D7 T13 A13 M10
R39 0 C49 47nF SOG1 GIN1M PCM_A11 TS1_CLK DVDD_RX_0 AVDD_MOD AVDD_MOD
GIN1 J2 A12 USB0_DM U18 U12 H11 N10
H2 GIN1P DM_P0 B12 USB0_DM V21 PCM_A12 TS1_VLD T14 DVDD_RX_0 AVDD_MOD
BIN1 USB0_DP
USB0_DP
USB
SOG1 J3 BIN1P DP_P0 AA7 USB1_DM U17 PCM_A13 TS1_SYNC
SOGIN1 DM_P1 USB1_DM PCM_A14
Y7 USB1_DP K9 V3
DP_P1 USB1_DP AVDDL_MOD AVDDL_MOD AVDD5V_MHL_C AVDD5V_MHL_C
D T17 D4 D
PCM_CD_N C94 100nF AVDD5V_MHL_D
IF
L2 W18 VIFP
Close to MST IC RIN2P PCM_CE_N VIFM DIFP
SCART
L3 AA20
AV Interface with wide trace K2
K1
GIN2M
GIN2P
Y21
V18
PCM_IORD_N
PCM_IOWR_N VIFP
V1
W1
VIFP C93 100nF
DIFM
DVDD_NODIE
H7
DVDD_NODIE VSENSE_VDD
R15
VIFM 10K
H5 BIN2P M1 AA16 PCM_IRQA_N VIFM R66 J6 R13
+3.3V_TU AVDD_NODIE
HSYNC2 CVBS1P PCM_OE_N AVDD_NODIE GND_EFUSE
VIF
CVBS
H4 N1 CVBS0 V20
VIDEO_IN R42 33 C50 47nF CVBS0 VSYNC2 CVBS0P N2 VCOM0 R21 PCM_REG_N Y1 IFAGC IFAGC K5
VIDEO_IN IF-AGC-T AVDD_AU
VCOM M2 P20 PCM_RESET IFAGC R69 0 AVDD_AU33 R6
CVBS_OUT1 CVBS_OUT PCM_WAIT_N C95 MCP_VDDC +1.2V_DEMOD
R44 75 C51 47nF VCOM0 R19 10nF
L5 R7
R43 0 PCM_WE_N AVDD_DMPLL AVDD3P3_DMPLL MCP_VDDC
AA3 R45
TGPIO0 V2 Dem od-RST 100 P9
TGPIO1 Dem od-RST MCP_VDD33 +3.3V_DEMOD
T10 Y3 K4
MCP
MSD6308RT NAND_ALE T_SCL
NAND_ALE NAND_ALE TUNER_I2C_SCL T_SCL AVDD_DVI AVDD_DVI_USB_MPLL
NAND_CEZ V8 W2 T_SDA L4 R8
NAND_CEZ
NAND_CEZ1
NAND_CEZ1
NAND_CLE
U8
U9
NAND_CEZ
NAND_CEZ1
TUNER_I2C_SDA
R46
100
T_SDA
TO TUNER AVDD_DVI_USB_MPLL MCP_AVDD
R12
NAND_CLE NAND_CLE +3.3V_Norm al MCP_TESTPIN
NAND_DQS U11 for T2 demod
NAND_DQS NAND_RBZ U7 NAND_DQS Power,chip T2
NAND_RBZ V7 NAND_RBZ demodpin NC
NAND_REZ C52 C53
NAND_REZ NAND_REZ
NAND
NAND_WEZ T11
NAND_WEZ T7 NAND_WEZ 22pF A15
NAND_WPZ 22pF
NAND_WPZ NAND_WPZ R47 R48 A18 GND M4
NAND_D[7:0] Y8 4.7K B15 GND GND M6
NAND_D0 4.7K
NAND_D1 W9 NAND_AD0 B18 GND GND M9
NAND_D2 AA9 NAND_AD1 T_SDA T_SCL C15 GND GND M11
NAND_D3 W10 NAND_AD2 C18 GND GND M12
NAND_D4 Y10 NAND_AD3 D15 GND GND M13
NAND_D5 W11 NAND_AD4 D18 GND GND M14
NAND_D6 W12 NAND_AD5 E15 GND GND M15
NAND_D7 Y12 NAND_AD6 E18 GND GND N4
NAND_AD7 F15 GND GND N6
F18 GND GND N11
Audio Line IN G7
G8
GND
GND
GND
GND
N12
N13
G15 GND GND N14
MSD6308RT GND GND
G18 N15
C54 2.2uF VGA-AUR_IN H6 GND GND P5
VGA_AUR_IN
H8 GND GND P10
C55 2.2uF VGA-AUL_IN H18 GND GND P11
GPIO & LVDS

VGA_AUL_IN J4 GND GND P12
J8 GND GND P13
J16 GND GND P14
J17 GND GND P15
HD-LIN C56 2.2uF LINE_IN_1L K8 GND GND R5
HD-LIN
K15 GND GND R9
HD-RIN C57 2.2uF LINE_IN_1R K16 GND GND R10
HD-RIN U9D GND GND
R49 b2 NC/100
L6 R11
3D_EN PCM_PWR_EN K17 K21 LVA0N L7 GND GND T6
3D_EN 3D_EN/PCM_PWR_EN LVA0N LVA0N GND GND
PWM
AMP_MUTE K18 J19 LVA0P L8 T8
AMP_MUTE BL_ADJUST J18 AMP_MUTE LVA0P K19 LVA1N LVA0P L9 GND GND T9
BL_ADJUST D9 BRI_ADJ LVA1N K20 LVA1N L10 GND GND U6
R50 100 PWM_PM LVA1P
PWM_PM LVA1P L19 LVA2N LVA1P L11 GND GND U10
R51
b NC/1K LVA2N L20 LVA2P LVA2N L12 GND GND V6
SYNC_TO_6M30
U9C
SYNC 6M303D GLASSES
SYNC_TO_6M30 LVA2P
LVACKN
M21 LVACLKN LVA2P
LVACLKN
L13 GND
GND
GND
GND
V10
KEY0_IN E4 M20 LVACLKP L14 V12
KEY0_IN LVACKP LVACLKP GND GND
SAR
LED_R R52 100 E5 N21 LVA3N L15 W8
P3 C2 HDMI0_RX0N ARC_DET F7 LED_R LVA3N M19 LVA3P LVA3N L16 GND GND Y9
LINE_IN_0L A_RX0N HDMI0_RX0N ARC_DET ARC_DET LVA3P LVA3P GND GND
R2 C1 HDMI0_RX0P KEY1_IN F6 N19 LVA4N Y11
Audio Line Out LINE_IN_1L U2 LINE_IN_0R
LINE_IN_1L
HDMI A A_RX0P
A_RX1N
D3 HDMI0_RX1N
HDMI0_RX0P
HDMI0_RX1N POWER_DET F8 KEY1_IN
POWER_DET
LVA4N
LVA4P
N20 LVA4P
LVA4N
LVA4P
GND
GND
AA10
LVDS
LINE_IN_1R T3 D1 HDMI0_RX1P AA12
LINE_IN_1R A_RX1P HDMI0_RX1P GND
VGA-AUL_IN T2 D2 HDMI0_RX2N E19 LVB0N
LINE_IN_2L A_RX2N HDMI0_RX2N LVB0N LVB0N
VGA-AUR_IN T1 E3 HDMI0_RX2P A10 E20 LVB0P
HDMI0_RX2P
Analog Audio
LINE_IN_2R A_RX2P PM_SPI_CK LVB0P LVB0P
SPI
R1 C3 HDMI0_CLKN SPI_SDI B10 F21 LVB1N
LINE_IN_3L A_RXCN HDMI0_CLKN PM_SPI_DI LVB1N LVB1N
R3 B1 HDMI0_CLKP C11 F20 LVB1P
LINE_IN_3R A_RXCP HDMI0_CLKP PM_SPI_DO LVB1P LVB1P
B2 HDMI0_HPDIN B11 G21 LVB2N
HOTPLUGA HDMI0_HPDIN PM_SPI-CSN LVB2N LVB2N
F1 HDMI0_SCL F19 LVB2P
DDCDA_CK HDMI0_SCL LVB2P LVB2P
F2 HDMI0_SDA G19 LVBCLKN
DDCDA_DA HDMI0_SDA LVBCKN LVBCLKN
EARPHONE_OUTL U5 E2 HDMI_ARC G20 LVBCLKP
EARPHONE_OUTL PAD_ARC HDMI_ARC LVBCKP LVBCLKP
EARPHONE_OUTR V5 F3 HDMI_CEC H19 LVB3N
EARPHONE_OUTR CEC HDMI_CEC LVB3N LVB3N MSD6308RT
AMP-INL R53 150 LINE_OUTL1 R58 b NC/100 H20 LVB3P
AMP-INL AMP-INR LINE_OUTR1 T4 LOCAL_DIMMING_EN C21 LVB3P J21 LVB4N LVB3P
AMP-INR LINE_OUT_0L LOCAL_DIMMING_EN UART_RX2 LVB4N LVB4N
T5 W5 HDMI2_RX0N MODE R60 C20 J20 LVB4P
R54 150 LINE_OUT_0R C_RX0N Y5
HDMI2_RX0N MODE UART_TX2 LVB4P LVB4P
HDMI2_RX0P
HDMI2_RX0P 100
C59 LINE_OUTL1 U3 C_RX0P W6 HDMI2_RX1N D20
C60 LINE_OUT_2L C_RX1N HDMI2_RX1N LDE
HDMI C
LINE_OUTR1 U4 Y6 HDMI2_RX1P UART_RX E7 D19 TCON_WP

LINE_OUT_2R C_RX1P HDMI2_RX1P M_UART0_RX LCK LCK
2.2nF 2.2nF AA6 HDMI2_RX2N UART_TX D7 D21
C_RX2N HDMI2_RX2N M_UART0_TX LVSYNC
W7 HDMI2_RX2P M_I2C_SCL B21 C19
C_RX2P HDMI2_RX2P M_I2C_SCL LHSYNC
AA4 HDMI2_CLKN M_I2C_SDA B20
C_RXCN HDMI2_CLKN M_I2C_SDA
AUVAG N3 Y4 HDMI2_CLKP
VAG C_RXCP HDMI2_CLKP
GPIO
AUVRM P2 V4 HDMI2_HPDIN R18 IF-AGC-SEL
VRM HOTPLUGC HDMI2_HPDIN TCON0 IF-AGC-SEL
C W4 HDMI2_SCL P17 WIFI_CTL C
DDCDC_CK W3 HDMI2_SDA
HDMI2_SCL
HDMI2_SDA
TO POWER BACKLIGHT CONTROL TCON1 N18
WIFI_CTL 3 CORE POWER +1.15V_VDDC
DDCDC_DA TCON2
LOCAL DIMMING
F12 L17
TCON
R57 150 EARPHONE_OUTL s pi_s ck N17 AVDDL_MOD
EARPHONE-OUTL I2S_IN_BCK s pi_s ck 8 7 SPI1_CK TCON3 C63 C64 C66 C68
E12 C6 HDMI3_RX0N s pi_m os i L18 P16 NC/100nF
I2S_IN_WS D_RX0N HDMI3_RX0N s pi_m os i 6 5 SPI1_DI TCON4 NC/100nF NC/100nF 100nF
R59 150 EARPHONE_OUTR D12 B5 HDMI3_RX0P s pi_m is o M18 N16
EARPHONE-OUTR I2S_IN_SD D_RX0P HDMI3_RX0P s pi_m is o 4 3 SPI2_CK TCON5
C5 HDMI3_RX1N s pi_cs b M16 R17 R61 HP_DET
D_RX1N HDMI3_RX1N s pi_cs b
RM1 2 1 SPI2_DI TCON6 HP_DET
HDMI D
B4 HDMI3_RX1P M17 R16 100 5V_DETE C67

HDMI3_RX1P
I2S
F10 D_RX1P A4 VSYNC_LIKE TCON7 5V_DETE 10uF

HDMI3_RX2N y 22 X 4 C69 C70
I2S_OUT_BCK D_RX2N HDMI3_RX2N C62
E11 C4 HDMI3_RX2P Vs ync NC/100nF
I2S_OUT_MCK D_RX2P HDMI3_RX2P NC/2.2uF 100nF
F11 A6 HDMI3_CLKN R111 100 E9
I2S_OUT_WS D_RXCN HDMI3_CLKN LAN_LED0
C72 D11 B6 HDMI3_CLKP F9
C71 I2S_OUT_SD D_RXCP HDMI3_CLKP LAN_LED1
2.2nF 2.2nF A2 HDMI3_HPDIN C65
HOTPLUGD HDMI3_HPDIN
A3 HDMI3_SCL D6 PM_TX NC/100nF
DDCDD_CK HDMI3_SCL R113 PM_TX/PANEL_ON/OFF PANEL_ON/OFF
B3 HDMI3_SDA 4.7K
E6 PM_RX
DDCDD_DA HDMI3_SDA +3.3V_Norm al PM_RX/VBL_CTRL VBL_CTRL
GPIO_PM
A7 U2_EN
FLASH_WP U2_EN
SPDIF MHL
E10 C10
IRIN B7 SPDIF_IN/3D_FLAG D10
3D_FLAG
SPDIF_OUT
3D_FLAG E2PROM_WP C7 b2 NC/100
EEPROM_WP
3D_LR_IN
DDR3 POWER
IRIN SPDIF_OUT SPDIF_OUT 3D_LR_IN 3D_LR_IN
Sys tem _RST E8 C83 Close to MSTAR IC C58 PWR_ON/OFF
C12 R62
A9 R63
PWR_ON/OFF
100
PWR_ON/OFF nodie DVDD_NODIE
+1.5V_DDR
C79
AVDD_DRAM
RESET 33pF 22pF PM_CONFIG0

AUVRM PM_CONFIG0 NC/100nF
AUVAG R14 R55 G6 PM_CONFIG1
FB4 TESTPIN F4 MHL_CABLE-DET M-SCL 100 M_I2C_SCL PM_CONFIG1
C73 MHL_CABLE_DET MHL_CABLE-DET M-SCL C77 C80
1K/100MHz C74 XTALI AA2 F5 MHL_VBUS-EN C75 C76 2.2uF 100nF C82
4.7uF XTALIN MHL_VBUS_EN MHL_VBUS-EN
100nF XTALO Y2
M-SDA R56 100
1uF
XTALOUT M_I2C_SDA 100nF
M-SDA 10uF
Close to MSTAR IC C61
22pF MSD6308RT
with width trace Close to MST IC C78 C81
MSD6308RT NC/100nF 100nF
+3.3V_Norm al
R86
4.7K
R87
4.7K Standby Power 3.3V
M-SDA M-SCL
AVDD_DMPLL +3.3V_Standby AVDD_AU
+3.3V_Standby AVDD_DVI AVDD_NODIE
FB5
600/100MHz FB6
// CHIP Config {PM_CONFIG0, SPI_DI, PM_CONFIG1, PWM_PM} 600/100MHz

C84 C87 C88
Mode Selection //SB51_EXT spi 4'b1000 Boot from 51 EXT SPI flash// 10uF
C85 C86
NC/100nF NC/100nF 100nF
C89 C90
100nF
C91
100nF
C92
NC/100nF
NC/100nF 100nF
+3.3V_Standby
HEMCU_EXT spi 4'b1001 Boot from MIPS EXT SPI flash
4'b1011 Boot from ROM
IR&Key_CONNECT +5V_Standby
+5V_Standby
PM_CONFIG0
+3.3V_Standby
R65
R67 4.7K HP_MUTE j 560??
HP_MUTE R68
j 560?? R115 LED/R
Normal Power 3.3V Demod 1.2V
4.7K SPI_SDI
GND_CN1
R71 R70
3
j 560??
4.7K
LED_G
LED_R
KEY1
USB_SW
KEY0
R73 1 Q6
USB_SW +1.2V_DEMOD
+5V
3
4.7K
IR
R74 +5V_Standby j KMBT3904 +3.3V_Norm al AVDD_MOD VDDP AVDD_PLL +3.3V_DEMOD

j 4.7K
PM_CONFIG1 LED_R 1 Q7 R76
2
1
1
1
1
1
1
FB7
1
KMBT3904 j 560??
R77 NC/4.7K 600/100MHz
4.7K
2
R78 PWM_PM R80
CN4 LED_G C96 C97
33K
11 +3.3V_Standby C101 t 100nF t 100nF
C103
10 R79 C98 C99 C100 1uF C102
9 10K 10uF 100nF 100nF t 100nF
KEY0/IN t 100nF
8 KEY1/IN
7 LED/R
6 R82 R83
5 +5V_Standby R81 j 10K/NC j 10K/NC
IR IRIN
4 IR R84 100
3 LED/R +5V_Standby 100 KEY0/IN KEY0_IN
2 KEY1/IN KEY1_IN
1 +5V_Standby KEY1/IN R85 KEY0/IN
RESET Crystal KEY0/IN D2
ESD C105
100 KEY0/IN 0 3.3K 6.2K 18K
3.3K
LED_G
10K
33pF D3 D4
27K
CN-M C104 C107
ESD ESD V- V+ CH- CH+
0
100nF 100nF
5400-99112S-0900 C106
100nF
V- V+ CH- CH+
KEY1/IN 0 9.1K 18K
B B
STB SOURCE MENU

KEY1/IN
+5V_Standby
10K
27K
0
3
STB SOURCE MENU

C108
1M
R88 D5
BAV99
XTALO
27pF
Detect NAND Flash Power DEBUG heat sink
+5V_Standby
2
FORU9
C109 R89
1
2.2uF 1M 24MHz MUST pull high to 5VSTB

+5V_Standby
ISP AND VGA EDID
X1 C110 1
2
FOR_U9
1
27pF R92 R93

R90 Q8 XTALI 1
1 4.7K 4.7K
MMBT3906
100K HS GND 2
R91 1K R64 GND 2
3
Sys tem _RST 220K??

C111 R95 100 UART_TX
1uF R94 C112 UART-TX UART_RX
1nF R72 UART-RX R96
100K POWER_DET 1505-M0300300-23
j Heat Sink
100
1K PART NO:1505-M0420400-2302
R75
100K
ON RESET Time=140mS
when detect source is from 5V,

EEPROM change resistance ,make sure
SDA_E2P
SCL_E2P
+3.3V_Norm al
detect power 1VPP.
WP
GND_E2P
R97
3V3
4.7K E2P_CONNECT
1
1
1
U10
1
1 8
2 A0 VCC 7 EEPROM_WP EEP-SCL1
3 A1 WP 6 100 M-SCL
R98
4 A2 SCL 5 R99 100 M-SDA
GND SDA SDA2
EEP-SDA1 EEP-WP EEP-GND
FM24C04A
C114 C115 C116 SCL2 GND2 Debug Port
TX2 7 1 M-SDA
100nF 22pF 22pF
RX2 2 M-SCL
6
WP: M-SDA 5 3
M-SCL 4 4
0:READ AND WRITE 3 5 EEPROM_WP
+3.3V_Norm al
1::WRITE PROTECT UART-TX 2 6

UART-RX 1 7
CN3
NC/CN-M NC/CN-M
CN31
A A

Title
CONTROLER
Size Docum ent Num ber Rev

E 1.0

5 4 3 2 1
5 4 3 2 1
+3.3V_Normal +3.3V_Normal
R310 R308
4.7K b1 NC/4.7K
LOCAL_DIMMING_EN
M-SCL R306 P_SCL
M-SCL
b1 NC/100 C230
b1 NC/22pF
R311
MODE
M-SDA P_SDA
M-SDA
b1 NC/100 C229 FOR FHD
b1 NC/22pF TCON_WP R289 WP_P 53
D LCK D
52
b1 NC/0
R284 51
P_SCL R287 b1 NC/0 50 1
b1 NC/0 2
3D_FLAG
3D_FLAG P_SDA R288 b1 NC/0 49
3
R316 b1 NC/100 SCLP 48
SDAP 47 4
0 X 4 SYNC_TO_6M30
SYNC_TO_6M30 SYNC_TO_6M30_1 R302
5
LVB1N RM16 LVB1N1 R301 b1 NC/0 b1 NC/0 46
2 1 SYNC 45 6
LVA4N LVA4P LVB1P LVB1P1 MODE MODE
LVA4N LVA4P 4 3 44 7
LVA3N LVA3P LVB0N LVB0N1 BL/ADJUST BL_ADJUST_1
LVA3N LVA3P 6 5 BL/ADJUST 8
LVACLKN LVACLKP LVB0P LVB0P1 R300 b1 NC/0 MODE 43
LVACLKN LVACLKP 8 7 42 9
LVA2N LVA2P LOCAL_DIMMING_EN LOCAL_DIMMING_EN_1
LVA2N LVA2P LOCAL_DIMMING_EN 41 10
LVA1N LVA1P R299 b1 NC/100 BKL 11
LVA1N LVA0N LVA0P LVA1P 0 X 4 LVB0P1 40
LVA0N LVA0P B0P1 12
LVBCLKN RM15 LVBCLKN1 LVB0N1 39
LVB4N
LVB4N LVB4P
LVB4P
LVBCLKP 2
4
1
3
LVBCLKP1 B0N1
B1P1
LVB1P1 38
13
14
FOR HD
LVB3N LVB3P LVB2N LVB2N1 LVB1N1 37 32
LVB3N LVB3P 6 5 B1N1 36 15
LVBCLKN LVBCLKP LVB2P LVB2P1 LVB2P1 31 +12V_Panel
LVBCLKN LVBCLKP 8 7 B2P1 35 16
LVB2N LVB2P LVB2N1 30
LVB2N LVB2P B2N1 17
LVB1N LVB1P +3.3V_Normal 34 29
LVB1N LVB1P 0 X 4 +3.3V_Normal
LVBCLKP1 33
18
LVB0N LVB0P 19 28
LVB0N LVB0P LVA1N RM11 LVA1N1 BCP1
2 1 LVBCLKN1 32 27
LVA1P LVA1P1 BCN1 20
4 3 31 26
LVA0N LVA0N1 R305 R307 21
6 5 b2 NC/4.7K LVB3P1 30 25
LVA0P LVA0P1 R292 b1 NC/0 b2 NC/4.7K B3P1 29
22
8 7 LVB3N1 24
3DEN B3N1 23
LVB4P1 28 23
R298 B4P1 24
0 X 4 LVB4N1 27 22 MODE
b2 NC/100 B4N1 25
LVACLKN RM12 LVACLKN1 3D_EN 3D_EN 3D_EN_1 26 26 21
LVACLKP 2 1 LVACLKP1 3D_LR_IN 3D_LR_IN_1 25 20
4 3 3D_LR_IN 27
LVA2N LVA2N1 R297 b2 NC/100 LVA0P1 24 28 19 LVA0P1
6 5 A0P1 LVA0N1 23
LVA2P LVA2P1 18 LVA0N1
8 7 R293 A0N1 22 29
LVA1P1 17
3DLR A1P1 21 30
b1 NC/0 LVA1N1 31 16 LVA1P1
0 X 4 A1N1 20
LVA2P1 15 LVA1N1
RM14 A2P1 32
LVB4N LVB4N1 LVA2N1 19 14
LVB4P 2 1 LVB4P1 A2N1 33
18 13 LVA2P1
4 3 34
LVB3N LVB3N1 LVACLKP1 17 12 LVA2N1
6 5 ACP1 35
LVB3P LVB3P1 LVACLKN1 16 11
8 7 ACN1 36
C 15 10 LVACLKP1 C
37
LVA3P1 14 9 LVACLKN1
0 X 4 A3P1 38
R296 LVA3N1 13 8
LVA4N RM13 LVA4N1 b1 NC/0 A3N1 39
LVA4P1 12 40 7 LVA3P1
LVA4P 2 1 LVA4P1 A4P1
LVA4N1 11 41 6 LVA3N1
LVA3N 4 3 LVA3N1 R304 A4N1
LOCAL_DIMMING_EN LOCAL_DIMMING_EN_1 10 42 5
LVA3P 6 5 LVA3P1 9 4 P_SCL
8 7 b1 NC/100 8 43
R303 3 P_SDA
7 44
b1 NC/100 45 2
6 1
GND_P 46
5
47
4 CN32
48
3 b NC/CN-F
49
2
50
1
+12V_Panel 51
12V_P CN34
b CN-F
+12V_Panel
1 2
3 4
5 6
7 8
LVA4P1 9 10 LVA4N1
LVA3P1 11 12 LVA3N1
LVACLKP1 13 14 LVACLKN1
LVA2P1 15 16 LVA2N1
LVA1P1 17 18 LVA1N1
LVA0P1 19 20 LVA0N1
3D_EN_1 21 22 3D_LR_IN
B LOCAL_DIMMING_EN_1 23 24 MODE B
BL_ADJUST_1 25 26 SYNC_TO_6M30_1
27 28
LVB4P1 29 30 LVB4N1
LVB3P1 31 32 LVB3N1
LVBCLKP1 33 34 LVBCLKN1
LVB2P1 35 36 LVB2N1
LVB1P1 37 38 LVB1N1
LVB0P1 39 40 LVB0N1
41 42
b CN-M
CN17
5400-99121S-4020
LVB4P1
LVB4P1 LVB4N1
LVB4N1 LVB3P1
LVB3P1 LVB3N1
LVB3N1
LVBCLKP1
LVBCLKP1 LVBCLKN1
LVBCLKN1
LVB2P1
LVB2P1 LVB2N1
LVB2N1 LVB1P1
LVB1P1 LVB1N1
LVB1N1 LVB0P1
LVB0P1 LVB0N1
LVB0N1
LVA4P1
LVA4P1
LVA4N1
A LVA4N1 A
LVA3P1
LVA3P1 LVA3N1
LVA3N1
LVACLKP1
LVACLKP1 LVACLKN1
LVACLKN1
LVA2P1
LVA2P1 LVA2N1
LVA2N1 LVA1P1 SCHEMATIC DIAGRAM FOR 6M82 MAIN BOARD
LVA1P1 LVA1N1
LVA1N1 LVA0P1 Title
LVA0P1 LVA0N1 LVDS
LVA0N1
C 1.0
5 4 3 2 1
5 4 3 2 1
HDMI1 10 X 4 HDMI0/5V
ARC DATA2+
DATA2 SHIELD
DATA2-
1
2
3
4
HDMI0-RX2P
HDMI0-RX2N
HDMI0-RX1P
HDMI0-RX2P
HDMI0-RX2N
HDMI0-RX1P
RM2
7
5
3
8
6
4
HDMI0_RX2P
HDMI0_RX2N
HDMI0_RX1P
HDMI0_RX2P
HDMI0_RX2N
HDMI0_RX1P
DATA1+ HDMI0-RX1N HDMI0_RX1N
5 1 2 HDMI0_RX1N
DATA1 SHIELD 6 HDMI0-RX1N R131
DAT1A- HDMI0/5V 1K
7 HDMI0-RX0P R132
DATA0+ 8 10 X 4 10K
DATA0 SHIELD 9 HDMI0-RX0N HDMI0-RX0P RM3 HDMI0_RX0P HDMI0-HPD
DATA0- HDMI0-RX0N 7 8 HDMI0_RX0N HDMI0_RX0P
20 10 HDMI0-CLKP HDMI0_RX0N
GND CLK+ HDMI0-CLKP 5 6 HDMI0_CLKP
11
3
CLK SHIELD 3 4 HDMI0_CLKP R133 R134
21 12 HDMI0-CLKN HDMI0-CLKN HDMI0_CLKN 10K R135
GND CLK- 1 2 HDMI0_CLKN 10K Q10 1 HDMI0_HPDIN
13 CEC KMBT3904 HDMI0_HPDIN
22 CEC 14 HDMI-ARC 4.7K
GND NC HDMI0-SCL R136 22
2
15 HDMI0-SCL HDMI0_SCL
SCL HDMI0-SDA
23 16 HDMI0-SDA HDMI0_SDA
GND SDA R137 22
17
DDC/CEC GND 18
+5V POWER HDMI0/5V
19 HDMI0-HPD
HOT PLUG
D D
CN6
HDMI SOCKET
MHL
HDMI2
CN7
1 HDMI2-RX2P
DATA2+ 2 MHL-CD-SENSE1
DATA2 SHIELD 3 HDMI2-RX2N 10 X 4 +5V_Standby
DATA2- 4 HDMI2-RX1P HDMI2-RX2P RM4 HDMI2_RX2P
DATA1+ 5 7 8 HDMI2_RX2P
HDMI2-RX2N HDMI2_RX2N
DATA1 SHIELD 6 HDMI2-RX1N HDMI2-RX1P 5 6 HDMI2_RX1P HDMI2_RX2N
DAT1A- 7 3 4 HDMI2_RX1P
HDMI2-RX0P HDMI2-RX1N HDMI2_RX1N R138 R139
DATA0+ 8 1 2 HDMI2_RX1N
DATA0 SHIELD 10K 10K
9 HDMI2-RX0N
20 DATA0- 10 HDMI2-CLKP
GND CLK+ HDMI2-SCL R141 22
11 HDMI2-RX0P R140 0 HDMI2_RX0P
HDMI2_RX0P HDMI2_SCL
21 CLK SHIELD 12 HDMI2-SDA
HDMI2-CLKN HDMI2-RX0N R143 0 HDMI2_RX0N HDMI2_SDA
GND CLK- 13 CEC HDMI2_RX0N R142 22
22 CEC 14 HDMI2-CLKP R145 10 HDMI2_CLKP
HDMI2_CLKP
GND NC 15 HDMI2-SCL
SCL
HDMI2-CLKN R146 10 HDMI2_CLKN
HDMI2_CLKN
23 16 HDMI2-SDA
GND SDA 17
DDC/CEC GND 18
+5V POWER 19 HDMI2/5V
HDMI2-HPD
HOT PLUG
HDMI2-HPD R144 33 HDMI2_HPDIN
HDMI SOCKET HDMI2_HPDIN
Hotplug is built in for this HDMI port .
C C
HDMI3 HDMI3/5V
1 HDMI3-RX2P HDMI3/5V
DATA2+ 2
DATA2 SHIELD 3 HDMI3-RX2N 10 X 4
DATA2- R147
4 HDMI3-RX1P HDMI3-RX2P RM5 HDMI3_RX2P
DATA1+ 7 8 HDMI3_RX2P 1K R148
5 HDMI3-RX2N HDMI3_RX2N
DATA1 SHIELD 6 HDMI3-RX1N HDMI3-RX1P 5 6 HDMI3_RX1P
HDMI3_RX2N
R150 10K
HDMI3_RX1P R149
DAT1A- 7 HDMI3-RX0P HDMI3-RX1N 3 4 HDMI3_RX1N 10K 10K HDMI3-HPD
DATA0+ 8 1 2 HDMI3_RX1N
3
DATA0 SHIELD 9 HDMI3-RX0N HDMI3-SCL R151 22
20 DATA0- 10 HDMI3-CLKP HDMI3-SDA HDMI3_SCL Q11 1 R153 HDMI3_HPDIN
GND CLK+ 10 X 4 HDMI3_SDA HDMI3_HPDIN
11 RM6 R152 22 KMBT3904
CLK SHIELD HDMI3-RX0P HDMI3_RX0P 4.7K
21 12 HDMI3-CLKN 7 8 HDMI3_RX0P
HDMI3-RX0N HDMI3_RX0N
2
GND CLK- 13 CEC 5 6 HDMI3_RX0N
CEC HDMI3-CLKP HDMI3_CLKP
22 14 HDMI3-CLKN 3 4 HDMI3_CLKN HDMI3_CLKP
GND NC 15 HDMI3-SCL 1 2 HDMI3_CLKN
23 SCL 16 HDMI3-SDA
GND SDA 17
DDC/CEC GND 18
+5V POWER HDMI3/5V
19 HDMI3-HPD
HOT PLUG
CN8
HDMI SOCKET
B
CEC & ARC MHL SWITCH(OK) ARC DET(OK) B
HDMI-ARC C119 HDMI_ARC HDMI2/5V R154 ARC_DET

HDMI_ARC +5V_MHL +5V_VBUS HDMI0/5V
2.2uF ARC_DET
+5V_Normal_1 4.7K
CEC R157 HDMI_CEC j 60/100MHz U12
HDMI_CEC R159
200 FB11
5 1
HDMI2/5V AVDD5V_MHL_C 10K
IN OUT
+
CE10
R156 +5V_Standby 2 100uF C122 R160
5.1 GND 100nF NC/10K
j 60/100MHz
FB12 4 3
EN FLG
AP2171WG-7
R155 1A active high power switch

MHL-CD-SENSE1 100
MHL_CABLE-DET R161 NC/100
MHL_VBUS-EN
R163
R162 NC/10K
R158 MHL_CABLE-DET
300K C120 1K
47nF C123
100nF
A A

Title
HDMI

D 1.0
5 4 3 2 1
5 4 3 2 1
YPBPR GND_CN19 Y PR PB
2
1
j NC
1
1
1
YPBPR-G
5 YPBPR-R YPBPR-G
2 AV-OUT
D CVBS_OUT D
YPBPR-R 1
3 YPBPR-B
YPBPR-R R164
4 YPBPR-B CN10 NC
YPBPR-B
1 YPBPR-G
CN19
6100-024100-0500
YPBPR-R
YPBPR-G
YPBPR-B
NC/ESD NC/ESD
NC/ESD D7 D8
D6 R165 R166 R167
75 75 75
C C
AV INPUT SPDIF OUT
GND_CN18
SPDIF
VIDEO
GND_VIN
YELLOW 1
1
2 VIDEO_IN R224
1
VIDEO_IN BLACK 1
200
1
3 2 SPDIF_OUT
R168 SPDIF_OUT
3
CN26 D18 75
RCA SOCKET ESD CN18 R283
RCA SOCKET 75
D21
ESD
B B
GND_LIN LIN
1
WHITE 1
2 AV2_AUL R170
HD-LIN
3 10K
CN27 D19
RCA SOCKET ESD R171
12K
GND_RIN RIN
1
RED 1
R172
2 AV2_AUR HD-RIN
3 10K
CN28 D20
RCA SOCKET ESD R173
A 12K A

Title
VIDEO

B 1.0
5 4 3 2 1
5 4 3 2 1
VGA SDA SCL GND_VGA
1
VGA_TX R175 100 VGA_SDA VGA_SDA
17
UART-TX B G R
D VGA_RX R174 100 VGA_SCL VGA_SCL 15 5 D
1
UART-RX
1
10
R179 100 VGA_VS VGA_VS 14 4
VGA-VSYNC
9
VGA-HSYNC R180 100 VGA_HS VGA_HS 13 3 VGA-B
8 VGA-B
VGA-G VGA-B
12 2 VGA-G
1
R182 R181 VGA-G
10K 7 VGA-R
10K HS VS VGA-R
11 1 VGA-R
6 D10
CN12 NC/ESD
VGA SOCKET NC/ESD
LI RI R176
16
75 D11
GND_CN20 D9 R177 R178
1
1
NC/ESD 75 75
1
R183
C
VGA_AUR 10K VGA_AUR_IN
C
VGA_AUR_IN
2 VGA_AUL
VGA_AUL R184 VGA_AUL_IN
5 VGA_AUL_IN
10K
3 VGA_AUR
R185 R186
12K 12K
4
CN20
6100-024100-0500
B B
A SCHEMATIC DIAGRAM FOR 6M82 MAIN BOARD A
Title
VGA

A 1.0

5 4 3 2 1
5 4 3 2 1
USB2.0 INTERFACE USB HUB +3.3V_Normal

M3V3
+5V_USB
FB13
+5V_USB +5V_USB
+5V_USB2
M3V3 w 60/100MHz
GND_U2
C124 C239
+3.3V_Normal
10uF FB14
D2+
100nF
D2-
CN14
w 470/100MHZ
1
1 C126 C128
1
C127
1
1
VBUS 2 5.1 USB1_DM USB1_DM Direct to main IC
D-
R187
USB1_DM R202 & C134 are close to pin 26 (OVCJ). w 56pF w 56pF
D 3 R188 USB1_DP USB1_DP D
D+ 4
5.1
USB1_DP Traces of VccDP1 to VccDP4 are 1.5mm width. R189
w 1K
w 10uF
GND 5 BUSJ
SHELL signal only 8 mil +5V_USB
6
SHELL XRSTJ
NC/ESD NC/ESD R202 signal only 8 mil R192
OVCJ
USB2.0 SOCKET R191
6100-089110-0420 R190 w 10K M3V3 w 10K
C134 C129
w 10nF R193
w 100K w 100nF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R194
NC3
DRV
LED2
LED1
VD33
DPU
VDD5
DMU
BUSJ
OVCJ
PWRJ
TESTJ
VBUSM
XRSTJ
Punch 3 more GND vias w 100K
near by C5 GND side.
USB0_DP USB0_DM
Crystal 12MHZ/16 ~ 20pF USB0_DM
30 ~ 50ppm / (HC-49S) FE1.1s Rev. B USB0_DM USB0_DP
USB0_DP
XOUT
Punch 3 more GND
REXT
To main IC
DM4
DM3
DM2
DM1
NC1
NC2
VSS
DP4
DP3
DP2
DP1
+5V_USB
XIN
vias near by pin 1. UCS (BC1.2) mode
U13
+5V_USB1
PART NO.: 47EQ-FE11S0-0280
1
2
3
4
5
6
7
8
9
10
11
12
13
14
w FE1_1s_B_SSOP28
GND_U1
C130 C240 R195
100nF 10uF
D1+
w 2.7K
D1-
CN15
ww NC/0
USB2_DP
USB2_DM
USB3_DM
1
To USB HUB +5V_USB
USB3_DP
1 R197 X2
1
1
1
VBUS 10 USB3_DM USB0_DM

D-
2 R196 USB3_DM w 12MHz Punch 3 more GND vias
3 10 USB3_DP 2 1
D+
R198 USB3_DP USB0_DP near by R5 GND side.
4
GND 5 R199
SHELL 6 ww NC/0
SHELL C132 C133 R203
w 18pF w 18pF w 10K
R201
USB2.0 SOCKET
6100-089110-0420 R200 NC/ESD * To enable UCS (BC1.2) mode,
BUSJ
NC/ESD pin 22 (DRV) & pin 19 (BUSJ)
must be High.
C C135 R204 C
w 100K
w 10nF
USB POWER
+5V_Normal_1
FB23
y 100/100MHz +5V_USB
+3.3V_Standby
U11
y NC/AO3401A
3 2
R268 R269 FB20

y NC/4.7K y NC/4.7K y NC/100/100MHz
+
C212
1
100uF
3
R225 1 Q21
USB_SW
USB_SW y NC/KMBT3904
y NC/10K
2
B B
Wifi_CONNECT
+5V_WIFI
GND_WIFI
CTL
D+
D-
1
1
1
1
1
1
R205 To USB HUB

2
R206
3 USB_WIFI_D+ w 5.1 USB2_DP
4 USB_WIFI_D- w 5.1 USB2_DM
5 FB21 +5V_Normal
6 CTR_WIFI WIFI_CTL
7 w 60/100MHz
R207 H :ON
8 w 100 L :OFF
D22
CN16 C136 C137 w NC/ESD
w CN-M w 100nF w 10uF +3.3V_Normal
D12 D13
5400-92112S-0600 w NC/ESD w NC/ESD R208
w 4.7K
WIFI_CTL WIFI_CTL 3
A A

Title
USB

C 1.0

5 4 3 2 1
5 4 3 2 1
EARPHONE/LINE OUT
+5V_Normal
MUTE CONTROL
FB15
22uF 22uF 60/100MHz
L :Normal AMP_MUTE AMP_MUTE
D D14 C209 C208 D
H :Mute BAV70
R209 2
+3.3V_Standby C138 HP-OUTL
3 R211 SD
4.7K R210
1 1K EARPHONE-OUTL 2.2uF OP_VCC1
H :Normal
3
R212 150
4.7K L :Mute
PWD_MT 1 Q12
5
6
7
8
KMBT3904 C139
+12V_PWR
3
IN2
BIAS
VCC
2.2nF
OUT2
2
R214 U14
C140 C141
R213 33K BH3544F-E2 100nF 10uF
D15 470K
BAV99
MUTE
OUT1
3
GND
IN1
R215 1 Q13
2
MMBT3906 OP_VCC1
C142 470K
4
3
2
1
2
2.2uF
R218
10K
HP/MUTE
HP-OUTR
C143 R217
HP_MT R220 HP/MUTE 2.2uF
1K EARPHONE-OUTR
3
150
R221 1 KMBT3904 C145
CE5 10K Q15 1uF
+
R216 C144
100K 100uF R263 2.2nF
2
33K
3
HP_MUTE R219 1 KMBT3904
HP_MUTE
Q14
H: MUTE, L: UN-MUTE 4.7K
RO_CN22
LO_CN22
GND_A
DET
CA33 CN25
R223 6100-024100-0500
HP-OUTL 220uF
1
1
1
1
C C
22
+
2
CA34 R222
HP-OUTR 220uF
+ 5
22
3
R278
+5V_Normal 4
4.7K
HP_DET R277 1
HP_DET
100
R276
10K
B
AUDIO AMP +12V_AMP
B
+12V_AMP +12V_PWR
R226 +12V_AMP
100K
SD
C146
R227 C147 220nF
100K 220nF L4 SPK_L+
C149 CE8
+
C148
1uF 100nF 100uF 22UH
29
AV_L_OUT# C150 100nF C151 U15 L5 SPK_L-

100nF 1 28 22UH
EP
2 /SD PVCCL 27 C152

R230 R231 3 /FAULT PVCCL 26 220nF
0 NC/33K 4 LINP BSPL 25
R229 5 LINN OUTPL 24
+12V_AMP 33K 6 GAIN0 PGND 23 C153
R228 NC/0 R232 GAIN1 OUTNL
7 22 C155 220nF C156
10 8 AVCC BSNL 21 220nF
C154 1uF 220nF
9 AGND BSNR 20 L6 22UH SPK_R-
R233
C157 10 GVDD OUTNR 19
1uF 11 PLIMIT PGND 18
R234 4.7K RINN OUTPR L7 22UH
3K 12 17 C159 SPK_R+
C158 1uF C160 13 RINP BSPR 16 220nF
AMP-INL R235 AV_L_OUT# 100nF 14 NC13 PVCCR 15
AMP-INL C162 CN9
150 PBTL PVCCR CN-M 5400-92112S-0200
R+
+12V_AMP 220nF
AMP-INR R236 AV_R_OUT# AV_R_OUT# C161 TPA3110D2 1
R-
AMP-INR SPK_L-
150 100nF C163 CE9
L+
2
+
SPK_L+
100nF 100uF
1
3
L-
1
4
1
C164 C165 SPK_L-

2.2nF 2.2nF SPK_L+
SPK_R- SPK_R- 1
SPK_R+ SPK_R+ 2
A 3 A
4
CN11
CN-M
5400-92112S-0210

Title
AMPLIFY

C 1.0

5 4 3 2 1
5 4 3 2 1
TUNER CASE & RF SW +3.3V_TU

T SI TUNER +3.3V_TU
24 MHz /ESR< 120 , CL=8pF
Y1 C166
22pF??
1
XTALO1 +3.3V_TU
ANT_PC_2 C1
2
FB16
2
C167
600/100MHz
4
8
close 20pin
11
8 21 9 k 47nF X3
9 10 C172 R238
24MHz C173
13
12
11
10
11 10 7 k 100nF 3.3
22pF??
XTALO1
7
1
XTALI1
C174 XTALI1
C1
C2
VDD
GND
4 5 2158 FOR LOW SINGER WATER WAVE 100nF +1.8V_TU
5 6 +3.3V_TU
2
C175 1 9
6 3 GND GND 2157 CAN CANCLE
Y2
k 1nF 2 8 1 Q16
3 ANT_PC_1 RF1 RF2
1
3 7 MMBT3906 +1.8V_TU
1
GND
GND
GND GND
RFC
C177 C178
C176 C179 C168 C169
3
CN29 1nF 1nF 1nF 1nF 1nF
D 1nF D
21
20
19
18
17
16
15
C180
4
5
6
k RF SOCKET U16
k PE42750MLAB-Z 2.2uF
GND
XOUT
XTAL_O
VDD_H
VDD_H
XTAL_I
LDO_ADJ
+1.8V_TU
ANT_PC_1 C181 C182 22 14
L8 L9
1
1nF 1nF 23 RF_REF VDD_L 13 R239 100 IF-IN+ IF-IN- DIFM

ANT_PC_2 RF_IP ALIF_P DIFM
CN30 2 24 12 100 IF-IN- IF-IN+ DIFP
1
2 270nH 270nH R240 DIFP

kk RF SOCKET 3 C183 25 RF_IN ALIF_N 11
3 4 R242 R243 R244 C213 RF_SHLD DLIF_P
C2 C2 C184 C185 180pF 26 10
4 R245 +3.3V_TU C237 IF-IN-DTMB
5 R241 10nF 10nF 82pF 27 ADDR U17 VDD_H 9
5 6 k ESD ESD kk NC/0 kk NC/0 kk NC/0 RSTB SI2157-A30-GMR DLIF_N d 100nF
6 C186 28 8
29 AGC1 VDD_D +1.8V_TU C238
L10 L11 180pF IF-IN+DTMB
L13 EP d 100nF
VDD_IO
330nH NC/180nH
GPIO1
GPIO2
AGC2
L12 270nH
GND
SDA
SCL
270nH
C187
1
2
3
4
5
6
7
NC/150pF +3.3V_TU
TUNER POWER +3.3V_Normal +3.3V_TU
R246 3.3V_TUNER 110MA
k 4.7K
R237 FB24
C1 60/100MHz
DTMB RM38 TS1_D0
TS1_D0
C3 k 100 +3.3V_TU FB17
D_RFAGC TS1_D1 IF-AGC 60/100MHz
TS1_D1
d 10K CM6 TS1_D2
TS1_D2
d 100nF TS1_D3 C190 C188 C189 C194
TS1_D3 100nF 22pF 22pF C191 C192 C193
TS1_D4 10uF 100nF 10uF 100nF
+1.2V_VDDM +1.2V_VDDM TS1_D5 TS1_D4
TS1_D5 R247 R248
TS1_D6 100 100
CM66 d 22pF XIN
VCC3V3/ TS1_D7 TS1_D6
TS1_D7
TUNER I2C
4
RM52
X5
TSSYNC_M d 33 TS1_SYNC TS1_SYNC
T_SDA
T_SDA
TS1_D0
TS1_D1
TS1_D2
TS1_D3
TS1_D4
TS1_D5
TS1_D6
TS1_D7
RM42 CM70 T_SCL
d 30.4MHz
d 1M d 100nF TSVLD_M d 33 TS1_VLD TS1_VLD T_SCL
C CM73 C
CM7 RM53
d 100nF
3
d 100nF
CM65 XOUT
12
11
10
d 22pF
9
8
7
6
5
4
3
2
1
TSB0
TSB1
TSB2
TSB3
TSB4
TSB5
TSB6
TSB7
PWM0
VDD12
VDD12
VDD33
49 Pin is exposed pad,

LM2
VCC3V3/
d 2.2uH
49
must connect to GND
DVB_T2 POWER CONTROL +3.3V_Normal
13 GND 48 VCC3V3/ VCC3V3/
CM69 XIN TSSYNC_M
XOUT 14 REFCLKI0 TSBSYNC 47 TSVLD_M
d 100nF REFCLKI1 TSBVLD
15 46 D_TSCLK
VDD_OSC TSBCLK D_TSCLK
LM3
16
17 CLK_REF_OUT U25 TEST1
45
44
RM39 RM40
d 51K
VCC3V3/ AVDD_ADC d ATBM8878 TEST0 d 100K
d 2.2uH 18 43 R106 R107
CM72 IFBP DBGSEL t 4.7K
d 100nF 19 42 Demod-RST t 10K
CM71 20 IFBN RESETN 41
d 2.2uF +1.2V_VDDM
2
IFAP VDD12 Demod-RST
21 40
IFAN VDD33 VCC3V3/ C3 R109 1
22 39 Q37
23 REF_BIAS_EXT TESTIO20 38 t MMBT3906
IF-IN+DTMB CM59 d 100nF VDD12 VDD33 VCC3V3/ t 10K
24 37
3
IF-IN-DTMB PWM1 VDD12 +1.2V_VDDM CM60
TESTIO23
CM68 d 100nF d 2.2uF

RM45 5V_DETE
VDD12
VDD33
VDD33
VDD12
I2CINT
R100
SDAM
SCLM
CM64 5V_DETE
SDAS
CM62
SCLS
t 10K
GND
GND
d 59K d 100nF d 100nF R108 C217

+5V_Normal t 22K t 100nF
+1.2V_VDDM
CM63 CM61
25
26
27
28
29
30
31
32
33
34
35
36
CM67 d 100nF d 100nF

d 100nF
CM82 Q36
d 100nF L52
t AO3401A
RM49 RM46 F2 t 1K/100MHZ
d NC/100 d NC/4.7K 3 2 ANT_PC_1
T_SDA
+1.2V_VDDM
T_SDA C214 t 200mA/24V

T_SCL RM44 CM75 t 100nF
T_SCL CM80 CM81 R102
d NC/100 d NC/22pF d 100nF
R282 C215
VCC3V3/
+1.2V_VDDM
CM74 d 100nF t 10K t 10K
1
d NC/22pF t 100nF
RM47 R105
d NC/4.7K
3
B 1 t 10K B
VCC3V3/ Q18
RM41
3
d 100K t KMBT3904
C1 R101 1
RM48 d NC/100
2
+3.3V_Normal
d NC/100 +1.2V_Demod C218 t 10K
RM43 t 100nF
2
M-SCL
M-SCL RM51 d 100 FB29 Q25
FB28
M-SDA RM50 d 100 d 600/100MHz d 600/100MHz t KMBT3904
M-SDA
CM78 +1.2V_VDDM VCC3V3/

CM79 CM77
d 22pF d 22pF CM76 d 10uF
d 10uF
H12
1
1 2
2 3
3 4
4 5
5 6
6
IF AGC Switch R823 dd 100
TUNER SURPORTER & CONNECTOR TUNER-J
CN22
IF-AGC 3 2 IF-AGC-T IF-AGC 3 2 D_RFAGC 1 IF-AGC
IF-AGC-T 1 +3.3V_TU_2
Q803 Q808 2 +3.3V_Normal
+5V_Normal +5V_Normal d MMBT3906 2 3 T_SDA
d MMBT3906 +3.3V_TU_2
3 4 T_SCL +5V_Normal
1
4 5 FB25
R816 R814 R822 R821 5 6 FB27
60/100MHz
d 10K d 100K d 1K d 100K +3.3V_Normal 6 7 DIFM
7 8 60/100MHz
8 9
R281 9 10 DIFP C242
C241
3
d 4.7K 10 100nF
10uF
A Q806 1 R815 Q807 1 R819 IF-AGC-SEL A
d KMBT3904 d KMBT3904 d 10K IF-AGC-SEL CN5X2-J1
d 100K
2

Title
TUNER

C 1.0

5 4 3 2 1
5 4 3 2 1
NAND FLASH
NC/22
NAND-DQS R250 NAND_DQS
NAND_DQS
+3.3V_Nand +3.3V_Nand +3.3V_Nand NAND-WPZ NAND_WPZ
8 7 NAND_WPZ
NAND-WEZ NAND_WEZ
6 5 NAND_WEZ
U18 K9F2G08U0C-SCB0 NAND-ALE NAND_ALE
4 3 NAND_ALE
NAND-CLE NAND_CLE
1 48 2 1 NAND_CLE
D NC1 NC48 RM7 D
2 47
R251 3 NC2 NC47 46 22 X 4 C195
10K 4 NC3 NC46 45 NC/33pF
5 NC4 NC45 44 NAND-D7
6 NC5 I/O7 43 NAND-D6
NC6 I/O6 NAND-CEZ1 NAND_CEZ1
NAND-RBZ 7 42 NAND-D5 8 7 NAND_CEZ1
R//B I/O5 NAND-CEZ NAND_CEZ
NAND-REZ 8 41 NAND-D4 6 5 NAND_CEZ
/RE I/O4 NAND-REZ NAND_REZ
NAND-CEZ 9 40 4 3 NAND_REZ
/CE NC40 NAND-RBZ NAND_RBZ
NAND-CEZ1 10 39 2 1 NAND_RBZ
NC10 NC39 RM8
11 38 R252 NC/0
12 NC11 NC38 37 22 X 4
C196
13 VCC VCC 36 Micron Nand should NC NC/33pF
14 VSS VSS 35 NAND-DQS
15 NC14 NC35 34
NAND-CLE 16 NC15 NC34 33 NAND_D[7:0]
NAND-ALE 17 CLE NC33 32 NAND-D3 22 X 4
NAND-WEZ 18 ALE I/O3 31 NAND-D2 NAND-D0 RM9 NAND_D0
/WE I/O2 NAND-D1 8 7 NAND_D1
NAND-WPZ 19 30 NAND-D1
/WP I/O1 NAND-D2 6 5 NAND_D2
20 29 NAND-D0
NC20 I/O0 NAND-D3 4 3 NAND_D3
21 28
NC21 NC28 2 1
22 27
23 NC22 NC27 26
NC23 NC26 NAND-D4 NAND_D4
24 25 8 7
NC24 NC25 NAND-D5 NAND_D5
C NAND-D6 6 5 NAND_D6 C
C197 4 3
100nF C198 NAND-D7 NAND_D7
100nF RM10 2 1
22 X 4
+3.3V_Normal +3.3V_Nand
C199 C200 C201

2.2uF 100nF
100nF
B
NAND Power B
A A

Title
NAND FLASH

B 1.0

5 4 3 2 1
5 4 3 2 1
D D
[+5V_Normal==>3.3V,100mA]
4
OUT OUT
UM03
m LD1117-3.3 [SPI Flash] VCC3.3V_6M30
[Chip Config]
ADJ
VCC3.3V_6M30
IN
VCC3.3V_6M30 VCC3.3V_6M30 AVDD_LVDSRX1 VDDP1 {PAD_GPIO[2:0]} VCC3.3V_6M30 UM04

BOOT_SPI 3b'111 mEN25F10-100GIP CM48
1
m 100nF
+5V_Norm al RM60 SPI_CZ 1 8
SPI_DO 2 /CS VCC 7
GPIO0 m 10K DO /HOLD
RM61 3 6 SPI_CK
4 /WP CLK 5 SPI_DI
m 10K RM01 VSS DI
CM25 CM27 RM62 m 10K
CM26 CM28
C118 C171 C206 C170 CM24 m 100nF
m 100nF m 100nF GPIO1 m 10K
m 10uF m 100nF RM19
m 2.2uF m 100nF m 2.2uF m 100nF m 10K
RM20
GPIO2 m 10K
RM21
m 10K
AVDD_MOD1
FBM01
m 60/100MHz
CM29 CM30
m 100nF m 100nF
AVDD_MPLL
FBM02
m 60/100MHz
CM31
m 100nF
m 0 X 4
LVA4N RM28 RXO4+
LVA4N LVA4P 2 1 RXO4-
LVA4P LVA3N 4 3 RXO3+
LVA3P 8 7
LVACLKN RM27 m 0 X 4 RXOC+
LVACLKN LVACLKP 2 1 RXOC-
LVACLKP 4 3 RXO2+
LVA2N 6 5 RXO2- [I2C_S Port & UART Port ]
LVA2N LVA2P 8 7
LVA2P m 0 X 4 CN13
[VCC3.3V==>1.8V DDR,240mA] LVA1N
LVA1P
LVA1N
LVA1P
LVA0N
RM17
2
4
1
3
RXO1+
RXO1-
RXO0+
m CN-M
1
2
3
4
5
6
7
LVA0P 8 7
I2CS_SDA 1
I2CS_SCL 1
C C
GND_CN13 1
VCC1.8V AVDDIO_CMD1 AVDDIO_MCLK AVDDIO_CMD0
VD_TX 1
VD_RX 1
VD_TX
VD_RX
I2CS_SDA
I2CS_SCL
4
m 0 X 4
UM22 RM18
LVB4N RXE4+
OUT OUT
m AS1117L/TR-HF LVB4N 2 1
CM41 CM42 CM43 CM44 LVB4P RXE4-
VCC1.8V m 10uF m 2.2uF m 100nF LVB4P 4 3 SPI_DI AVDD_MOD1
DVDD_DDR_DATA
m 100nF LVB3N RXE3+
AVDDIO_DATA0
AVDDIO_DATA1
LVB3N LVB3P 6 5 RXE3- SPI_CK
R2
ADJ
LVB3P 8 7 SPI_CZ
R286
IN
m 330 LVBCLKN RM26 m 0 X 4 RXEC+ SPI_DO

VCC3.3V_6M30 LVBCLKN 2 1 DIM6 GPIO6 RM70
LVBCLKP RXEC-
VDDP1
DVDD
DVDD
1
LVBCLKP 4 3 RXE2+ PWM5 m 39K Close to Mstar IC

LVB2N 6 5 PWM4
AVDDIO_DATA1 LVB2N RXE2-
AVDDIO_DATA0 LVB2P 8 7 DIM3 PWM3 GPIO3 A0P
LVB2P DIM2 GPIO2 A0M
LVB1N RM29 m 0 X 4 RXE1+ PWM2
LVB1N 2 1 PWM1 IRE A1P
LVB1P RXE1- RM03
R285 LVB1P LVB0N 4 3 RXE0+
VD_RX m 100 DIM1 GPIO1 A1M
C236 C235 C233 C234
m 150
R1 m 2.2uF m 100nF m 2.2uF m 100nF
LVB0N
LVB0P
LVB0P 6
8
5
7
RXE0-
VD_TX
RM04
m 100
DIM0 A2P
A2M
ACKP
CM45 CM46 CM47
m 100nF m 100nF m 100nF ACKM
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
Vout=1.25V*(1+R1/R2)
DVDD_DDR_DATA
AVDDIO_DATA0
AVDDIO_DATA1
PAD_SPI_CZ
PAD_GPIO[1]
PAD_GPIO[2]
PAD_GPIO[3]
PAD_GPIO[4]
PAD_GPIO[5]
PAD_GPIO[6]
PAD_SPI_CK
PAD_SPI_DI
PAD_REXT
PAD_ACKM
PAD_SPI_DO
PAD_ACKP
PAD_A0M
PAD_A1M
PAD_A2M
PAD_A0P
PAD_A1P
PAD_A2P
VDDP3_L
MARK
MARK
DVDD
DVDD
E-Pad
Test
GND
RM06
PWM0 GPIO0 1 102 IRE A3P
m 100 PAD_GPIO[0] PAD_A3P
GPIO16 2 101 IRE A3M
M-SCL 3 PAD_DIM0 PAD_A3M 100 IRE
GPIO17 A4P
M-SDA PAD_DIM1 PAD_A4P
IRE GPIO18 4 Pin116 reserved 99 IRE A4M
RM05 PAD_DIM2 PAD_A4M
m 100 IRE GPIO19 5 98
PAD_DIM3 AVDD_MOD AVDD_MOD1
AVDD_LVDSRX1 6 97
AVDD_LVDSRX AVDDL_MOD AVDDL_MOD1
RXE0- 7 96
PAD_RA0N DVDD DVDD
CM52 CM51 RXE0+ 8 95 B0P
RXE1- 9 PAD_RA0P PAD_B0P 94 B0M
m 22pF m 22pF
[12V==>1.18V core power,1A] RXE1+
RXE2-
RXE2+
10
11
12
PAD_RA1N
PAD_RA1P
PAD_RA2N
PAD_B0M
PAD_B1P
PAD_B1M
93
92
91
B1P
B1M
B2P
RXEC- 13 PAD_RA2P PAD_B2P 90 B2M
UM01
RXEC+ 14 PAD_RACKN PAD_B2M 89 BCKP
m MST6M30KUX
LVDS OUT1 PAD_RACKP PAD_BCKP
MST6M30KUX
RXE3- 15 88 BCKM
RXE3+ 16 PAD_RA3N PAD_BCKM 87 B3P
CN33
m CN-F RXE4-
RXE4+
17
18
PAD_RA3P
PAD_RA4N
PAD_B3P
PAD_B3M
86
85
B3M
B4P
53
AVDD12_LVDSRX
19 PAD_RA4P PAD_B4P 84 B4M
+12V_Panel
52
51
LVDS OUT2 AVDD_LVDSRX1
20 AVDD12_LVDSRX/DVDD
AVDD_LVDSRX
PAD_B4M
AVDDL_PREDRV
83
AVDDL_PREDRV
RXO0- 21 82
50 RM80 m NC/0 I2CS_SCL PAD_RB0N AVDD_MOD AVDD_MOD1
RXO0+ 22 81
VCC1.18V 49 PAD_RB0P AVDDL_PREDRV AVDDL_PREDRV
FB8 UM02 RM81 m NC/0 I2CS_SDA CN35 RXO1- 23 80 C0P
m 60/100MHz
mMP1494DJ-LF-Z 48 m CN_F RXO1+ 24 PAD_RB1N PAD_C0P 79 C0M
4 5 R249 C223 L14 47 PAD_RB1P PAD_C0M
RM82 m NC/0 Glas s _Sync 43 RXO2- 25 78 C1P
3 GND BST 6 m 100nF m 10uH 46 PAD_RB2N PAD_C1P
SW EN/SYNC m 22 42 RXO2+ 26 77 C1M
2 7 R261 45 RM83 m NC/0 MODE RXOC- 27 PAD_RB2P PAD_C1M 76 C2P
1 IN VCC 8 MODE 41
R280 m 1K 44 RXOC+ 28 PAD_RBCKN PAD_C2P 75 C2M
m 100K AAM FB 40 PAD_RBCKP PAD_C2M
43 RXO3- 29 74 CCKP
R124 39
AVDDIO_CMD1/AVDDIO_MCLK
R1 42 RXO3+ 30 PAD_RB3N PAD_CCKP 73 CCKM
38
41 31 PAD_RB3P PAD_CCKM 72
m 1K/?? C227 R279 C207 37 RXO4- C3P
40 A0P RXO4+ 32 PAD_RB4N PAD_C3P 71 C3M
m 220nF/?? m 604 m 10uF 36
R266 39 A0M 33 PAD_RB4P PAD_C3M 70 C4P
m 82K R267
35 AVDD12_LVDSRX AVDD12_LVDSRX/DVDD PAD_C4P
38 A1P 34 69 C4M
m 100K
34
C225 C221 37 A1M IRE 35 PAD_SSPI2_DO PAD_C4M 68
C224 33 DVDD
m 10uF m 100nF

R275 36 A2P [3D Flag] 36 PAD_SSPI2_CZ DVDD 67
DVDD_DDR_CMD
C226 m 100nF 32
m 10uF m 3.3K 35 A2M
C0P
PAD_SSPI2_CK AVDDL_MOD AVDDL_MOD1
37
PAD_I2CS_SDA
66
PAD_I2CS_SCL
R2 3D_FLAG RM09 3D_FLAG_IN
AVDDIO_CMD0
AVDDIO_CMD1
31 C0M 3D_FLAG AVDD_MOD1
PAD_SPI4_CK
PAD_TESTPIN
R264 34 m 100 38 PAD_SSPI2_DI AVDD_MOD 65
PAD_SPI4_DI
30 C1P D0P
m NC/10K
AVDD_MPLL
PAD_RESET
PAD_XTALO
33 ACKP VDDP1 VDDP3_B PAD_D0P
PAD_DCKM
PAD_XTALI
PAD_DCKP
R294 29 C1M
PAD_D4M
PAD_D3M
PAD_D2M
PAD_D1M
PAD_D0M
32 ACKM
PAD_D4P
PAD_D3P
PAD_D2P
PAD_D1P
m 100 28 C2P
31 Any GPIO
27 C2M
DVDD
DVDD
30 A3P support L/R in
26
29 A3M L/R out can
25 CCKP use PWM
28 A4P
24 CCKM function pins
27 A4M 23
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
B [1.18V] AVDD12_LVDSRX DVDD 26 RM84 m NC/0 3D_EN_U B
22 C3P
25 RM85 m NC/0 LR_SYNC
VCC1.18V 21 C3M RM65
24 B0P VCC3.3V_6M30 m 4.7K D0M
20 C4P
23 B0M D1P
19 C4M FOR_UM01
22 B1P D1M
18
21 B1M RM66 D2P
17
20 B2P m 4.7K
CM02 CM03 CM04 CM05 CM06 CM07 CM08 CM09
19
16 D0P D2M HS GND
B2M DCKP GND
CM01 15 D0M
m 10uF
m 100nF m 100nF m 100nF m 100nF m 100nF m 100nF m 100nF m 100nF 18
14 I2CS_SCL RM67 m 100 DCKM
D1P
17 BCKP I2CS_SDA RM68 m 100 D3P
13 D1M
16 BCKM
12 D3M 1505-M0300300-22
DVDD
DVDD
D2P
15
AVDD_MPLL
AVDDIO_MCLK
Rt R1 R2 Vout
AVDDIO_CMD0
AVDDIO_CMD1
D4P
DVDD_DDR_CMD
11 D2M
14 B3P D4M
33K 20K 3.6K 5.0V 10
13 B3M 9 DCKP
AVDDL_MOD1 33K 11.25K 3.6K 3.3V 12 B4P
8 DCKM VCC3.3V_6M30
11 B4M
33K 3.15K 3.6K 1.5V 7
10 RM86 LOCAL_DIMMING_EN LOCAL_DIMMING_EN 6 D3P
9 m NC/0
3
33K 1.8K 3.6K 1.2V
FBM03 5 D3M
8
4 D4P
7
m 60/100MHz 3 D4M R117
CM12 CM13 CM14 CM15 Vout=0.8x(1+(R1/R2)) 6
2 m 1M D16
m BAV99
CM11 5
CM10 m 100nF m 100nF m 100nF m 100nF 1 RM69
4
m 10uF R1=R0P9 +12V_Panel C228
2
m 10uF 3 m 2.2uF m 1M
2
R2=R1P7 XM01
2
1
R116 1 m 24MHz
Rt=R1P2 Q24
m MMBT3906 2 1
AVDDL_PREDRV m 100K
3
R121m 1K
RESET
RM22 C222
m 33 m 1uF?? C232 CM49 CM50
GPIO2 LR_SYNC R119
FBM04 m 1nF m 22pF m 22pF
GPIO3 RM23 m 33 Glas s _Sync m 100K
GPIO6 3D_EN_U
m 60/100MHz
CM17 CM18 CM19
CM16 CM20 RM24
m 10uF m 100nF m 33
m 100nF m 100nF m 100nF
DVDD_DDR_CMD DVDD_DDR_DATA
FBM05
m 60/100MHz
CM21 CM22 CM23

m 10uF m 100nF
m 100nF
A A

Title
NAND FLASH
Size Docum ent Num ber Rev

E 1.0
5 4 3 2 1
5 4 3 2 1
Connector
D D
GND
RX+
TX+
TX-
RX-
Ethernet SG1
2
1
1
TN1 U21
AZ3028-04P??
1
MDI_TP R257 5.1 1 16 1 8 1
MDI_TP 2 15 R253 I/O1+ I/O2+ TX+
2 7 2
MDI_TN R258 5.1 3 14 75 3 I/O1- I/O2- 6 3 TX- 9
MDI_TN 4 13 I/O3+ I/O4+ RX+ GND
TD TX 4 5 4 10
5 12 I/O3- I/O4- 5 4 GND 11
R254 75
MDI_RP R259 5.1 6 RD RX 11 6 5 GND 12
MDI_RP 7 10 R255 75 RX- GND
7
MDI_RN R260 5.1 8 9 8 7
MDI_RN 8
R256 75
CN21
TRANSFORMER
1
NETWORK SOCKET
1
C202 C203
1
SG3
SG4
SG5
SG6
100nF 100nF
C204
1
SG2
2
C205
1nF
2
1nF
2
+3.3V_Standby
2
C C
6
5
4
C231
GNDVDD
I/O1 I/O4
I/O2 I/O3
100nF U19
AZ1013-04S??
1
2
3
B B
A A

Title
ETHERNET

B 1.0

5 4 3 2 1
5 4 3 2 1
20131118 HDMI6100-150110-19496100-150110-1960
20131209 R2941.177V
20131118 CN28 32 20131209 R285/R286.
20131119 LVDS 20131209 6M30
20131119 Q36 20131211 CA33/CA34470uF220uFFOR U9
20131120 R290R291,R294,R295 20131211 IC R15
20131120 ICL17/L18/M18/M16/M17SPIRM1 PCB
201312023 C58/C61IC
201312023
D
201312023 IC D
20131120 R115LED 201312023 ;

201312023 2.5MM
20131121 CN29 201312023 PCB
20131121 TUNRT CN22CN23;CN29 201312023 1505-M0420400-2302
20131121 LVDS+12V_Panel
20131121 TUNER CN30
20131213
20131122 TUNER
20131122 C170C171(+3.3V_TU) 201312023 FB9
20131122 3MOS U8U11Q36 20131216 FB5/FB6/FB7/FB28/FB29,RM46/RM47,R64,R238
20131216 CN16,TN1
20131125 R257/R258/R259/R260/C206/C207 U19/C231 20131216 CM51/CM52,RM05/RM06
20131125 H3/H6/H12MARK 20131216 R23804020603
20131125 CN5/CN16 PCB 20131216 R300
20131126 CN9/CN11 PCB 20131217 L10482S-S033B0-5300U22/U3/U7/U6
20131217 C68IC
20131127 y_Q21Q21
20131217 X5,CM11,CM24,CM25
20131127 R501K100 20131225 R8033K
20131127 R91NC/1K1K;R49/R62 b 20131231 R295
C
20131127 R216NC,;R197/R199ww 20131231 HP_DET5V_DETE IO C
20131127 U2/U5j 20140102 F2

20131127 R1522.122 20140102 R195
20140102 C108/C11027P,24.0003667MHz
20131127 R43/R69
20140103 R101,Q25,R282;C239/C240.Q18FB25/F1.C212100uF
20131128 R120 20140106 CN4u13
20131128 D2/D3/D44100-L60000-Z300 4100-L18002-T0 20140108 RM05/RM06
20131128 C1014300-CB1050-A200 4300-CC105D-T2 20140108 CN22/H12
20140108 R2421X2MM,.CN23
20131128 C11144300-CD1050-73004300-CC105D-T2
20140108 C312
20131128 C954300-CD223D-T54300-CF1030-7200 20140110 AV
20131128 D18/D19/D20/D214500-75V3U0-0S004100-L18002-T0/NC 20140114 RM44RM49
20131128 C1134300-KC227E-T044300-KC107E-T0
20131202 CON1 DTMB. 20140121 U22UM22
20131202 +24VF2. 20140121 X10.6MM
20131202 3D Glass CN24 20140121 ICRM28,RM27,RM17,RM18,RM26,RM29
20131203 CN9/CN11/CN5/CN17 20140124 CN4
201311204 IC L17/L18/M18/M16/M17SPIRM1
20140124 ES
201311204 CN2.
201311204
201311204 R253/R254/R255/R2560805
B 201311204 C202/C203,R257/R258/R259/R260. 20140124 B
20140211 NOTE
20140211
20140213 UM01 6M30 IC
20140213 UM01 6M30 IC PIN131
20140218
20140219
20140220 H13,H14.CN4
20140220 2.
20140221 lvds
20140221 R196/R198 5.1----10
A A

Title
CHANGE LIST

C 1.0
5 4 3 2 1
H11x1
H11
H11
CN9x4 CN9x3 CN1 x4 CN1 x3 CN16x7 CN16x8 CN4x1 CN4x10 CN4
H1x8 H1x5 H1x7
H10x1 CN4x9 CN4x8 CN4x7 CN4x6 CN4x5 CN4x4 CN4x3 CN4x2 CN4x1
CN13x7 CN13x6 H7x8 H7x5 H7x7
CN4
H1x4 H1x3 C107x1 D3x1 D4x1 C106x1 R79x1 R81x2 D2x1 R115x2 R76x1 Q7x3 H7x4 H7x3
H7
CN13
C107x2 D3x2 D4x2 C106x2 R79x2 R81x1 D2x2 R115x1 R76x2
C107
D3
D4
C106
R79
R81
D2
R115
R76
Q7x1 Q7x2
H1
H7
H1x2 H1x6 H1x9
R84x2 R83x2 R82x2 R85x2 C104x1 C105x1 R65x1 R68x1 R73x1 R80x2
H1x1 CN13x5 CN13x4 CN13x CN13x2 CN13x1 H7x2 H7x6 H7x9
H7x1
CN11
R84x1 R83x1 R82x1 R85x1 C104x2 C105x2 R65x2 R68x2 R73x2 R80x1
CN13
Q6x3
C105
R68
H10
CN9x2 CN9x1
CN16
CN1 x2 CN1 x1 CN16x CN16x5 CN16x4 CN16x3 CN16x2 CN16x1
H10CN9
R52x1 R70x2
R80
C137x1
R83 D3
R82 D4
FB21x1
D13
D12
R208x1 R207x2 D22x1 C136x1 D13x1 D12x1
Q7 Q6
Q6x1 Q6x2 R52x2 R70x1
R52
H1
R80 R52
R70
C137
C136
C146x2 C152x2 C156x1 R208x2 R207x1 D22x2 C136x2 D13x2 D12x2
CN2x16
R84 C107
R85 C106
L6x1
R208
R207
D22
C136
R274
L5x1 FB21x2 Q7
R208
R70
C137x2
FB21
R113x2
R205x2 R206x2
C146
R65 D2 R81
R73 R76 R115
C146x1 C152x1 C156x2 Q6 R113x1 CN23x15
R73
C146
C152
C162x2 C162x1 R205x1 R206x1 CN2x15
R65
R68
D13 R205
D12 R206
R113
R30
C162
R111x1
C104 R79 C104

C105
C128x1
C126x1 FB22 R111x2
C137 FB21
C128x2
R113 R111
R205
R206
R84
R83
R82
R85
R31
R273C36
L6x2
R111
R6
L5x2 CN23x14
CN2x14
C128
Q2
R202x2
C126
C162
L5
FB10
R29
R22
L6
CN18x3 C155 C126x2 R202x1 R272x1 Q23x1
C126
Q22x1
C128R202
D22 R207
R274x1 R273x1
R2x2 R3x2
R2
R3
Q2x1 R128x2 R6x1 R1x2 Q22x3 R272x2 Q23x3 FB26x2 CN23x13
CN2x13
L4
R272 R272
FB13x2
C156 C156C152
R274x2 R273x2
CN18
C153
C155x2 C155x1 R189x1 C134x2
R274
R273
R2x1 R3x1 Q2x3 R128x1 R6x2 R1x1 C26x1 C26x2 Q23x2
Q22x2
C155
L7x1
R128 R128
R6
R189x2 C134x1 R270
C159
CN16
R189
C134
Q2x2
L4x1 X2x1 FB13x1 R271x2 R271x1 R270x2 R270x1
R1
FB26
R265x2 R32x2 R4x1
R270
C216 CN2x12
CN23x12
L7
C153x1 C153x2 C159x1 R194x1 R265x1 R32x1 Q1x1 R4x2 C27x1 C27x2 FB26x1
FB26
Q19x1 R31x2 C36x2
U8x1
CN18x1
Q22 R271U8
C147 R194x2 R130x1 R63x2 Q1x3 C28x2 C28x1
C220x2 C220x1 FB3
R1 R4Q1
Q19x3 R5x1 CN5x12
Q23R271 C220
R29x2 R22x1 R31x1 C36x1 C219 CN23x11
CN2x11
R31
C36
U8x2
C31 R25
C159x2 L7x2 R192x1 R203x1 R130x2 R63x1 Q19x2 Q1x2 R5x2
Q19
R2 R265 R130
FB14x2 R29x1 R22x2 R30x2 R30x1 U8x3
R202 C134
U5x4 U5x3 U5x2 U5x1
R30
Q22 U8
X2
L4x2 R192x2 R203x2 U20x4 U20x3 U20x2 U20x1 C216x2
R125x1
CN2
C147x2 C147x1
CN9 L5 L4
C149x2 Q28x1 Q17x1 R27x2 C31x2 C216x1 FB3x2 CN23x10
CN2x10
FB3x1 CN5x10
C153 C147
U5
FB14x1
Q23C220 C216
C149 R193x2 R204x2 R125x2
C26 C27 C28
R194 R192
R189FB13 R203
C163x2
R5 R125
R4 R5 R125
C149x1 Q28x3 Q17x3 R27x1 C31x1 FB22x2 FB22x1
C149
C26C27C28U5
R193x1 R204x1
CN18x2 U5x5 U5x6 U5x7 U5x8
CN23
C163x1
Q17
Q28x2 Q17x2 R127x2
C163
Q28
Q2 Q19 Q28
U15x28 U15x27 U15x26 U15x25 U15x24 U15x23 U15x2 U15x21 U15x20 U15x19 U15x18 U15x17 U15x16 U15x15 C219x1
CE9
D21x1
CE9x1 C129x2 C135x1 C127x1 R127x1 C25x2 R23x2 R26x2 R28x1 R25x2
FB19x1 CN23x9
CN2x9
FB19x2 CN5x9
FB3 FB19
Q9
D21x2
X2x2 C129x1 C135x2 C127x2
FB10x1 FB10x2 FB19
X2
R262x2 R129x2 Q9x1 C25x1 R23x1 R26x1 R28x2 R25x1
R3 R32 R63 R32 R265
FB13 R194R192 R193 C129

R203 R204 C135
FB14 C127
D21
CE8x2 CE8x1 R126x2 C219x2
C159 U15
R23
R26
R28 R29 R27 R28
R27 R22 C31 R25
D21
R130
U20x5 U20x6 U20x7 U20x8
C219
FB18
FB14
C133x2 C132x2 R262x1 R129x1 Q9x3 R126x1 C30x1 C30x2 CN5x8
CN23x8
CN2x8
R262
R129
U15x29 Q9x2 R123x2
R63
C133x1 C132x1
C132
R193
R204
C25
R23
C25 R26
C239
C127
R123x1
CE8
C163
R123
C29x2 C29x1 FB18x2
CE8
R226x2 U15x1 U15x2 U15x3 U15x4 U15x U15x6 U15x7 U15x8 U15x9 U15x10 U15x1 U15x12 U15x13 U15x14 Q5x1 CN5x7
CN2x7
CN23x7
U13x1 U13x28
CN11L6L7CE9
U13x2 U13x27
R123
R226x1
CE9x2 RM03x2 RM04x2 FB18x1
U15
FB9
R127 R126 Q5
Q5x3
R226
FB18
U13x3 U13x26 C131x2 C131x1
C133
C133 C132
R127 R126
C135C129
R227x2 C148x2 C151x2 R230x1 R228x1 C154x2 R233x2 C160x2 C161x2 C165x1 U13x4 U13x25
RM03x1 RM04x1 Q5x2 C121x2 C121x1
RM03
RM04
Q1 Q17 Q9 Q5
FB22 FB10C30 C29 C121
C239x1 U13x5 U13x24
CN5x6
CN23x6
CN2x6
L3
CN15x5 R227x1 C151x1 R230x2 R228x2 R233x1 C160x1 C161x1 C165x2
R227
C148x1 C154x1 U13x6 U13x23
CN5
U13x7 U13x22
FB9x2 FB9x1
C29 C121
U20 C30 C131
C157x2 C158x2 U13x8 U13x21
CN15x1 C239x2 C164x1 C150x2 R235x2 R231x2 R229x2 R232x2 R234x1 R236x2
L3x2 L3x1 CN5x5
CN23x5
CN2x5
CN15
U13x9 U13x20
C130x1 C130x2 C164x2 C150x1 R235x1 R231x1 R229x1 R232x1 R234x2 R236x1 U13x10 U13x19
R226 C164
C148 C150
C151 R235
R230 R231
R228 R229
C154 R232
C165 R236
C157x1 C158x1 C226x1 C226x2 FB8x2 FB8x1
FB9 FB8
U13
C161 C158
U13x11 U13x18
R200x2 U13x12 U13x17
CN15x2
R200x1 R196x1 R196x2 R196 U13x13 U13x16
CN5x4
CN23x4
CN2x4
U13x14 U13x15
C118x2 C236x2
C225x1 C225x2 C225 C117x2
U20 C131C226C225
C171x1 C235x1 R286x2 R285x2 C221
R201x1
U13
C160 R234 R228
R198x1 R198x2 R198
R196 R198
CN15x3 R197
C171C118
C117
C171x2 C235x2 R286x1 R285x1 C221x2 C221x1 CN5x3
C221
R195x2 R195x1 R197x2 R197x1 CN23x3
CN2x3
C171
C235
R286
R285
R201x2 C118x1 C236x1
R195
C239C130R200R201
C130 R200 R264x2 C117x1
C118
R195 R199
C117
R199x2 R199x1 UM02x4 UM02x3 UM02x UM02x1
R262 RM03
R129 RM04
R264x1
R197R199
L14
R227
R233
C160
CN15x4 R169x2
C164
FB8 C226R280
R201 UM03x3 UM03x2 UM03x1 UM22x3 UM22x2 UM22x1 C223x2 CN5x2
CN2x2
CN23x2
C235C236
C236R285
R266x2 R280x1 R169x1
R169
C223x1
C223
R266x1 R280x2
UM02
L14x1 L14x2 UM02x5 UM02x6 UM02x7 UM02x8
L14
CN5x1
R233 C157 R230C151 R235

R231
C154 R232
R234C157
C165C161 C158
R236
R249x2 C227x1 R267x2 C224x1 R124x2 CN23x1
CN2x1
UM22
R264 R266
CN15x6 C211
R286 UM03
R249x1 C227x2 R267x1 C224x2 R124x1
UM02 R280 R124

Q11CE5x2 CE5x1 R21R19 C207x2 CM01x2 RM1x2 RM1x4 RM1x6 RM1x8
C148 C150CE5
C142x2
D15 RM1x1 RM1x3 RM1x5 RM1x7
R261x2 R279x1 R275x2 R294x1 CN5x11
R124
RM1
R103 C207x1 CM01x1 CN2x17
CN23x16
C224 R294
UM03
UM03x4 UM22x4 R261x1 R279x2 R275x1 R294x2
C223 R249 R261

C227 R279
R267 R275
R264 R266 C224 R294
CM01
C142x1
CN2
CN23
R147 CM41 R169RM1
CE5
C142
D15x2 D15x1
D1 D17
Q11x2 R216x2 R213x1 R215x2 R18 CM24x2 CM10CM15
R279
C206x1 C233x1
CN8
C170x1 C234x1
C207
C32x1 C32x2
C32C33 CM44
Q11x3 R216x1 R213x2 R215x1
D1x2 CN33x53
C207CM01
FBM03
R213
R229 C142 R215
C170x2 C234x2
R213
C170
Q11x1 D15x3 C206x2 C233x2 CM21
C206
C33x2 C33x1 CM24x1 RM86x2 RM86x1
C206
FBM03x2 FBM03x1
C32 C33
CM10x1 CM10x2
CM24
CN8x22 CN8x20 C145x2 RM01x1 CN33x51
C227R249R261
CM10
R67x1 Q13x2 Q13x1 D14x3 CM48x1 FBM04
R147x1 R147x2 R153x2 R153x1 RM85x2 RM85x1 CN33x50
Q20
Q11 R147
RM01x2 CN33x49
CN8x19 R67x2 CM48x2 CM41x2 CM41x1 FBM05x1 CM15x2 CM15x1 FBM04x2 FBM04x1
C233RM01
R215
C234 CM48
C145x1 U6x3 U6x2 U6x1 CN33x48
C233RM01
R67
C234CM48
R216 R216
CN8x18
R148x2 R148x1 RM84x2 RM84x1
C145
Q13
CM16 CN33x47
CN8x17 CM14x2 CM14x1
C170 CM24
Q13x3 D14x1 D14x2 RM66 CM44x1 CM44x2 CN33x46
R267 R275 CM15 CM14
R112
CN8x16 R150x1 R150x2 R152x1 R152x2
D1x1
Q20x3 RM80x2 RM80x1 UM04x1 UM04x8 FBM05x2
CN33x45
FBM05
R7x1 R112x2 CM14
CN8x15 CM16x2 CM16x1 RM82x2 RM82x1
RM65 CN33x44
D14
R220x1 R219x2 R263x1 R221x2 R214x1 R212x2 R209x1
FBM05
CN8x14
R7
R149x1 R149x2 R151x1 R151x2 R7x2 R112x1 RM81x2 RM81x1 UM04x2 UM04x7 CN33x43
CN8x13
R7
U6
R153 R148 R152 R151

R220x2 R219x1 R263x2 R221x1 R214x2 R212x1 R209x2 CM21x1 CM21x2 RM83x2 RM83x1 CN33x42
R67 C145
CN8x12
RM86 RM85 RM84 RM82 RM83
R219
R263
R221
R214
R212
R209
CM17x1 CM17x2
R214
Q20x1 Q20x2 RM70x2 CM17 CN33x41
RM86
CM41 CM44 CM21
R220
CN8x11 R78x1 RM67x2 RM67x1 RM66x2 RM66x1 UM04x3 UM04x6
R153 CN33x40
CN8x10 RM6x1 RM6x2
Q14x2 Q14x1 RM70x1 CM19x1 CM19x2 CN33x39
RM85
CN8x9 RM6x3 RM6x4
Q15x2 Q15x1 Q12x2 Q12x1 R78x2
D17x2 CM19
RM70
CM25x2 CM05x2 CM45x2 CM47x2 CM22x2 CM04x2
FBM03 FBM04CM16 CM17CM19

RM68x2 RM68x1 RM65x2 RM65x1 UM04x4 UM04x5 CN33x38
R78 R112 R78

CM45
CM47
CM22
CM04
CN8x8
RM66 RM65
RM6x5 RM6x6
R148
L3 UM22 UM04
R295 CN33x37
CN8x7 CM25x1 CM05x1 CM45x1 CM47x1 CM22x1 CM04x1 RM84
RM6x7 RM6x8 CN33x36
CM05
CM47
CM22
CM04
Q14
Q15
CN8x6
U6x4 RM23x2 RM23x1
R263R219
R220 R221
R209R212
Q12
R110 CN33x35
CN8x5 R20 R104
UM04
Q14
CN33x34
D14 Q12
CN8x4 RM5x1 RM5x2
Q14x3 Q15x3 Q12x3 FB2x1 RM20 RM82
R152 C34x1 C34x2 C34 R295x2 R295x1 RM22x2 RM22x1 CN33x33
CN8x3 RM5x3 RM5x4
C24 CN33x32
CM25CM25
CM45CM05
CN8x2 RM5x5 RM5x6
R218x2 R211x2 RM83
RM70
RM62 CN33x31
R110x1 R110x2 R104x1 R104x2 C211x1 C211x2
R24
CN8x1
RM5x7 RM5x8
R151 C35x1 C35x2 C35 FB2x2 CM29 CN33x30
C35
R218x1 R211x1
FB2 FB2
D17x1
R150 R149 RM6RM5

RM21x2 RM21x1 RM20x1 RM20x2
R218
R211
CN33x29
R24x2 R24x1 R20x2 R20x1 C24x1 C24x2 R21x1 R21x2 UM01x129 CM13 CN33x28
CN33x27
R150 C9x1 C9x2
C9 C10
C37x1 C37x2 C37C38 U4 R19x2 R19x1
C13x1 C13x2 RM19x2 RM19x1 RM62x1 RM62x2
FOR_UM01x2 UM01x28 UM01x27 UM01x26 UM01x25 UM01x24 UM01x23 UM01x2 UM01x2 UM01x2 UM01x9 UM01x8 UM01x7 UM01x6 UM01x5 UM01x4 UM01x3 UM01x2 UM01x UM01x UM01x9 UM01x8 UM01x7 UM01x6 UM01x5 UM01x4 UM01x3 CM06 CN33x26
CN33x25
R149 R15x2 UM01x1 UM01x102
C10x2 C10x1 CN33x24
RM24x2 RM24x1
R218
U4x1 U4x8 R103x2 R103x1 UM01x2 UM01x101
D15 Q13 Q15 C9 C10

RM60 CN33x23
R211
CN8x23 CN8x21 C38x2 C38x1 R15x1 CM29x1 CM29x2
RM6 C18x2 C14x2 C14x1 R14x1 R14x2 UM01x3 UM01x100
CN33x22
R15
U4x2 U4x7
C38
D1 D17C13C14
R14
C19x2 C20x1 RM61x2 RM61x1 RM60x1 RM60x2 UM01x4 UM01x99
CN33x21
U4x3 U4x6 R18x1 R18x2
RM80 RM81 RM67 RM68 RM23 RM22 RM21 RM19 RM24 RM61
RM20 RM62 RM60
UM01x5 UM01x98
CM13x1 CM13x2
Q20 R295 C211R104R21C24R19R103R18

RM5 U1x3 U1x2 U1x1 C20x2 U4x4 U4x5
RM80 CM26x2 CM26x1 UM01x6 UM01x97
CN33x20
CM26
CN33x19
R110 R20 C20

U4
C18x1 UM01x7 UM01x96 CM06x1 CM06x2
CM26 CN33x18
U7x3 U7x2 U7x1 U3x3 U3x2 U3x1
CM29CM13CM06
Q10x2 C19x1 UM01x8 UM01x95
R24 C18
C17 RM81 CN33x17
R15R14
C19
C17x2 C17x1 R16x1 R16x2 UM01x9 UM01x94
Q10x3 CN33x16
C17
R16
UM01x10 UM01x93
RM67 CN33x15
UM01x11 UM01x92
CN33x14
CN6
Q10x1 UM01x12 UM01x91
CN33x13
RM68 UM01x13 UM01x90
CN33x12
R131x1 R131x2 R135x1 R135x2 UM01x14 UM01x89
R90R94
C20C18 R88
R131R132 CN33x11
R75
R135R159
R16
UM01x15 UM01x88
R91C112
CN33x10
Q10
CN6x22 CN6x20 R132x2 R132x1 R159x2 R159x1
RM23 UM01x16 UM01x87
CM18
L2x2 CN33x9
R154 UM01x17 UM01x86
CM20 CN33x8
C109x1 C109x2 C109 RM22 UM01x18 UM01x85
CN33x7
U1
R154x2 R154x1 U1x4
C19 R64R72
CN6x19 CM08x2 CM08x1 UM01x19 UM01x84
CN33x6
CN6x18 UM01x20 UM01x83 CM18x1 CM18x2
U6C34 C37 U7
U3
RM21 CN33x5
CN6x17
U7x4 U3x4 UM01x21
UM01x131 UM01x82
U1 C59 R53
R134x1 R134x2 R137x1 R137x2 C111x1 C111x2 C111 CM27x2 CM27x1 CN33x4
CN33
CN6x16
R134 R137 UM01x22 UM01x81
CM08CM27
C13 CM08 CM20x1 CM20x2 CN33x3
CM18CM20
CN6x15 C59x1 C60x1 RM19 UM01x23 UM01x80
R133x1 R133x2 R136x1 R136x2 C84x2 C39x1 CN33x2
CN6x14 R268x2 UM01x24 UM01x79
R135R159 R137R136
R133 R136 D5x2 CM27
UM01x132 CN33x1
CN6x13 C59x2 C60x2 L2x1 C14 UM01x25 UM01x78
CN6x12 R268x1 RM24 UM01x26 UM01x77
L2
D5x3
U7 C60 R54 C39

R268
CN6x11 RM3x1 RM3x2 C84x1 C39x2 UM01x27 UM01x76
C39
R74
D5
CN6x10 RM3x3 RM3x4 R53x1 R54x1 D5x1 UM01x28 UM01x75
U3
RM61
C84
CN6x9 RM3x5 RM3x6 UM01x29 UM01x74
CN6x8 R53x2 R54x2 C67 UM01x30 UM01x73
R268
RM3x7 RM3x8
C84
C59 R53
C60 R54
CN6x7 Q8x2 UM01x31 UM01x72
C21 C21x1 C21x2 C67x2 C67x1 CN33x52
C40x2 C87x2 C88x2 R77x1
C98
CN6x6 R74x2 UM01x32 UM01x71 CM02
CN6x5 RM2x1 RM2x2
Q8x3 C62 UM01x33 UM01x70
CN6x4 C40x1 C87x1 C88x1 R74x1 R77x2 UM01x34 UM01x69
RM2x3 RM2x4
C87
C88
R77 R77
CN6x3 RM2x5 RM2x6 C11x1 C98x1 Q8x1 C22 C16 CM03 UM01x35 UM01x68 CM02x1 CM02x2
UM01
C109C111D5 Q8
C12x2 C62x2 C62x1 C16x2 C16x1
CM02
CN6x2
C22x2 C22x1 UM01x36 UM01x67
C11C12
RM2x7 RM2x8
L2 C21C67C22
RM3 RM2
CN6x1
C12x1 FB5x1 FB6x1 R91x1 R94x2 R90x2 R88x1 C23 CM28 UM01x37 UM01x66
CN35x42
C85x1 C89x1 C86x1 UM01x38 UM01x65
C12
C11x2 C15
C85
C89
C86
FB5
FB6
C98x2 R91x2 R94x1 C23x1 C63x1 C63x2 C15x2 C15x1
C11
R90x1 R88x2
C40
C87
C40 C88
C64C23x2
C16 C15
C85x2 C89x2 C86x2 FB5x2 FB6x2
C85
C89
C86
C63 CN35x41
FB5
R74 FB6
C112x1 R75x1 R72x2 C64x2 C64x1 C65x1 C65x2 CM03x2 CM03x1
R64x1
C62 C23C64
C90 UM01x130 CN35x40
C100x1
C101x1 C99x1 C90x2 C90x1 C76x1 C76x2 C65C66
FOR_UM01x1 CN35x39
C90
C112x2 R75x2 R72x1 R64x2 C66x1 C66x2 CM28x2 CM28x1
UM01x39 UM01x4 UM01x4 UM01x42 UM01x43 UM01x4 UM01x45 UM01x46 UM01x47 UM01x48 UM01x49 UM01x5 UM01x5 UM01x52 UM01x53 UM01x54 UM01x5 UM01x56 UM01x57 UM01x58 UM01x59 UM01x6 UM01x6 UM01x62 UM01x63 UM01x64 CM12x1 CN35x38
R91 C112
R94 R75
R90 R72
C69
Q8 R88 R64
CM03CM28
C76
CN18 CN15 CN8 CN6

CN35x37
CN6x23 CN6x21 C119x1
CM12
C100x2 C101x2 C99x2
C99
CM12x2
C100
C119x2 FB7x1 FB7x2 C69x2 C69x1 C70x1 C70x2 CN35x36
CM12
C98C101
C70 C77
C69
C63 C65 C66 C70
C77x2 C77x1
Q10R131R132R154 R134R133 RM3RM2 C119

C100
C101
C75 CN35x35
C76C77
C97x2 C96x2 C103x2 C103x1
C75x1 C75x2 CN35x34
R157x1 CM11x2 CN35x33

CM51x1 RM09x2 CM07x1 CM43x1 CM23x2 CM09x1 CM31x1 FBM01x2
FOR_UM01
C97x1 C96x1 R119x2 R121x2 C232x1 CM30x1 CN35x32
C102x2 C102x1 CM52x2
C99 C96
C97
FB7C103C102
R157x2 C92x2 C92x1 CN35x31
CM51x2 RM09x1 R119x1 R121x1 C232x2 CM07x2 CM43x2 CM23x1 CM09x2 CM31x2 CM30x2
R157
RM09
CN35x30
CM43
CM51
CM07
CM23
CM09
CM31
CM52x1
R119
R121
FBM01x1
C119 R157
CM11x1 CN35x29
FBM01
C91x2 C91x1
CM52
FB7 C103
R283
C75 C92C91
CN35x28
CM11
R175
R95 D16x3 Q24x3 CN35x27
CM46x1 CM42x2 FBM02x2
C96
C97
R36 C102 C92 R117x1 C228x2 CM49x2 CM50x2 CN35x26
C83
C91 R62x2 CM46x2 CN35x25
C78
C79
R181 D10 R117x2 CM49x1 CM50x1 CN35x24
R118
CM46
CM52 R117
R71 CM42x1 FBM02x1
CM49
CM50
C228x1 CN35x23
FBM02
D16
CM42
R62x1 D16x1
Q24
D16x2 Q24x1 Q24x2
C232 C228
R182
R62
C83x2 R224x1 R283x1 CN35x22
R177 RM69x1 RM69x2
CN35x21
RM69
R174 FORU9x2 R71x2 R71x1 C83x1 R224x2 R283x2
C222x1 R116x1 D16 Q24 XM01 RM69 CN35x20
R71
C83
R224 C80 R224
R283
CN35x19
R35 R176
R178 R116x2
R116
CN35x18
R62
CM49
CM50
C82x2 C81x2
C222x2 CN35x17
C222
CM51 R117 R116
C222
CN12x17 D9 CN35x16
R34C42
CM11
R178x2 R178x1 C82x1 C81x1 CN35x15
R38
CN35x14
CM30 CM30 FBM01

C68 C80x1 C78x1 C79x1 R118x1
RM06x1 RM05x1 XM01x2 XM01x1 CN35x13
D11x2 D11x1 R36x1 R36x2 C44 C68x2 C68x1
FOR_U9x1 CN35x12
R178D11
R60 RM06x2 RM05x2
C68
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C82C80
C81C78
C79
R118
D10x1 D10x2 C43 R114x1 R114x2 R60x2 R60x1 CN35x10
R58 CN35x9
CN12
C82
C81
FOR_UM01
CN12x5
R177x1 R177x2 R33 R120x1 R120x2 R58x2 R58x1
CN31x1 CN31x2 CN31x3 CN31x4 CN31x5 CN35x8
R114 R120
U9xA2 U9xA3 U9xA4 U9xA6 U9xA7 U9xA9 U9xA10 U9xA12 U9xA13 U9xA14 U9xA15 U9xA16 U9xA17 U9xA18 U9xA19 U9xA20 CN35x7
CN35
CN12x15 R35x1 R35x2 C44x1 C44x2 CN35x6
U9xB1 U9xB2 U9xB3 U9xB4 U9xB5 U9xB6 U9xB7 U9xB8 U9xB9 U9xB10 U9xB11 U9xB12 U9xB13 U9xB14 U9xB15 U9xB16 U9xB17 U9xB18 U9xB19 U9xB20 U9xB21
CN35x5
CN12x10 U9xC1 U9xC2 U9xC3 U9xC4 U9xC5 U9xC6 U9xC7 U9xC8 U9xC9 U9xC10 U9xC11 U9xC12 U9xC13 U9xC14 U9xC15 U9xC18 U9xC19 U9xC20 U9xC21
R114 CN35x4
RM06 RM06
R176x2 R176x1 C43x1 C43x2 RM29x8 RM29x7
CN35x3
RM05 RM05
CN12x4
CN31
U9xD1 U9xD2 U9xD3 U9xD4 U9xD6 U9xD7 U9xD9 U9xD10 U9xD11 U9xD12 U9xD15 U9xD18 U9xD19 U9xD20 U9xD21 RM29x6 RM29x5 RM16x8 RM16x7
CM43
CM31
R120 RM29x4 RM29x3 RM16x6 RM16x5
CN35x2
CN12x14 D9x2 D9x1 R33x1 R33x2 C41x1 C41x2 CN35x1
C41 U9xE2 U9xE3 U9xE4 U9xE5 U9xE6 U9xE7 U9xE8 U9xE9 U9xE10 U9xE11 U9xE12 U9xE14 U9xE15 U9xE18 U9xE19 U9xE20 RM16x4 RM16x3
CN31x7 CN31x6
C44 C43R33
C41
RM29x2 RM29x1
R36D10R177R35R176D9
CN12x9 RM16x2 RM16x1
U9xF1 U9xF2 U9xF3 U9xF4 U9xF5 U9xF6 U9xF7 U9xF8 U9xF9 U9xF10 U9xF11 U9xF12 U9xF13 U9xF15 U9xF18 U9xF19 U9xF20 U9xF21
CN31
CN12x3 R305
U9xG1 U9xG2 U9xG3 U9xG4 U9xG5 U9xG6 U9xG7 U9xG8 U9xG9 U9xG10 U9xG11 U9xG12 U9xG15 U9xG18 U9xG19 U9xG20 U9xG21
R119
C232R121
CN12x13 RM15x8 RM15x7
RM09
CM09CM23
U9xH2 U9xH3 U9xH4 U9xH5 U9xH6 U9xH7 U9xH8 U9xH9 U9xH10 U9xH11 U9xH18 U9xH19 U9xH20
CN3
CN12x8
CN3x6 U9xJ1 U9xJ2 U9xJ3 U9xJ4 U9xJ6 U9xJ8 U9xJ9 U9xJ10 U9xJ11 U9xJ12 U9xJ16 U9xJ17 U9xJ18 U9xJ19 U9xJ20 U9xJ21 RM26x6 RM26x5
RM15x4 RM15x3 R293
R307R292 CN35x43
CN12x2 C42x2 R34x1 RM26x4 RM26x3
CN5 CN33CN35
U9xK1 U9xK2 U9xK3 U9xK4 U9xK5 U9xK8 U9xK9 U9xK12 U9xK15 U9xK16 U9xK17 U9xK18 U9xK19 U9xK20 U9xK21 RM15x2 RM15x1
RM26x2 RM26x1
C48 R41C45 R40

CN12x12
C46 C49 R39 C47 R37

C42x1 R34x2 R298 R297
RM29 RM26
C42
R34
U9xL2 U9xL3 U9xL4 U9xL5 U9xL6 U9xL7 U9xL8 U9xL9 U9xL10 U9xL11 U9xL12 U9xL13 U9xL14 U9xL15 U9xL16 U9xL17 U9xL18 U9xL19 U9xL20
CN12x7
CM07 CM46C228
CN3x1 R307x1 R307x2 R305x2 R305x1
U9xM1 U9xM2 U9xM4 U9xM6 U9xM8 U9xM9 U9xM10 U9xM11 U9xM12 U9xM13 U9xM14 U9xM15 U9xM16 U9xM17 U9xM18 U9xM19 U9xM20 U9xM21 RM18x8 RM18x7 R49
CM42
CN12x1
RM18x6 RM18x5
CN12x11 U9xN1 U9xN2 U9xN3 U9xN4 U9xN6 U9xN8 U9xN9 U9xN10 U9xN11 U9xN12 U9xN13 U9xN14 U9xN15 U9xN16 U9xN17 U9xN18 U9xN19 U9xN20 U9xN21 R298x2 R298x1 R292x2 R292x1 R293x1 R293x2
RM18x4 RM18x3
R298
R307 R292
R316R49x2 R49x1
FBM02
CN12x6 C50x2 C51x2 U9xP2 U9xP3 U9xP5 U9xP9 U9xP10 U9xP11 U9xP12 U9xP13 U9xP14 U9xP15 U9xP16 U9xP17 U9xP19 U9xP20 RM18x2 RM18x1
R287
R38x1 C46x2 FB4x2 C74x1 C73x1
RM16 RM15 RM18

R51 R316x2 R316x1 R297x1 R297x2 R287x2 R287x1
RM16 RM15 RM18

U9xR1 U9xR2 U9xR3 U9xR5 U9xR6 U9xR7 U9xR8 U9xR9 U9xR10 U9xR11 U9xR12 U9xR13 U9xR14 U9xR15 U9xR16 U9xR17 U9xR18 U9xR19 U9xR20 U9xR21
C50 R42
C51 R44
CN3x2 R302
R305 R293 R297

C50x1 C51x1 RM14x8 RM14x7
R38x2 C46x1 C73x2 RM17x8 RM17x7
C73
RM14x6 RM14x5
U9xT1 U9xT2 U9xT3 U9xT4 U9xT5 U9xT6 U9xT7 U9xT8 U9xT9 U9xT10 U9xT11 U9xT12 U9xT13 U9xT14 U9xT15 U9xT16 U9xT17 U9xT18 U9xT19 U9xT20 U9xT21
C73
R175x1 R93x2 FB4x1 C74x2 RM17x6 RM17x5
R308x1 R308x2 R301 R51x1 R51x2 R301x1 R301x2 R302x2 R302x1
R42x2 R44x2 RM14x4 RM14x3
R308R304 R310R50 R288
C74
FB4
RM17x4 RM17x3
U9xU2 U9xU3 U9xU4 U9xU5 U9xU6 U9xU7 U9xU8 U9xU9 U9xU10 U9xU11 U9xU12 U9xU13 U9xU14 U9xU15 U9xU16 U9xU17 U9xU18 U9xU19 U9xU20 RM14x2 RM14x1
R296
R175x2 R93x1 C48x2 C49x2 RM17x2 RM17x1 R304x2 R304x1 R310x2 R310x1 R288x2 R288x1
R42x1 R44x1 U9xV1 U9xV2 U9xV3 U9xV4 U9xV5 U9xV6 U9xV7 U9xV8 U9xV10 U9xV12 U9xV13 U9xV15 U9xV16 U9xV18 U9xV19 U9xV20 U9xV21
R287R302 R288
R299
C50R42
C51R44
CN3x3
C74FB4
RM17
C48x1 C49x1 U9xW1 U9xW2 U9xW3 U9xW4 U9xW5 U9xW6 U9xW7 U9xW8 U9xW9 U9xW10 U9xW11 U9xW12 U9xW13 U9xW14 U9xW15 U9xW16 U9xW17 U9xW18 U9xW19 U9xW20 U9xW21 RM11x8 RM11x7
R95x2 R180x2 R168x1 R168x2 R296x2 R296x1
RM11x6 RM11x5
R299x2 R299x1 R300 R50x2 R50x1 R300x1 R300x2
R168
R51 R50
R49 R316 R301 R310 R300
R296
U9xY1 U9xY2 U9xY3 U9xY4 U9xY5 U9xY6 U9xY7 U9xY8 U9xY9 U9xY10 U9xY11 U9xY12 U9xY13 U9xY14 U9xY15 U9xY16 U9xY17 U9xY18 U9xY19 U9xY20 U9xY21 RM11x4 RM11x3
R95x1 R180x1 R41x2 R39x2
U9xAA2 U9xAA3 U9xAA4 U9xAA6 U9xAA7 U9xAA9 U9xAA10 U9xAA12 U9xAA13 U9xAA15 U9xAA16 U9xAA18 U9xAA19 U9xAA20 RM11x2 RM11x1 R289 R289x1 R289x2 CN32x32
R308 R304 R299 R289

R284x1
CN3x4 R168 RM27x8 RM27x7
CN34x53
RM14 RM11
R181x2 R179x2 R41x1 R39x1
RM27x6 RM27x5
R93 RM27x4 RM27x3
R284x2
R181x1 R179x1 C45x2 C47x2 CN34x51
RM27x2 RM27x1
R180 RM28x8 RM28x7
CN17x41 CN34x50
R60R58 RM29 RM26 RM17 RM27

RM27
C45x1 RM12x8 RM12x7 CN32x30
CN3x5 C47x1 RM28x6 RM28x5 CN34x49
R182x2 R92x2 RM12x6 RM12x5 CN17x44
R179 RM28x4 RM28x3 CN34x48
RM12x4 RM12x3 CN32x29
R40x2 R37x2 RM28x2 RM28x1 CN34x47
R182x1 R92x1 RM12x2 RM12x1 CN17x39 CN17x40
RM28
CN12x16
R284 R284
RM28
R92R96 CN34x46 CN32x28
R40x1 R37x1 CN34x45
R38 C48R41C45R40
C46 C49R39C47R37
R174x2 R96x1 FOR_U9x2 RM13x8 RM13x7 CN17x37 CN17x38 CN34x44 CN32x27
R174x1 R96x2 CN3x7 CN34x42
R175 R95 R181 R182R174

R93 R180 R179 R92R96
CN17x35 CN17x36
CN3
CN34x41
RM13x2 RM13x1
C54 CN34x40 CN32x25
RM14RM11 RM12RM13
RM12 RM13
R183x1 R183x2 CN17x33 CN17x34 CN34x39
CN20x4 CN20x3 C54x2 C54x1 C93x1 C94x1 C61 R56 R99 C116 CN34x38 CN32x24
R164x1 R43x1 CN34x37
R186x1 R186x2 CN17x32 CN34x36
U9
C55 C93x2 C94x2
FORU9x1 R311R86 C115CN17x31 CN32x23
R43
R164x2 R43x2 CN34x35
R164
R43
R184x1 R184x2 CN17x29 CN17x30 CN34x34
R164
C55x2 C55x1 C229 CN32x22
CN34x33
R306R98
C54C55
C182 R66x1 R69x1
R185x1 R185x2 CN34x32 CN32x21
CN17x28
R183R186R184 R185
C230 CN34x31
C94 C94
R66x2 R69x2
R97 C114CN17x27
CN17
C93 C93
R66
R69
C58 R55 R87 CN34x30
R66
CN32x20
FORU9
R183 L8L9 CN17x25 CN17x26 CN34x29
C183 C95x2 C108 CN34x28 CN32x19

CN34x27
CN20x1 R186 C186
CN10x1 CN10x2 C95x1 CN17x23 CN17x24 CN34x26
R89 C110 CN32x18
CN20x5 CN20x2 R184 L13 CN29 RM9x7 RM9x5 RM9x3 RM9x1 RM10x7 RM10x5 RM10x3 RM10x1 CN34x25
C108x2 C108x1 R89x1 R89x2 C110x1 C110x2 CN17x21 CN17x22 CN34x24 CN32x17
C108
R89
C110
RM9x8 RM9x6 RM9x4 RM9x2 RM10x8 RM10x6 RM10x4 RM10x2 CN34x23
R252
C197
C198
CN10
CN34x22
R185 C196
RM9
RM10
L12
CN10 CN17x19 CN17x20 CN34x21
CN32x16
R69 C95 C95

CN20 CN30 CN17x17 CN17x18
CN34x20
CN34x19
CN32x15
CN34x18 CN32x14
CN34x17
CN17x15 CN17x16 CN34x16
RM9
H12x3 H12x2 H12x1 X1x2 X1x1 CN32x13
RM10
CN34x15
RM7
RM8
R250x2 C195x2
U9
R225
CN17x13 CN17x14 CN34x14 CN32x12

R250x1 C195x1 CN34x13
H12
C196x2 C196x1
X1
C195
R250
CN34x12 CN32x11
CN30x3
CN29x4 C199x2
CN17x11 CN17x12 CN34x11
R241 RM7x7 RM7x5 RM7x3 RM7x1 CN34x10 CN32x10

C199
R251x2 C200x2 CN17x9 CN17x10 CN34x9
C210
CN32
C195
RM7x8 RM7x6 RM7x4 RM7x2 C199x1 CN34x8 CN32x9
R8
R241x1 R241x2 RM8x8 RM8x6 RM8x4 RM8x2 R251x1 C200x1 CN34x7
RM7
C199
R17 C5
R251
R241
CN17x7 CN17x8
C196 RM8
C200
C201x1 C201x2
R122U2
CN34x6
R9 C8
R303x1 CN32x8
C201
R251
C200
X3x2 X3x1 CN34x5
C1
CN17x5 CN17x6 R303x2 CN34x4 CN32x7
CN34 R303
CN34x3
L52x1 L52x2 C187x1
R303
U18x24 U18x23 U18x2 U18x21 U18x20 U18x 9 U18x U18x 7 U18x 6 U18x 5 U18x 4 U18x 3 U18x 2 U18x 1 U18x 0 U18x9 U18x U18x7 U18x6 U18x5 U18x4 U18x3 U18x2 U18x1 CN34x2 CN32x6
L52
CN17x3 CN17x4
X3
C181 CN34x1
R12 R10 R11 R13
C187x2
R250
C187 C187
CN30x1 C181x1 C176x1 FB16x1 C177x1 C174x1 C166x2 C173x2 X3 CN32x5
CN29x1 C182x2 C182x1
Q16x2 CN17x1 CN17x2
C125x1
L52
CN2309x23 C181x2
CN2CN309x45
C201
L11x2 C176x2 FB16x2 C177x2 C174x2 C166x1 C173x1 R238x2 CN32x4
C181
Q16x3
C176
FB16
C177
C174
C166
C173
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R242 L8x1 L8x2 CN17x43 C125x2
C125
C178x1 Q16x1 CN32x3
R238
R242x2 R242x1 C180
R242
R238x1
C125
U17x22 U17x21 U17x20 U17x19 U17x18 U17x17 U17x16 U17x15
C178
R243x1 L11x1
C185
L9x2 L9x1
R238
U17x23 U17x14 C178x2 R239
CN34x52 CN32x2
C178
U17x24 U17x13
CN22x2 CN22x1
C52
R243x2
R45
UM01 XM01 CN17
C184x2 C185x2 C185x1 C183x2 C183x1
CN30x6 U17x25 U17x12
C180x1 C180x2 CN17x42 CN32x1
L11 C184 C185

CN29x10 R240
Q16C180
U17x26 U17x11
C168 R239x1 R239x2
U16x9 U16x8 U16x7 R244x1 C184x1 C186x2 C186x1 U17x27 U17x10 C168x2 C168x1
U17x28 U17x9
C172x1 C172x2
U16x10
U16x11
U16x6
U16x5 R244x2 C213x1 C213x2 L13x2 L13x1 U17x1

U17x29 C179 R240x1 R240x2
CN22x4 CN22x3
U10
R243 R244
C179x2 C179x1
R243 R244
L11C184 C213
U17x2 U17x3 U17x4 U17x5 U17x6 U17x7 U17x8 C53x1
C168C179
U16x12 U16x13 U16x4
C167x2 C167x1 L12x1 L12x2 C189x1 C189x2 R46x1 C61x2 C61x1 R56x2 R56x1 R99x2 R99x1 C116x2 C116x1 U10x5 U10x4
C172
C172C167
C53x2
C182L8L9C183C186L13L12
U16x1 U16x2 U16x3 L10x1 L10x2 C169x2 C169x1 C52x2 CN32x31
R48
C190x2 C190x1 R248x2 R248x1
L10
C169
R260x1 R259x1 R258x1 R257x1
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CN32
C188x2 C188x1 R46x2 C52x1
CN22x6 CN22x5 C229x1 C229x2 R311x2 R311x1 R86x2 R86x1 C115x2 C115x1 U10x6 U10x3
R46 R46
R47x2
C189C188
U16
R247x2 R247x1 R260x2 R259x2 R258x2 R257x2
R239R240 R248R247
R260 R260
R259 R259
R258 R258
R257 R257
R248
R47x1 R45x1 C230x1 C230x2 R306x2 R306x1 R98x2 R98x1 R97x1 R97x2 U10x7 U10x2
CN30x5
CN29x11 C213
C189C188
R247 R45x2 CN22x8 CN22x7 C58x2 C58x1 R55x2 R55x1 R87x2 R87x1 C114x2 C114x1 U10x8 U10x1
R237x2 R246x2
FORU9 FOR_U9 CN22
C167
R48x2
L10 R252x1 C197x1 C198x1
R237x1 R246x1
CN34 U10
U19
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C190
C169
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CN29x9 CN22x10 CN22x9 R252x2
C197x2 C198x2 C203 C231
C197
Q21
R109x1 R106x1
FB29 LM3R12x1 C210x2 R122x2 R17x2 R225x2 FB1x1
C53 R47 C53C191

C175x1
C193
C193x1 C191x2
U18
C194x1 FB17x2 C192x1 Q21x1 U11x1 U19x4 U19x3
C202
R12x2 C210x1 R122x1 R17x1 R225x1
U16
C175 R109x2 R106x2 R269x1
R99 R86 R98 R87 R12
R122
R17
C116 C115 R97 C114 R225
C242 FB1x2
U17R246 R106
C175x2
R109
R106
C194x2 C192x2 Q21x3 U11x2 C203x2 C203x1 C231x2 C231x1 U19x5 U19x2
C231
R269x2
R237
R246
C242x2 C242x1 R8x2
C194
C192
FB29x2 LM3x2
C203
FB17x1 C241x1 R9x1 R10x1

R269
R107x2
R47
U11
C193x2 C191x1 Q21x2 U11x3 C202x1
FB17
U19x6 U19x1
R269
Q21
C194 Q37
Q36
R8x1
C193
R245x1 R9x2 R10x2
C192FB17
R107x1 U2x8 U2x7 U2x6 U2x5
U19
R245 C214x2 R105x2

FB25x1 FB27x2 FB29x1 LM3x1
C241x2 C202x2
U18
C241
Q37x2 Q37x1 Q36x3 Q36x1 U18x25 U18x26 U18x27 U18x2 U18x29 U18x30 U18x31 U18x32 U18x3 U18x34 U18x35 U18x36 U18x37 U18x3 U18x39 U18x40 U18x41 U18x42 U18x43 U18x4 U18x45 U18x46 U18x47 U18x4 C8x1 R11x1 C5x1
C202
R245x2
CN29x8 CN29x2 CN29x6 R102 C4x2 C3x1
C175 R245
C217x2 R108x2 R100x2 C215x1 C214x1 R105x1 FB20x1 FB20x2
C191 R105
FB25x2 FB27x1 C8x2 R11x2 C5x2
R8 C5
FB27
CM77x2 CM71x1
R56 R311 R306 R55 C198 R9 C8
C217x1 R108x1 R100x1 C215x2

U2x1 U2x2 U2x3 U2x4
R107
TN1x8 TN1x7 TN1x6 TN1x5 TN1x4 TN1x3 TN1x2 TN1x1
FOR_U9 X1CN22
R102x1 R102x2
C214
R105
C217
R108
R100
R237 R109 R107 C215
Q37
Q36
C214 R102
C3C4
Q37x3 Q36x2 R13x1 C1x2 C1x1 C4x1 C3x2

C210 U2
R57x2 R59x2
C1
FB1 C4
FB1 C3
Q803x2 CM77x1 CM71x2 FB23x1 FB23x2

R13x2
C176
FB16
R10 R11 R13
R57x1 R59x1
C177
C174
FB29 CM77
C61 C229 C230 C58 R252 LM3CM71
Q803x3 R281x2 C113
CN12 CN20 CN29

C242 FB25 FB27
CN29x7 R823x2 C71x2 C72x2 Q803x1 R281x1 FB11x1 FB12x1 FB20
C217
R108
C215R100
R823x1 C71x1 C72x1 CM70x2 CM63x2 RM52x2 RM53x2
CM66
RM40 L1x2 FB23
R57C71
R59C72
R101
R823
R814x1 CM6x2 RM38x1 CM62x2 FB11x2 FB12x2
U25
C166
C173
U11 FB20FB23FB11
FB12
CM66x2 CM70x1 CM63x1 RM52x1 RM53x1
H12
CM71 CM77
TN1
H12x6 H12x5 H12x4 R819x1 CM64
CM62
CM70
CM63
RM52
RM53
CM70
CM63
RM52
RM53
Q25 R814x2 CM6x1 RM38x2 CM62x1

L1
F2
R282x1
C241 Q803 RM38

CM62
Q803
C218x2 R101x2 CM66x1 CM73RM39
C1 3x2
R281 R281
R819x2
R819
CN19x4 CN19x3
R819
RM38
R57 C71
R59 C72
Q18
Q25x1 R282x2 Q18x1 FB24x1 FB24x2 FB24 RM42x1
R282
C218x1 R101x1 Q808x2
FB24
X5x1 X5x4
C218
R101
Q25x3 Q18x3 CM65x1 RM42x2 U25x12 U25x1 U25x10 U25x9 U25x8 U25x7 U25x6 U25x5 U25x4 U25x3 U25x2 U25x1
FB11
FB12
Q808x3 U25x13 U25x48 RM40x1 RM40x2

F2x1 F2x2 R816x1 X5
F2
Q25x2 Q18x2 CM65x2 U25x14 U25x47
L1x1 TN1x9 TN1x10 TN1x1 TN1x12 TN1x13 TN1x14 TN1x15 TN1x16
Q25
Q18
R816x2 Q808x1 U25x15 U25x46
FB25 R814 R816

X5x2 X5x3 CM64x1 CM64x2
U25x16 U25x45
R282
X5
U25x17 U25x44
R823
R822x2 Q806x2 CM69x1 CM72x1 U25x18 U25x43
C212
U21
C144x2 R217x2
C143x2 U25x19 U25x42
CM73x1 CM73x2 R253
U14x4 U14x3 U14x2 U14x1 R822x1 Q806x3 CM69x2 CM72x2 U25x20 U25x41
CN19x1
RM42 RM42 CM72
C1 3x1
CM65CM66 CM65 CM69
C113
D8 U25x21 U25x40
C144x1 R217x1
U21x4 U21x3 U21x2 U21x1
CM72
CM69
U25x22 U25x39
C144
R217
CA34x2 CA34x1 R821x2
Q806x1 RM39x2 RM39x1 R253x2 R253x1
C218
R167 CN19x5 CN19x2 C143x1
C237 C237x1 C237x2 CM59x2 CM59x1 U25x23
U25x24
U25x49 U25x38
U25x37
C6x2 C7x1
C212x R255 R255x1 R255x2
R158R144
R821x1
C6
CM61x1 CM61x2
R814 R816 R822 R821

D7x1 R166x1 D8x1 R167x1 D6x1 R165x1 R222x1 Q807x2 C238x1 C238x2 CM68x2 CM68x1 C7x2
C7C7
D7
C237C238
C238 U25x25 U25x26 U25x27 U25x28 U25x29 U25x30 U25x31 U25x32 U25x3 U25x34 U25x35 U25x36
U14
R822
U25
D7x2 R166x2 D8x2 R167x2 D6x2 R165x2 R222x2 C138x2 R155x2 R144x2 R158x1 R162x1 R161x1 R815x2 Q807x3 RM45x1 RM45x2
CM61 C6x1 C204x1 C205x2
D6
C139x2 R210x2
R166
R167
R165
C6
D8
D6
R815x1 Q807x1 RM41x1 RM41x2
CM81x1 CM81x2 R254 R254x1 R254x2
R165
R155x1 R144x1 R158x2 R162x2 R161x2
CN19
CM6 Q808 Q806 Q807
R815
R155
C139x1 R210x1 CM7x2 CM7x1 CM67x1 CM80x1
CM59CM68RM45CM7
C139
R210
CM81 R256
U14
U14x5 U14x6 U14x7 U14x8 C138x1 R61x2 R156x1 C120x1 C123x1 R163x1
CM59
LM2x2 CM82x1
TN1 U21
U21x5 U21x6 U21x7 U21x8
CA34
C204
CM80x2
C143 C138
CN25x4 CN25x3
R222 R222R223
R61x1 CM68 CM67x2 CM82x2 CM76x2 FB28x1 CM60x2 R256x2 R256x1
R255R254R256
R156x2 C120x2 C123x2 R163x2 R187x2 R188x2 C124x2 C204x2 C205x1
R61
D7 R166
C212x1
R156 R144R156
C120 R158C120
RM41
R162 C123 R162C123

R253 C204
C205
LM2x1
CM6 Q808 Q806 Q807
R217 R210
C143 C138
C144 C139
CE10
LM2
FB28 CM76
R190
CM74x1 CM75x1 CM79x1 CM78x1 R187x1 R188x1 C124x1
R155
C124
C208x2 C209x2 C141x1 R142x2 R141x2 FB28x2

R188 R187
R188
C140x2 FB15x1 R278x2 R277x1

RM40 CM64 CM73 RM39 CM61 CM81 FB28
CM74x2 CM75x2 CM79x2 CM78x2

CM76x1 CM60x1
R821 R815
C205
RM45
CM60
CA33x2 CA33x1 CM7 C240x2 C240x1

CM76
C124
R142x1 R141x1 R190x2 R190x1 R191x1 R191x2

C240
R278x1 R277x2
L1C212C240
H4
R141
C140x1
CM60 R190
R191
R278
R61 R277
C140
R223x1
FB15x2
R187R191
RM41CM82CM82
FB15
CA33
C208x1 C209x1 C141x2 RM47x2 RM46x2 RM48x1 RM43x1
R223x2 U12x4 U12x3
CE10x2 CE10x1 CN21x8 CN21x7 CN21x6 CN21x5 CN21x4 CN21x3 CN21x CN21x
CN25x1 RM47x1 RM46x1 RM48x2 RM43x2
CM67 CM74 RM47
R276
CN25 R160x2
CA34 CA33
R276x2 C56x1 U12x2 H4x1
C208
C141C209
FB15C140
R277R278
LM2
C57x1
CN14
R142
R161 R163 R161R163 R142 R141
D20x1 R172x2 R173x1 D19x1 R170x2 R171x1 D18x1 R160x1 C122x2 R139x2 R138x2 R146x2 R145x2 R143x2 R140x2 RM4x2 RM4x4 RM4x6 RM4x8
CN30 CN19 CN25

CN25x5 CN25x2 R276x1 U12x5 U12x1 RM44x2 RM49x2 RM51x2 RM50x2
R160
C56
D18
R223 R276
U12
D20x2 R172x1 R173x2
CN27 D19x2 D18x2 C122x1 R139x1 R138x1 R146x1 R145x1 R143x1 R140x1 RM4x1 RM4x3 RM4x5 RM4x7
R171
CE10
R170x1 R171x2 RM44x1 RM49x1 RM51x1 RM50x1
C209 D20
R172
R173
C57
D19
R160
R139
R138
R146
R145
R143
R140
C122
D18
R171
C56x2
CM67 CM75 RM46 RM49
CM80 CM79 RM48 RM51
C122
R139
R138
R146
R145
R143
R140
RM4
C57x2
CN14x1 CN14x2 CN14x3 CN14x
C56
C141 C57
C208 R173D20
CN28 CN26
R170 R170D19
RM44RM4
H8x8 H8x5 H8x7 CN21x10
R172
CN7x19 CN7x18 CN7x1 CN7x16 CN7x15 CN7x14 CN7x13 CN7x12 CN7x1 CN7x10 CN7x9 CN7x8 CN7x CN7x6 CN7x5 CN7x4 CN7x3 CN7x2 CN7x1 H2x8 H2x5 H2x7
CM74
CM75
H8x4 H8x3CN28x3 CN28x2 CN27x3 CN27x2 CN26x3 CN26x2 CN7x20 CN7x21 CN14x5 CN14x6 CN21x9 H2x4 H2x3
H4 CN21
CM78 RM43
CN7
H8
H2
H8x1H8x2 H8x6 H8x9 H2x2 H2x6 H2x9

H2x1
CN28x1 CN27x1 CN26x1 CN21x1 CN21x12
H2
H8
CN7x22 CN7x23
RM47 RM44
CM80 CM78 RM43 RM50 CM79 RM48RM46 RM49
RM51
RM50
CN7
CN14
CN21
H5x1 H9x1
H9
H5
H5
H9
CN28
CN27
CN26
H1x8 H1x5 H1x7 H7x8 H7x5 H7x7
VD_RXx1 VD_TXx1 GND_CN13x1 I2CS_SCLx1 I2CS_SDAx1
LED_G
VD_RX
VD_TX
GND_CN13
I2CS_SCL
I2CS_SDA
KEY0x1 KEY1x1 +5Vx1 IRx1 GND_CN1x1 LED_Rx1 LED_Gx1
IR
GND_CN1
LED_R
H1x4 H1x3 H7x4 H7x3
KEY0
KEY1
+5V
R+x1 R-x1
H1
H7
R-
R+
H1x2 H1x6 H1x9
H1x1 H7x2 H7x6 H7x9
H7x1
L+x1 L-x1
L+
L-
CTLx1 +5V_WIFIx1 D-x1 D+x1 GND_WIFIx1
CTL
+5V_WIFI
D-
D+
GND_WIFI
VSYNCx1
VSYNC
SPDIFx1
SPDIF
CN18x1
GND_CN18x1
GND_CN18
+12Vx1
+12V
CN15x5 CSBx1
+5V_USB1x1 MISOx1
D1-x1 STANDBYx1
D1+x1 MOSIx1
GND_U1x1
+5V_USB1 D1-D1+ GND_U1

BL-ADJx1
BL-ON/OF x1
CSB MISO STANDBY MOSI BL-ADJ BL-ON/OFF

CN15x6
CN8x22 CN8x20
FOR_UM01x2
CN8x23 CN8x21
CN6x22 CN6x20
FOR_UM01x1
CN18 CN15 CN8 CN6

CN6x23 CN6x21
FOR_UM01
CN12x17 FORU9x2
FOR_U9x1 EEP-SDA1x1 EEP-SCL1x1 EEP-GNDx1 EEP-WPx1
EEP-SCL1
EEP-GND
EEP-WP
EEP-SDA1
SCLx1
VSx1
Bx1
HSx1
Gx1
SDAx1 RX2x1
Rx1
B GR
GND_VGAx1 TX2x1
SCL VS HS SDA GND_VGA

GND2x1
B0P1x1
B0P1
SCL2x1
B1P1x1 B0N1x1
SDA2x1 CN17x44
RX2TX2 GND2 SCL2 SDA2

WP_Px1
WP_P
CN12x16 FOR_U9x2 B1N1x1
B2P1x1
B2N1x1
FOR_U9
BCP1x1
B1P1 BCP1
CN20x4 CN20x3 RIx1
RI
B3P1x1
B3P1
FORU9x1 BCN1x1
GND_CN20x1 B3N1x1 BKLx1
GND_CN20
BKL
B4P1x1 MODEx1
FORU9
B4N1x1 SYNCx1
B0N1 B2P1B2N1 B3N1SYNC

B4N1
CN20x1 CN10x1 CN10x2 A0P1x1
LIx1 A0N1x1
LI
3DENx1 3DLRx1
B1N1 BCN1B4P1 3DEN
CN10
3DLR
A1P1x1
A1N1x1
H12x3 H12x2 H12x1 A2P1x1
CN30x3
CN29x4 A4P1x1 A2N1x1
ACP1x1
Y1x1 Y2x1 A4N1x1 ACN1x1
Y1
A4P1 A4N1
Y2
GND_Px1
A3N1x1 A3P1x1
A0P1 A1P1 A2P1 ACP1GND_PA3P1
CN2309x23 CN30x1
CN29x1 CN2CN309x45 CN17x43 SCLPx1
SCLP
CN22x2 CN22x1
CN17
CN30x6
CN29x10 SDAPx1
MODE A0N1 A1N1 A2N1 ACN1 A3N1 SDAP
12V_Px1
12V_P
CN22x4 CN22x3
CN22x6 CN22x5 SDA_E2Px1
SCL_E2Px1
CN30x5 WPx1 GND_E2Px1
SDA_E2P WP
GND_E2P
CN29x11 CN22x8 CN22x7 3V3x1

SCL_E2P 3V3
CN29x9 CN22x10 CN22x9
CN29x8 CN29x2 CN29x6
CN22
CN12 CN20 CN29

CN29x7
H12
H12x6 H12x5 H12x4
CN19x4 CN19x3
PRx1
PR
GND_CN19x1
CN19x1 PBx1
Yx1
GND_CN19 Y
RO_CN22x1
PB RO_CN22
RX+x1 TX+x1
TX+
CN25x4 CN25x3
RX-x1 TX-x1
RX-
RX+TX-
GND_Ax1
CN25x1 DETx1
GND_A DET
CN30 CN19 CN25

LO_CN22x1
LO_CN22
SG2x1 SG3x1 SG4x1 SG5x1 SG6x1 SG1x1
SG2
SG3
SG4
SG5
SG6
SG1
SG2x2 SG3x2 SG4x2 SG5x2 SG6x2 SG1x2 CN21x10

H8x8 H8x5 H8x7 H2x8 H2x5 H2x7
+5V_USB2
D2-
D2+
LINx1 GND_LINx1 +5V_USB2x1 D2-x1 D2+x1 GND_U2x1

GND_RINx1 RINx1 VIDEOx1 GND_VINx1
GND_U2
GND_LIN
LIN
GND_RIN
RIN
VIDEO
GND_VIN
H8x4 H8x3 CN7x20 CN7x21 CN14x5 CN14x6 CN21x9 H2x4 H2x3
H8
H2
H8x2 H8x6 H8x9

H8x1 H2x2 H2x6 H2x9
H2x1
GND
CN28x1 CN27x1 CN26x1 CN21x1 GNDx1 CN21x12

CN7x22 CN7x23
CN7
CN14
CN21
CN28
CN27
CN26
Has video but no audio
Check if the Volume set to 0

or if it is mute
NG
Upgrade the software Done
NG
Check the audio input line

Done
& the audio input circuit.
NG
Check the audio output circuit. Done
NG
Check the voltage of Mute pin beside

Done
the amplifier IC. It should not be 0V.
=0V >0V
Check the mute circuit Change the

if it is OK. Main IC for U100 and the
CRYSTAL for Y100
OK
NG
Fix the mute circuit
Done
Has video but no color
Check the Color / Saturation

in picture menu if it is normal
OK NG
Check the cable input if

Increase the item
it has exactly connected
to default 50
NG OK
Done
Change the sound system of

Well connect the cable
TV source
NG
NG
Done
Done
Check the DC power
supply of the tuner
NG OK
Change 3.3V power Change the

supply IC Main IC and the CRYSTAL
NG
NG
Change the
Done
Mainboard
Done
Done
Has audio but no video
Upgrade the software
NG
Check if the backlight is on Done
NG OK
Check if the connector of Check if the LVDS line

backlight inverter is connected is connected
NG OK NG OK
Safely connect the Check the BL-ON/OFF voltage on Safely connect the Make sure the LVDS
inverter line CN2,should be High LVDS line power is ok
NG NG OK
NG OK
Check the voltage of Done Correct the Change the
Done
inverter line is ok Check the BL-ADJUST power Main IC
Check Q28 voltage on CN2,should OK
NG OK be High
OK
NG Done
Change the OK NG
LED driver board Change the Change the
Q28 Done
Change mainboard
Check R126
the panel
Done
OK
Done Done
NG
Done
Change the
R126
Done

CDH Le49smart06

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CDH Le49smart06

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SERVICE MENAUAL

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Supply voltage +2.8 +6.5 +4.5 +5.5 +4.0 +5.5 V

Absolute maximum ratings(Ta=25C)

Operating conditions (Ta=25C)

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Electrical characteristics (Unless otherwise noted, Ta=25C,VCC=5V,RL=32 ,f=1kHz,BW=400 30kHz

Quiescent current IQ 7 3.7 6.5 mA VIN=0Vrms

Mute pin control voltage H VTMH 1.6< V Mute OFF

Mute pin control voltage L VTML <0.3 V Mute ON

Channel separation CS -90 -87 -90 dB Rg=0

Mute attenuation ATT -80 dB Rg=0

Ripple rejection RR -57 dB fRR=100Hz,VRR=-20dBV

Input resistance Rin 180 90 k -

BH3541F/BH3544F BH3541F/BH3544F BH3541F/BH3544F

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Reference data (Continued)

BH3541F/BH3544F BH3541F/BH3544F BH3541F/BH3544F

BH3541F/BH3544F BH3541F/BH3544F BH3541F/BH3544F

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OU T1 MUTE IN1 GND

( ) are BH3544F, BH3547F, BH3548F values.

( ) are BH3544F, BH3547F, BH3548F values.

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Terminal Equivalent Circuit / Description

Pin Pin Equivalent circuit

0.1V Mute control pin

VCC VCC Bias pin

4 GND I - - - GND pin

8 VCC I - - - Power supply pin

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Description of external components.

Notes for use

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1)BH3541F/ BH3544F/ BH3548F