1984 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO.
5, MAY 2016
A Low-Jitter Fast-Locked All-Digital Phase-Locked
Loop With Phase–Frequency-Error Compensation
Yung-Hsiang Ho and Chia-Yu Yao, Member, IEEE
Abstract— The previous fast-locked all-digital phase-locked
loop (ADPLL) usually suffers from large timing jitter due to
the steep frequency transfer curve of its digitally controlled
oscillator (DCO). This paper presents an ADPLL that possesses
a coarse frequency selection function. All DCO frequency
transfer curves of the ADPLL have gentle slopes. The ADPLL
selects one transfer curve before acquisition. To fulfill the
fast-acquisition requirement, the proposed ADPLL employs
the phase–frequency-error compensation technique. In the
acquisition mode, the phase-error compensator resolves the
problem of phase-error accumulation. Meanwhile, the frequency-
error compensator predicts a proper control code by calculating
the cycle time difference between the reference clock and the
derived signal fed back from the DCO. Therefore, the proposed
ADPLL can compensate for the phase and the frequency errors
simultaneously. The experimental results show that the proposed
ADPLL possesses a fine-tuning acquisition within 5 reference
clock cycles. After acquisition, the code updates in a fractional
manner in the tracking mode to enhance the tracking jitter
performance. The ADPLL output frequency ranges from
860 MHz to 1 GHz. The measured rms jitter is 1.31 ps at
1-GHz frequency.
Index Terms— All-digital phase-locked loop (ADPLL),
digitally controlled oscillator (DCO), phase–frequency-error
compensator (PFEC).
I. I NTRODUCTION
T HE phase-locked loop (PLL) technique is widely used
in realizing clock generators in electronic systems.
In addition to the output jitter, which may be the most
important performance index of a PLL, the PLL acquisition
time is another important performance index that we have to
consider in some applications, such as the clock generators in
dynamic frequency scaling (DFS) systems. In this paper, we
propose a simple all-digital PLL (ADPLL) as a clock generator
prototype for the DFS application.
Since the settling time of a PLL is inversely proportional
to the loop bandwidth, a well-known method for achieving
fast settling time is to design a PLL that possesses a variable
loop bandwidth. The PLLs can use the wide loop bandwidth
to achieve the fast settling time and switch to the narrow
loop bandwidth for a better jitter performance in the tracking
mode. However, the analog approaches using the variable
Manuscript received March 29, 2015; revised July 11, 2015; accepted
August 16, 2015. Date of publication September 18, 2015; date of current
version April 19, 2016. This work was supported by the Ministry of Science
and Technology, Taiwan, under Grant MOST 103-2221-E-011-059.
The authors are with the Department of Electrical Engineering, National
Taiwan University of Science and Technology, Taipei 10607, Taiwan (e-mail:
D9807403@mail.ntust.edu.tw; chyao@mail.ntust.edu.tw).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2015.2470545
1063-8210 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
loop bandwidth control technique always need to vary the
loop parameters [1]–[7]. It increases the circuit complexity of
the PLLs. To further speed up the acquisition process of the
PLL, Chiu et al. [4] proposed a three-stage discriminator-aided
phase detector to roughly compensate for the accumulated
phase error during the frequency acquisition process.
On the other hand, ADPLLs with the digital loop fil-
ters (DLFs) were proposed for the fast acquisition time
applications because of the easily digital control of the loop
bandwidth [8]–[13]. Meanwhile, the signals are processed in
the digital domain such that many algorithms of digital signal
processing can be applied in designing ADPLLs [14]–[18].
Moreover, the design of digital circuits can be completely
done using highly efficient electronic design automatic tools
nowadays. This trend lowers the effort for designing
the ADPLL circuit and also improves the portability of
the ADPLL design. In this paper, most circuits of the proposed
ADPLL are synthesized by standard cells, and their layouts are
generated by a placement and routing tool. Hence, the design
labor work is minimized, and the design time is dramatically
shortened.
From the jitter-performance point of view, the conventional
ADPLLs are inferior to their analog counterparts mainly
because of the digitally controlled oscillators (DCOs) used in
the ADPLLs usually possessing steep frequency transfer curve
that a slight change of its DCO code leads to large deviation
of its output frequency. Similar to [19], this paper selects
a coarse frequency among several frequency transfer curves
of the DCO before frequency acquisition. All frequency
transfer curves of the DCO have gentle slopes. Furthermore,
we propose a phase–frequency-error compensator (PFEC)
that consists of a phase-error compensator (PEC) and a
frequency-error compensator (FEC). The proposed PEC is
different from those given in [4], [20], and [21]. Our PEC
directly counts the number of clock cycles of the DCO output
within the phase-error duration. The proposed ADPLL then
varies the divisor of the frequency divider (FD) accordingly
to compensate for the phase error in the next reference
clock cycle. Meanwhile, with the phase-error information,
the proposed FEC calculates the required offset of the
DCO’s control code to adjust the DCO’s output frequency.
Consequently, the proposed ADPLL can achieve fast phase
and frequency acquisition, while maintaining a relatively
small timing jitter compared with the previously reported
ADPLLs fabricated by the similar CMOS processes [14], [16].
This paper is organized as follows. Section II
presents the operating principle of the proposed PFEC.
Section III shows the detailed circuit design, including the
HO AND YAO: LOW-JITTER FAST-LOCKED ADPLL WITH PHASE–FREQUENCY-ERROR COMPENSATION
Fig. 1. PEC timing example assuming frequency is in lock.
coarse frequency selector (CFS). Section IV shows the
experimental results. The performance comparison with some
prior arts is also given in Section IV. Finally, the conclusions
are drawn in Section V.
II. P RINCIPLE OF THE P ROPOSED PFEC
A. Operation of the PEC
The PEC of this paper employs the ADPLL output clock
to measure the duration of the phase difference between
the reference clock and the derived signal fed back from
the ADPLL output. The duration of the phase difference is
measured in terms of the number of cycles of the ADPLL
output clock. As an example in Fig. 1, we assume that the
positive edge of the reference clock, CLKref , leads the positive
edge of the derived feedback signal, CLKfb , from the DCO by
τ of time in the beginning. Let the frequency multiplier of
the PLL be M. If the duration corresponding to τ contains
x cycles of the DCO’s output clock (denoted by CLKdco ),
the divisor of the FD, named Ndiv , will be changed to M − x
after the first positive edge of CLKfb . Hence, the second pulse
of CLKfb is advanced by x CLKdco cycles. Therefore, if the
DCO’s output frequency is close to the desired frequency, the
phase-error accumulation can be eliminated well in the second
reference clock cycle. If not, the phase error still becomes
smaller when the output frequency of the PLLs is gradually
close to the desired frequency in the acquisition process.
On the other hand, if CLKfb leads CLKref by x CLKdco
cycles in the beginning, Ndiv will be changed to M + x after
the corresponding positive edge of the reference clock cycle.
Thus, the second pulse of CLKfb is delayed by x CLKdco
cycles. All in all, once the output frequency of a PEC-equipped
PLL is very close to the desired frequency, the phase-error
accumulation can be quickly removed in the next reference
clock cycle, as in [4].
On the other hand, when the output frequency of the PLLs
is away from the desired frequency, the phase difference in the
second reference clock cycle will still exist significantly, even
though a PEC works well. To resolve this problem, this paper
employs a novel FEC to speed up the frequency acquisition
process. The detail operation of the FEC is presented next.
B. Derivation of the Proposed FEC
To illustrate the mechanism of the proposed FEC, we
assume that the phase between CLKref and CLKfb coincides
1985
Fig. 2. FEC timing example.
at the nth reference clock cycle; i.e., τ (n) = 0. At the
next reference clock cycle, the time difference |τ (n + 1)|
between the CLKref edge and the CLKfb edge contains
x CLKdco cycles, as shown in Fig. 2. Then, |τ (n + 1)| can
be expressed as
|τ (n + 1)| = x · τdco (n) (1)
where τdco (n) denotes the cycle time of CLKdco between the
nth edge of CLKref and the (n + 1)th edge of CLKfb . Since
the nth cycle of CLKfb is sure to contain M cycles of CLKdco ,
the CLKdco pulse number within the nth reference clock cycle
is M − x. Hence, τdco (n) can be approximated by
τref
τdco (n) = (2)
M−x
where τref denotes the cycle time of the reference clock.
|τ (n+1)| should be uniformly compensated for among the
next M cycles of CLKdco ; i.e., |τ (n +1)|/M amount of time
should be compensated for in every CLKdco cycle within the
(n + 1)th CLKfb cycle. We call it the cycle time decrement of
CLKdco in this case. According to (1) and (2), we can obtain
|τ (n + 1)| τref x
= . (3)
M M(M − x)
Since the period of CLKdco is determined by the DCO control
code, we would better use the code step, denoted by Stepdco , to
represent the cycle time decrement of CLKdco . Given the DCO
resolution τres , Stepdco can be obtained by dividing (3) by τres .
As long as the relationship between the period of CLKdco and
the DCO control code is sufficiently linear, the average DCO
resolution can be represented by
τdco,max − τdco,min
τres ≈ (4)
2b − 1
where τdco,max denotes the maximum period of CLKdco ,
τdco,min denotes the minimum period of CLKdco , and b denotes
the number of bits of the DCO control code. Thus
(2b − 1)τref x
Stepdco ≈ · . (5)
τdco,max − τdco,min M(M − x)
The term τref /(τdco,max − τdco,min ) can be approximated as
follows. Let N/ max denote the number of rising edges of
CLKdco with the longest period within one cycle of CLKref
and let N/ min denote the number of rising edges of CLKdco
1986 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 5, MAY 2016

with the shortest period within one cycle of CLKref . That is,
N/ max ≈ τref /τdco,max and N/ min ≈ τref /τdco,min . Thus
τref N/ max N/ min
≈ . (6)
τdco,max − τdco,min N/ min − N/ max
Fig. 2 only shows the case that CLKref leads CLKfd . Taking
the other case of CLKref lagging behind CLKfd into account
and defining
⎧
⎪
⎨−1, τ < 0 (CLKref leads CLKfb )
ε = sign(τ ) = 1, τ > 0 (CLKfb leads CLKref ) (7)
⎪
⎩
0, otherwise Fig. 3. Time-domain model of the ADPLL with the PFEC.

we can rewrite (5) as

(2b − 1)N/ max N/ min x Using (6), we obtain the condition for a converging |τ | as
Stepdco ≈ · . (8)
M(N/ min − N/ max ) (M + ε · x)
The update equation for the cycle time of the CLKdco is
τdco (n + 1) = τdco (n) + εStepdco τres . (9)
Notably, when the proposed FEC finds the value of Stepdco
and modifies the DCO’s oscillating frequency, the PEC also
compensates for the phase-error accumulation introduced
by τ (n + 1). Hence, PEC working with FEC can make
the phase difference between the next CLKref edge and
the next CLKfb edge reduced dramatically. However, since
τdco (n) = τdco (n + 1), the phase difference, τ (n + 2),
still exists in the (n + 2)th reference clock cycle, as shown
in Fig. 2. Hence, the proposed ADPLL still needs a few
reference clock cycles to truly acquire both frequency and
phase thereafter. To guarantee that |τ | will converge in this
situation, we have to figure out the required condition.
Fig. 2 shows the case that τ (n + 2) and τ (n + 1)
have the same sign. It is easy to derive that the cycle-time
update (9) guarantees |τ (n + 2)| ≤ |τ (n + 1)| in this case.
Therefore, we have to discuss the case that τ (n + 2) and
τ (n + 1) have the opposite sign. If CLKfb leads CLKref near
the (n + 1)th CLKref edge and CLKref leads CLKfb near the
(n + 2)th CLKref edge, we can also obtain the same result of
|τ (n + 2)| ≤ |τ (n + 1)|. On the other hand, suppose that
CLKref leads CLKfb near the (n+1)th CLKref edge and CLKfb
leads CLKref near the (n + 2)th CLKref edge. In this case
|τ (n + 2)| = τref − [τdco (n)x + (M − x)τdco(n + 1)].
Since |τ (n + 1)| = τdco (n)x, |τ (n + 2)| − |τ (n + 1)| < 0
is equivalent to τref − (M − x)τdco (n + 1) < 2τdco (n)x.
From (2), we can replace τref by (M − x)τdco (n) and write
(M − x)τdco(n + 1) > (M − 3x)τdco(n).
Thus
2x
τdco (n + 1) > τdco (n) − τdco (n). (10)
M −x
Comparing (10) with (9) and ε = −1, we can derive
2x
τdco (n) > Stepdco τres .
M −x
Therefore
(τdco,max − τdco,min )N/ max N/ min
2τdco (n) > .
M(N/ min − N/ max )
τref
2τdco (n) > . (11)
M
Let ftarget = M/τref and f dco,temp = 1/τdco (n). The
condition (11) becomes
f dco,temp < 2 ftarget .
This means, in any case, when the temporary DCO frequency
is less than two times the DCO target frequency, the phase
error will converge even though we let the PEC and the FEC
operate simultaneously.
Let f max and f min denote the maximum DCO frequency
and the minimum DCO frequency on the same DCO transfer
curve, respectively. Then, fmax < 2 f min guarantees that (11) is
satisfied. If the slope of any DCO transfer curve is sufficiently
gentle, fmax < 2 f min can be easily achieved.
Notably, we let the phase difference between CLKref and
CLKfb as small as possible in the beginning, as shown
in Fig. 2. Regarding how to achieve this will be discussed
in Section III.
C. Simulation of the ADPLL With the PEC or the PFEC
We use the block diagram in Fig. 3 to simulate the
acquisition process of the proposed ADPLL. In Fig. 3, the FEC
is modeled as the gain stage β = Stepdco . The PEC is modeled
as a gain of M + εx in the feedback path. Fig. 3 system is a
conventional ADPLL possessing a proportional-integral (PI)
DLF, without the FEC and the PEC. The phase–frequency-
detector (PFD) output, ε, goes to the PI DLF. This PI DLF
has a proportional path gain, α, and an integral path gain, β.
It is noticed that Fig. 3 shows a time-domain model. Its
output is the DCO’s cycle time τdco that equals the DCO’s
free-running period τdco,free plus the DCO time resolution
τres (s/LSB) times the PI-DLF output σ . The term x in (8)
is approximately equal to (|τ (n)|/τdco (n − 1).
Fig. 4 shows the simulated acquisition processes of three
ADPLLs (the conventional one, the one with the PEC,
and the proposed one with the PFEC) with the following
settings: τref = 1 μs, M = 1000 (so, the target τdco = 1 ns),
τres = 0.4 ps, and α = 0.5. Since the acquisition time of
the conventional ADPLL is very long, by setting a 1.007-ns
τdco,free , we can quickly observe the conventional ADPLL
reaching the steady state. The right side of Fig. 4 shows the
HO AND YAO: LOW-JITTER FAST-LOCKED ADPLL WITH PHASE–FREQUENCY-ERROR COMPENSATION
Fig. 4. Comparison of the ADPLLs with the PEC or PFEC.
Fig. 5. Lock-in processes with different τdco,free and α values.
zoomed-in waveforms in the first sixty cycles. We can see
that the initial trace of the DCO output period of the
PEC-equipped ADPLL follows that of the conven-
tional ADPLL. However, the PEC-equipped ADPLL quickly
acquires the phase when the DCO’s output period is close to
its target period. Furthermore, the proposed PFEC-equipped
ADPLL quickly acquires the target frequency from the
beginning, so the trace of the corresponding DCO output
period tends toward the target τdco much faster than the other
two ADPLLs.
Regarding the stability of an ADPLL, the proportional path
gain should be much greater than the integral path gain in the
PI DLF [9], [11], [13], [22]. However, in the proposed ADPLL,
since Stepdco in (8) will eventually get very small as x → 0.
We need not really trouble about the α/β ratio. The simulation
results in Fig. 5 were all done with an initial β = 1. All
acquisition processes with different values of αs and τdco,free s
complete the phase and frequency acquisition in three clock
cycles. However, a large α worsens the jitter performance of
the ADPLL in the tracking mode. Hence, the proposed ADPLL
should use a small α, e.g., 0.5. Furthermore, in Fig. 5, we also
observe that the larger the difference between τdco,free and the
target DCO period is, the more serious the initial ringing in
the beginning of the acquisition process will be.
III. C IRCUIT AND S YSTEM I MPLEMENTATION
A. Proposed ADPLL
Fig. 6 shows the block diagram of the proposed ADPLL.
The ADPLL is composed of a traditional PFD, a CFS,
a DLF, a DCO, a pulse-swallow FD whose divisor ranges
from 768 to 1023, and a PFEC. The DLF includes a loop
1987
Fig. 6. Proposed ADPLL architecture.
bandwidth controller (LBC). In the proposed ADPLL, only
the DCO is custom-built. The other blocks are synthesized
by standard cells in the TSMCs 0.18-μm cell library. The
CLKDLF signal from the PFD is the clock signal for the DLF
and the PFEC. The signal PE from the PFD delivers the phase
difference information to the PFEC. The signals, RNPFD and
RNFD , produced by the CFS are employed to reset the PFD
and the FD, respectively. The 8-bit digital codes, SM [7:0]
and S[7:0], determine the frequency multiplication ratio of the
ADPLL and the divisor of the FD, respectively. CodeDLF [12:4]
and CodeCFS [8:0] are the DCO’s fine-tuning control code
produced by the DLF and the CFS, respectively. When
RNPFD is logic high, Codedco[8:0] connects to CodeDLF [12:4];
otherwise, Codedco [8:0] connects to CodeCFS [8:0]. Moreover,
CodeDLF [3:0] represents the fractional part of the DLF’s
output.
The proposed ADPLL operates as follows. First, RNPFD
is pulled low to disable the PFD and the DLF. Now, the
CFS determines a proper DCO transfer curve that contains
the target frequency. The CFS also determines the values
of N/ max and N/ min . After the CFS determines the DCO
transfer curve, RNPFD is pulled high to enable the PFD and
the DLF with γ = 1 and CodeDLF [12:4] = 256. Next, the
PFEC compensates for the frequency and phase errors for the
ADPLL in a short time. In the meantime, the LBC of the DLF
monitors whether the acquisition process of the ADPLL is
complete. If so, the LowBW signal is set to switch the value
of γ to 1/16. This lowers the loop bandwidth and enhances
the ADPLL’s jitter performance in the tracking mode.
B. Digitally Controlled Oscillator
To get a good jitter performance in a conventional analog
PLL, it is well known that we should make the gain of
the voltage-controlled oscillator small. We adopt the same
concept in this paper and design our DCO possessing small
gain. To reduce the gain of the DCO and retain a wide
operating-frequency range without increasing the bitwidth of
the DCO control word, a common method is to design a
DCO having multiple transfer curves [19]. In this paper, we
design a prototype ADPLL that serves as a clock generator
with fast acquisition time for the DFS application. For a clock
1988 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 5, MAY 2016
Fig. 7. DCO architecture.
Fig. 8. Simulation results of the DCO transfer curves for eight differ-
ent Codedco [11:9] codes and three corner cases: FF-0 °C, SS-80 °C, and
TT-27 °C.
generator used in a digital system, the jitter performance is
more important than the phase noise performance. Hence,
a ring oscillator suffices. A ring oscillator has an advantage
that it takes a smaller area than an LC DCO. Fig. 7 shows
the proposed DCO schematic. It consists of a coarse-tuning
stage, a fine-tuning stage, and a ring oscillator built by
three inverters, I1–I3. The coarse-tuning stage utilizes eight
transmission gates possessing different gate widths to control
the driving capability to I1. The coarse-tuning control code,
Codedco [11:9], is decoded by a 3-to-8 single-bit decoder to
produce D[7:0]. D[7:0] turns ON only one transmission gate
in the coarse-tuning stage. The fine-tuning stage includes
nine different-sized nMOS capacitors controlled by the fine-
tuning control code, Codedco [8:0], to vary the output load
of I1. To make the cycle resolution small, the MOS capacitor
connected to the LSB Codedco [0] is made by the minimum-
sized nMOS transistor. Since the capacitance at I1’s output
node is easily affected by the parasitic capacitors, Cpar0 –Cpar8 ,
we shunt nine capacitors, C0 –C8 , to the corresponding gates
of MOS capacitors for neutralizing the effect caused by the
parasitic capacitors. Each capacitor of C0 –C8 has 10 times
capacitance compared with the corresponding MOS capacitor.
The postlayout simulation results of the DCO period versus
Codedco [8:0] corresponding to eight different Codedco[11:9]
are shown in Fig. 8. To cope with the process–temperature
variations, the selected period range is the overlapped range
Fig. 9. Searching flow of the CFS.
among FF-0 °C, SS-80 °C, and TT-27 °C cases, which ranges
from 0.970 to 1.184 ns. The corresponding frequencies are
from 845 to 1031 MHz. The DCO resolution in the above
range is ∼0.34 ps.
Having eight DCO transfer curves, we need a coarse
frequency selection mechanism to target on one DCO transfer
curve before the acquisition process. This inevitably increases
the time required for the ADPLL clock generator to lock.
As mentioned before, this is what we have to trade for a better
jitter performance.
C. Coarse Frequency Selector
To determine, which curve the DCO’s target clock period
belongs to, the CFS employs an intuitional search method
shown in Fig. 9. The CFS starts from the lower end of a middle
DCO transfer curve by setting Codedco[11:9] = 100 and
Codedco[8:0] = 9’b0. Next, the CFS checks the phase relation
between CLKref and CLKfb . If CLKref leads CLKfb , which
means the period of the DCO is too large, then Codedco[11:9]
will be decreased by 1, as the search path for target 1 shows.
This process continuous until CLKfb leads CLKref , and then
we can determine the DCO curve.
On the contrary, if CLKfb leads CLKref in the beginning,
Codedco[8:0] will be changed to 9’b1, as the search path
for target 2 shows. Next, if the phase relation is unchanged,
Codedco[11:9] is increased by 1 until CLKref leads CLKfb , and
then we can determine the DCO curve.
Next, we use an 11-bit counter to count the number of
CLKdco ’s rising edges corresponding to two ends of the
desired DCO transfer curve within a reference clock cycle to
obtain the values of N/ min and N/ max , respectively. After both
N/ min and N/ max are obtained, the CFS operation is complete,
and RNPFD is set high to enable the PFD, as shown in Fig. 6.
Notably, we take two reference clock cycles to complete
the phase detection, as shown in Fig. 10. In the first reference
clock cycle, the ADPLL forces the phase of CLKfb to be
synchronized with CLKref,de . CLKref,de is a delayed version
of CLKref and will be discussed later. In the second reference
clock cycle, the ADPLL detects the phase relation. RNFD is
pulled high in the first 1.5 reference clock cycles and then
pulled low in the following 0.5 reference clock cycle. At every
falling edge of RNFD , the CFS adjusts the DCO control code
according to the result of the phase detection. To realize the
phase synchronization, the FD is designed to output a pulse
HO AND YAO: LOW-JITTER FAST-LOCKED ADPLL WITH PHASE–FREQUENCY-ERROR COMPENSATION 1989

Fig. 10. Timing chart of the CFS’s phase comparison.

Fig. 12. Timing example of the LBC.

the PFD becomes logic low, a short negative pulse output by

theNAND gate resets the counter. Next, the counter is enabled
when the inverted PE signal is high. During the time that the
counter is enabled, it counts the number of CLKdco ’s positive
edges to obtain the x value, as presented in Section II.
Fig. 11(b) shows the pseudocode of the divisor controller
that calculates the required number, S, for the FD. The
8-bit SM determines the steady-state divisor M of the proposed
ADPLL by M = 768 + SM . The pseudocode is designed
straightforward according to the PEC operation presented in
Section II, and the fact that S is an 8-bit unsigned number.
Fig. 11(c) calculates Stepdco given in (8). In (8), M is
known and N/ max and N/ min are determined when the CFS
process completes. Thus, the first product in (8), denoted by K
in Fig. 11(c), is calculated before the PFEC starts. Next, the
computation of Stepdco is straightforward except that when
x < 2, which means the phase difference between CLKfb and
CLKref is very small, Stepdco is set to 1.
Fig. 11. (a) Counter of the PFEC. (b) Divisor controller. (c) Calculator of
the code step.
E. Digital Loop Filter
The DLF is composed of a PI controller and an LBC,
as soon as possible after it is enabled by the rising of RNFD .
as shown in Fig. 6. According to the simulations discussed
Since the FD consists of some D flip-flops, when it is triggered
in Section II-C, we let α be 0.5, β equal Stepdco , and the
by CLKdco , the FD’s output is delayed by the clock-to-Q
initial γ be 1 in the DLF. The LBC monitors the variation
delay of a D flip-flop, τdff . Hence, we let CLKref experience
of the DCO’s control code to determine whether the ADPLL
a replica delay of τdff to produce the CLKref,de signal for
is going to be locked. When the control code bounces back
the phase synchronization. Notably, after the rising of RNFD ,
and forth with equal count-up and count-down values, and the
the FD waits a random time for being triggered by CLKdco .
β value is steady, the LBC is aware that the ADPLL will be
This random time cannot be compensated for in producing
locked soon. Fig. 12 shows a timing example of the DLF.
the CLKref,de signal. Fortunately, the maximum of this random
The LBC employs two counters, CounterUP and CounterDN ,
time will not exceed one cycle of the DCO output clock, which
to record the count-up value and the count-down value of the
is 1.184 ns shown in Fig. 8. Since the reference clock cycle
DCO control code, respectively. The signal Failcount indicates
of this paper is 1 μs, this random time only occupies a small
whether the β value is steady or not. A high Failcount indicates
portion of a reference clock cycle. Moreover, as mentioned in
that the β value is not steady yet; thus, the LBC resets
Section II, this phase synchronization technique is also used
both counters. When the LBC detects a direction change of
in the FEC of this paper.
the DCO control code, it pulls low Failcount and checks the
The CFS search time of a proper DCO transfer curve can
contents of CounterUP and CounterDN . If they are the same,
be figured out by analyzing Fig. 9. It should take 6, 8, 10, or
and β is steady, the LBC sets the LowBW signal to logic high
12 reference clock cycles depending on, which DCO transfer
and modifies γ = 2−4 that equivalently reduces the bandwidth
curve the target frequency belongs to.
of the loop filter.

D. Phase- and Frequency-Error Compensator IV. E XPERIMENTAL R ESULT

The PFEC contains three parts shown in Fig. 11. Fig. 11(a) Fig. 13(a) shows the microphotograph of the proposed
shows a counter. When the phase-difference signal (PE) from ADPLL in the TSMC 0.18-μm CMOS technology. The active
1990 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 5, MAY 2016
Fig. 13. (a) Microphotograph of the proposed ADPLL. (b) Experimental
setup.
area of the core circuit is ∼0.476×0.375 mm2 . Only the DCO
and the DCO input buffer are custom-built. The rest of the chip
is synthesized by standard cells. The total power consumptions
are 4.52 and 5.49 mW for an 860-MHz output and a 1-GHz
output, respectively. The power consumptions of the DCO are
1.58 and 1.75 mW at 860 MHz and 1 GHz, respectively.
The experimental setup is shown in Fig. 13(b). The input
reference clock CLKref is 1 MHz. The input clock signal and
the signal Start are generated by Agilent’s J-BERT N4903A
pattern generator. The off-chip signals, CLKref,out , CLKdco,od ,
and CLKfb,od , corresponding to CLKref , CLKdco , and CLKfb ,
respectively, are measured by Tektronix’s DPO70804 oscillo-
scope. The internal digital signal that we want to observe is
measured by Tektronix’s TLA5202B logic analyzer. The 8-bit
digital code, SM , for determining the frequency multiplication
ratio of the proposed ADPLL is serially shifted into an 8-bit
shift-register.
Fig. 14 shows the measured DCO control code during
the acquisition process for a 1-GHz output. The zoomed-in
waveform is also provided in Fig. 14. Since the CFS adjusts the
Codedco [8:0] value at every falling edge of RNdco , as shown
in Fig. 10, the Codedco [8:0] is changed at 1.5, 3.5, and 5.5 μs.
The value of Codedco[11:9] is kept at 4; i.e., the target
frequency is on the middle DCO transfer curve. The CFS takes
six reference clock cycles (6 μs) to complete the coarse tuning.
After the CFS operation, the ADPLL enters the acquisition
mode. In the beginning of the acquisition mode, the ADPLL
Fig. 14. Measured lock-in process of fine-tuning control code
at 1-GHz output frequency.
Fig. 15. Jitter performance of the proposed ADPLL at 1 GHz.
sets Codedco[8:0] to 256 and forces phase synchronization.
Next, the ADPLL evaluates the phase difference between
CLKref and CLKfb at 7 μs and then compensates for the phase
and frequency error at 8 μs. We can observe that the proposed
ADPLL is almost in the locked state at 9 μs. Finally, the LBC
detects that the control code bounces back and forth with equal
count-up and count-down values, so the LBC sets γ = 2−4
to lower the loop bandwidth at 11 μs; i.e., 5 reference clock
cycles after the CFS operation.
Fig. 15 shows that the measured peak-to-peak jitter and
the rms jitter are 28.75 and 1.31 ps, respectively, at 1-GHz
output clock. Table I summarizes the performance comparison
between this paper and some prior arts. The proposed ADPLL
with PFEC possesses sufficiently fast acquisition time. Since
we take the jitter performance as the most important perfor-
mance index, we design our DCO having a low DCO gain.
Hence, the proposed DCO has to have several DCO transfer
curves to cover the required frequency range. Therefore, the
proposed DCO needs some time to determine a DCO transfer
HO AND YAO: LOW-JITTER FAST-LOCKED ADPLL WITH PHASE–FREQUENCY-ERROR COMPENSATION
TABLE I
C OMPARISONS W ITH P REVIOUS W ORKS
curve, which the target frequency belongs to. Thus, the acqui-
sition time of the proposed ADPLL includes 6–12 reference
clock cycles for the CFS operation. After the CFS operation,
the time required for the phase and frequency acquisition
is not more than 5 reference clock cycles. Regarding the
settling time in clock cycles, the proposed ADPLL is only
inferior to those of [10] and [16]. For the jitter performance
in terms of % of a period, since the proposed DCO carries
a small DCO gain, the rms jitter of the proposed ADPLL
is only inferior to [25], and the peak-to-peak jitter of the
proposed ADPLL is only inferior to [20]. On the other hand,
we employ the figure of merit (FOM) in [25] and a FOM2 ,
which is from normalizing FOM by the supply voltage, as
two performance indices for comparison. Regarding the FOM,
the ADPLL in [25] is the best, and the proposed ADPLL
is comparable with the one in [24]. After normalizing FOM
by the supply voltage, the FOM2 of the proposed ADPLL is
comparable with the ADPLL chips designed by the advanced
CMOS technologies [20], [23]–[25].
V. C ONCLUSION
In this paper, an ADPLL with PFEC for shortening the
acquisition time was proposed. The phase-error information
was obtained using the DCO’s output to measure the time
difference between the rising edges of the reference clock
and the feedback signal. The PFEC modified the divisor of
the FD and the integral gain of the DLF to compensate for
the phase error and to adjust the DCO’s oscillating frequency,
respectively. All circuits except the DCO and the DCO input
buffer were synthesized using the TSMCs 0.18-μm cell library.
The DCO and the DCO input buffer were custom-built.
The measurement results demonstrate that the acquisition
time of the proposed ADPLL requires no more than
17 reference clock cycles, including 6–12 clock cycles to
determine a proper DCO transfer curve, which the target
frequency belongs to. The rms jitter and the peak-to-peak
jitter are 1.31 and 28.75 ps, respectively, measured at 1-GHz
output clock.
1991
ACKNOWLEDGMENT
The authors would like to thank the Chip Implementation
Center of Taiwan, ROC, for fabricating the prototype chips of
the proposed all-digital phase-locked loop.
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Yung-Hsiang Ho was born in Taichung, Taiwan,
in 1987. He received the B.S. and Ph.D. degrees in
electrical engineering from the National Taiwan Uni-
versity of Science and Technology, Taipei, Taiwan,
in 2009 and 2015, respectively.
His current research interests include CMOS ana-
log/digital IC design for the fast acquisition clock
generator.
Chia-Yu Yao (S’88–M’92) was born in Changhwa,
Taiwan, in 1963. He received the B.S. degree
from National Taiwan University, Taipei, Taiwan,
in 1985, and the M.S. and Ph.D. degrees from
the University of California at Los Angeles,
Los Angeles, CA, USA, in 1988 and 1992,
respectively, all in electrical engineering.
He served as a second Lieutenant with the Chinese
Military Academy, Kaohsiung, Taiwan, from
1985 to 1987. He was with LinCom Corporation,
Los Angeles, where he was involved in a program
of satellite communication system analysis through the National Aeronautics
and Space Administration, Houston, TX, USA, from 1990 to 1991, and
the Department of Electronic Engineering, Huafan University, Taipei, from
1992 to 2006. He joined the Department of Electrical Engineering, National
Taiwan University of Science and Technology, Taipei, in 2006, where he is
currently a Professor and the Associate Dean of Research and Development
Office. His current research interests include digital filter design, CMOS
VLSI, CMOS RFIC, and neural networks.
Dr. Yao was one of the recipients of the Group Achievement Award from
Computer Sciences Corporation in 1991. He was the Adviser of the Best
Student Paper Award in signal processing from the National Symposium on
Telecommunications, Taoyuan, Taiwan, in 2000, and the Adviser of the Praise
Award of Student Paper Contest from the Chinese Institute of Electrical
Engineering in 2009. He received the Best Advisor Award of the Macronix
Golden Silicon Semiconductor Design and Application Competition in 2012,
and the Distinguished Teaching Award of the National Taiwan University of
Science and Technology in 2013.