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Embedded Image Grabber and Processing

System Based on Camera Link

Li, Jianrong1,2; Gao, Huibin1; Wang, Zhiqian1; Geng, Tianwen1; Zhao,Yan1
1.Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences
Changchun, China
2.Graduate School of the Chinese Academy of Sciences
Beijing, China

Abstract—In order to realize real-time measurement based camera link a necessity[2-3]. The camera link interface will
on image, proposes a design project of embedded image reduce support time, as well as the cost of that support.
grabber and processing system based on camera link The standard cable will be able to handle the increased
interface. The system adopts FPGA+DSP structure design. signal speeds, and the cable assembly will allow
DSP used to process the image and send out processing
customers to reduce their costs through volume pricing[4-5].
results to external. FPGA adopts modularize design. It
contains camera link interface module, image memory This article introduces a embedded image grabber and
module, DSP connection module and so on. The experiment processing system based on camera link interface[6]. The
results show that the system design flexibility, small cubage, system adopts FPGA+DSP structure design. it can satisfy
high real-time image processing, and can fulfil the the needs of image processing speed, also convenient
requirement of real-time measurement. design interface with other systems.
Keywords- camera link interface; real-time image II. SYSTEM CONFIGURATION
processing; dsp;fpga
DSP and FPGA are the core parts of embedded image
acquisition, and processing system, and camera link
I. INTRODUCTION interface chip, FLASH, SRAM and so on are the periphery
Along with the development of image sensor, measure parts of embedded image acquisition and processing
technology based on image is more application. Because system. The system configuration shows as figure 1.
the data of image is so large, so the transmission The principle of embedded image acquisition and
technology, memory technology and processing processing system as follows: First, DSP sends image
technology of image are bottle-necks of image acquisition command to camera link interface module of
measurement. FPGA[7], camera link interface module configures the
Many camera and frame grabber manufacturers camera and send external trigger to camera by CC1 control
contributed to the development and definition of the port. Second, camera link interface module grab valid
camera Link standard. Camera link is a communication image by DVAL signal, LVAL signal and FVAL signal of the
camera, and the same time write the data to SRAM. After store
interface for vision applications[1]. The interface extends this frame image, FPGA sends external interrupt signal to
the base technology of channel link to provide a DSP. Finally, DSP reads the data from SRAM and
specification more useful for vision applications. processes the data, and attains measurement result. When
Increasingly diverse cameras and advanced signal and
data transmissions have made a connectivity standard like

Figure 1. system configuration.

finish debug program of DSP, stores the program codes to The program flow chart shows that the main
FLASH, and the same time sets the DSP work mode as difficulties of the program is the image processing.
computer mode. When the system restarts work, DSP will Because the images is a very large amount of data,
run the program of FLASH, and accomplish image grab different algorithm can make the calculation amount of
and image process. DSP has the very big difference. But in embedded
systems, data processing speed is the key, so different
image algorithm will directly influence the performance
DSP is this image grabber and processing system of the system.
CPU, is the core of the system components. It controls the
work flow of the system, and processing image data IV. FPGA PROGRAM DESIGN
according to the image processing algorithm of this The FPGA program uses modular design. The
system. Finally, gets the expectation calculating results program basically has camlink interface module, the
through the calculation of it, and send the calculating SRAM interface module, and DSP interface module, etc.
results to superordination machine through the Camlink interface is a kind of camera standard
communication interface. According to the function of interface, and it is the most widely used camera interface
digital signal processor (DSP), DSP software mainly today. The embedded image grabber and processing
includes the main program, DSP initial program, and the system can configurate the camera through the Camlink
upper machine subgroups of communication procedure, interface, control the camera's imaging range through the
image processing procedure, solving quantum procedures, Camlink interface, control the camera unit exposure time
etc. For One image processing the subroutine and through the Camlink interface, control the camera's data
contains the image extraction procedure, image judgment output format through the Camlink interface etc. And at
subroutine, image segmentation procedure, etc. Program the same time through Camlink interface the system can
flow chart shows as figure 2. receive the output data synchronization of the camera,
receives the grey of images information, to receive the
data of image state information, etc. According to the
information, can finally obtained the camera image
The earliest use of FPGA do Camlink interface is
directly in the Camlink interface LVDS signal access.
When read signals in FPGA, the first use the resources of
FPGA receives LVDS signal converted into TTL signal,
and then put these TTL signal to the assigned address
through timing read command. When sending orders, at
the first send the TTL instructions, and then convert the
TTL signals into LVDS signal. Because Camlink
interface fast data transmission, so the program is very
complex in FPGA. In order to solve this problem, the chip
manufacturers make the dedicated Camlink interface chip.
The Interface chip used as to realize interaction
conversion between the LVDS signal and TTL signal.
In this embedded image grabber and processing
system, Camera link interface chip choose ds90lv047 and
The DS90CR286 receiver converts the LVDS data
streams back into 28 bits of LVCMOS/LVTTL data. At a
transmit clock frequency of 66 MHz, 28 bits of TTL data
are transmitted at a rate of 462 Mbps per LVDS data
channel. Using a 66 MHz clock, the data throughput is
1.848 Gbit/s (231 Mbytes/s).
58 conductors are required. With the Channel Link
chipset as few as 11 conductors (4 data pairs, 1 clock pair
and a minimum of one ground) are needed. This provides
a 80% reduction in required cable width, which provides a
system cost savings, reduces connector physical size and
cost, and reduces shielding requirements due to the
cables’ smaller form factor.
The DS90LV047A is a quad CMOS flow-through
differential line driver designed for applications requiring
ultra low power dissipation and high data rates. The
Figure 2. program flow chart. device is designed to support data rates in excess of 400
Mbps (200 MHz) utilizing Low Voltage Differential The camera output data be converted 28 parallel data
Signaling (LVDS) technology. The DS90LV047A accepts by ds90cr286 chip. Including 24 bits image data, can
low voltage TTL/CMOS input levels and translates them teleport from 8 bits to 24 bits RGB signal image data.
to low voltage (350 mV) differential output signals. In This design chooses single channel black and white
addition, the driver supports a TRI-STATE function that output, so the data bus selects 16 bits, can satisfy the
may be used to disable the output stage, disabling the load requirements image grey adjustment. Another three bits
current, and thus dropping the device to an ultra low idle respectively be defined for data effective (DVAL) signal,
power state of 13 mW typical. The DS90LV047A has a line effective (LVAL) signal and frame effective (FVAL)
flow-through pin out for easy PCB layout. The EN and signal, and last bit reserved. If the sender as long as the
EN* inputs are together and control the TRI-STATE timing driving in accordance with the contract, then the
outputs. The enables are common to all four drivers. The receiver can calculate complete image information of
DS90LV047A and companion line receiver receive data by the three state signals[8].
(DS90LV048A) provide a new alternative to high power When FVAL and LVAL both HIGH, the data
psuedo-ECL devices for high speed point-to-point information is one pixel gray information in a
interface applications. CAM_CLOCK clock cycle. The control module generates
Design a control module matches with the ds90lv047 write memory address and write control signal by
in FPGA by VHDL, for controls CC1, CC2, CC3, CC4 CAM_CLOCK signal, FVAL signal and LVAL signal.
output. Sets application parameters to the camera and The control module’s timing simulation figure as shown
control the external trigger of camera. The control module in figure 5.
shows as figure 3. The CS signal is the module control
signal. When CS signal is HIGH, the control module does
not work, output signal is not changed with input signal.
When CS signal is LOW, the module in the work, output
signal is changed with input signal. Because the control
module is very easy, so does not introduce its timing

Figure 5. ds90cr286 control module timong simulation.

Design a DSP and SRAM interface module, used to

write the 16 data of image information to SRAM, also it
is used to DSP writes and reads the SRAM. The DSP and
SRAM interface module show as figure 6.

Figure 3. ds90lv047 control module.

Design a control module matches with the ds90cr286

in the FPGA, for receiving the image information and
clock information of camera. The control module shows
as figure 4.

Figure 6. DSP and SRAM interface module.

DSP sends a control signal to the DSP and SRAM

interface module. The signal controls the DSP read and
write control signal to SRAM is valid or the ds90cr286
control module read and write control signal to SRAM is
Figure 4. ds90cr286 control module.
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This work was supported in part by the jilin Provincial [8] YANG Fengbao,YANG Fanglin,WEI Quanfang,HAN Yan.Study
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