FET

→ Basic Structure of JFET:

→ Basic Operation of JFET:

- VDD provides a drain-to-source voltage and supplies current from drain to source. VGG
sets the reverse-bias voltage between the gate and the source.
- The JFET is always operated with the gate-source pn junction reverse-biased.
- Reverse biasing of the gate-source pn junction produces a depletion region which
extends into the n-channel, thus increasing its resistance.
- Therefore, the channel width and resistance (indirectly ID) can be controlled using
gate-source reverse bias voltage.
→ Schematic Symbols:
→ JFET Characteristics:

- Drain Characteristics:

● Consider the case where VGS = 0, and VDD is increased from 0 to a positive value.
● Ohmic region: As VDD increases, ID increases proportionally until VDD = VP (pinch off
vtg.).
● Active region: As VDD equals pinch off voltage, the reverse bias creates enough depletion
region to prevent ID from increasing and thus keeping it constant.
● Breakdown: Breakdown occurs when ID increases very rapidly compared to VDS. It can
cause irreversible damage to the device and hence JFET is operated below breakdown.

- Pinch-off Voltage:
● For VGS = 0, the value of VDS at which ID becomes constant ⇒ pinch-off voltage.
● For a particular JFET, VP has a fixed value.
● This value is always specified for VGS = 0 and is found on the datasheet for the JFET.

- VGS controls ID:

● We connect a bias voltage to gate such that VGS is negative.
● By adjusting VGS a family of drain curves is produced.
● The larger the value of VG, the smaller is the value of ID.
● For each increase in VGS, the JFET reaches pinch-off at a lower value of VDS.
- Cutoff Voltage:
● The value of VGS that makes ID approximately zero is the cutoff voltage, VGS(off).
● This cutoff effect is caused by the widening of the depletion region to a point where it
completely closes the channel.
● The JFET must be operated between VGS = 0 V and VGS(off).
● ID will vary from a maximum of IDSS to a minimum of almost zero.
● VGS(off) and VP are always equal in magnitude but opposite in sign.
● A datasheet usually will give either VGS(off) or VP, but not both.

- JFET Universal Transfer Characteristic:

● A.k.a. Transconductance curve.
● Shows the relation between VGS and ID.
● Notice that the bottom end of the curve is at a point on the VGS axis equal to VGS(off) and
the top end of the curve is at a point on the ID axis equal to IDSS.
● When:
○ VGS = VGS(OFF) ⇒ ID = 0
○ VGS = 0.5VGS(OFF) ⇒ ID = (IDSS / 4)
○ VGS = 0.3VGS(OFF) ⇒ ID = (IDSS / 2)
○ VGS = 0 ⇒ ID = IDSS

● The transfer curve can also be developed from the relation between ID and VGS.
0

● JFET transfer characteric curve can be expressed approximately using Schokley’s

Equation:

⇒ JFETs and MOSFETs are often referred to as square-law devices.

- JFET Forward Transconductance:

● The forward transconductance (transfer conductance), gm, is the change in drain current
(ΔID) for a given change in gate-to-source voltage (ΔVGS) with the drain-to-source voltage
constant.
● It is expressed as a ratio and has the unit of siemens (S).
 ● , ,
- Input Resistance & Capacitance:
● A JFET operates with its gate-source junction reverse-biased, which makes the input
resistance at the gate very high.
● This high input resistance is one advantage of the JFET over the BJT.

● The input capacitance, CISS, is a result of the JFET operating with a reverse-biased pn
junction.

- AC Drain to Source resistance:

● A large change in VDS produces only a very small change in ID.
● The ratio of these changes is the ac drain-to-source resistance (r’ds):

→ JFET Biasing:
- Self Bias:
● Most common type of JFET biasing.
● For a JFET, gate-source junction should always be reverse biased. This can be achieved
by a negative VGS for an n-channel JFET and positive VGS for p-channel.
● Gate resistor RG does not affect bias because it has essentially no voltage drop across it;
and therefore the gate remains at 0 V.
● RG is only necessary to force the gate to be at 0V and to isolate an ac signal from ground
in amplifier applications.
● For n-channel JFET in above figure, IS produces a voltage drop across RS and makes
the source positive w.r.t. ground.
● IS = ID and VG = 0 ⇒ VS = IDRS
● Therefore, gate to source voltage is:
VGS = VG - VS = 0 - IDRS = -IDRS
⇒ VGS = -IDRS