Reduction of pump current mismatch in the charge pump.

While the cascode charge pumps can be used to

charge-pump PLL
M.-S. Hwang, J. Kim and D.-K. Jeong
A charge pump that minimises the mismatch between the charging and
discharging currents and keeps the currents constant across a wide
output voltage range is described. The improved current matching
helps reduce the static phase offset and reference spur of a charge-
pump phase-locked loop (PLL) and the constant currents help
control the PLL dynamics precisely. The proposed charge pump with
dual compensation circuits demonstrates current mismatch of less
than 3.2% and pump-current variation of 1.7% over the output
voltage ranging from 0.2 to 1.0 V in the 0.13 mm CMOS process
with 1.2 V supply.
remove the current variation without increasing parasitic capacitance,
they are posed by the current mismatch from process variation [6, 7].
In Fig. 2a, the opamp in a feedback loop actively controls the PMOS
bias voltage VBP so that the pump currents are matched for the current
VCP_OUT [3]. While the difference between the currents can be signifi-
cantly reduced, as shown in Fig. 2b, the variation of the current with
VCP_OUT still remains. It is noteworthy that attention must be paid to
ensure the correct start-up of the circuit.
UP
VBP IP
ICH

Introduction: In modern communication systems, a phase-locked loop
(PLL) is a key building block for clock generation and recovery. The
majority of the PLLs use a charge pump to implement an integrating
loop filter. Its low-leakage integration has helped charge-pump based
PLLs achieve a wide frequency range compared with other active
filter implementations and gain such wide popularity today [1].
However, one of the challenges that remains in the conventional
charge-pump PLL design is minimising the current mismatch in the
charge pump. Any difference between the charging and discharging cur-
rents can cause static phase offset as well as dynamic jitter, known as
reference spur [2].
Various circuit techniques to reduce current mismatch have been
reported in the literature, but they remove current mismatch at the cost
of reduced output dynamic range. A wide dynamic range of the
charge pump is desired for the wide operating range of the PLL.
While the active feedback circuits based on operational amplifiers or
diodes proposed in [3] and [4] compensate the current mismatch, they
similarly suffer from reduced dynamic range owing to excessive
pump-current variation over the output voltage.
In this Letter, we propose a charge pump that improves current match-
ing in the charge pump without sacrificing the output dynamic range via
a dual compensation method.
VCP_OUT
self- VBN IDIS IDIS ICH
bias
DN
VCP_OUT
a b
Fig. 2 Conventional charge pump with single compensation
a Circuit and bias
b Characteristic
The proposed charge pump utilises the second compensation circuit to
reduce both the current mismatch and the current variation as shown in
Fig. 3. The resulting circuit has two push-pull charge pumps (CP1 and
CP2) and two replica-feedback biasing circuits (compensator 1 and 2).
The first compensator controls the bias voltage VBP2 so that the charging
current of the CP2 (ICH2) can be kept equal to the discharging current of
the CP1 (IDIS1). The second compensator controls VBN2 so that the dis-
charging current of the CP2 (IDIS2) can be kept equal to the charging
current of the CP1 (ICH1). As a result, the total charging and discharging
currents are kept the same as each other.

CP1 CP2 compensator 1 compensator 2

UP

VBP UP
ICH IP VBP 2
VCP_OUT ICH1 ICH2

VBP1 VBP1
self- VBN IDIS
bias IDIS ICH VCP_OUT

DN self- VBN1 VBN 1

bias
VCP_OUT
IDIS1 IDIS 2 VBN2

a b
DN
Fig. 1 Conventional charge pump
a Circuit and bias
b Characteristic
Fig. 3 Proposed charge pump and bias circuit

Proposed circuit: Fig. 1a shows a push-pull charge-pump circuit and its

bias circuit commonly used in PLLs and DLLs. The NMOS bias voltage
VBN may be provided by a bandgap reference or a supply-independent
self-biasing circuit. The PMOS bias voltage VBP, on the other hand, is
generated via a charge-pump replica circuit to keep the charging
current (ICH) nominally equal to the discharging current (IDIS) when
While the dual compensation circuit keeps both the ICH and IDIS
equal, the current variation can be mitigated considerably as well
because the deviation of ICH2 (IDIS2) counterbalances that of ICH1
(IDIS1) (Fig. 4). The variation in the charging and discharging current
of the CP1 can be given as:
the output voltage VCP_OUT is equal to VBP. However, as the output    
1 W 
voltage varies, the pumping currents deviate from each other owing to DICH1 ¼  mp Coxp ðVGSP  Vthp Þ2 lp DVDSP  ð1Þ
the channel length modulation effect (Fig. 1b). While the longer 2 L P
channel length may mitigate the channel length modulation effect, the    
increased parasitic capacitance coupling between the inputs and output 1 W 
of the charge pump may degrade the transient response of the charge
pump via charge injection and charge sharing [5]. The difference
between the total charge transferred during the charging and discharging
transients has the same adverse effect as the DC current mismatch. In
addition, the long-channel device presents the larger input capacitance
and degrades the speed and power of the preceding circuits that drive
ELECTRONICS LETTERS 29th January 2009 Vol. 45
DIDIS1 ¼  mn Coxn ðVGSN  Vthn Þ2 ln DVDSN  ð2Þ
2 L N
where VGSP ¼ VBP1 – VDD , VGSN ¼ VBN1 , DVDSP ¼ VBP1 – VCP_OUT,
DVDSN ¼ VCP_OUT – VBP1. In (1) and (2), lp and ln represent the
channel length modulation coefficients of the PMOS and NMOS transis-
tors, respectively. Assuming that charging and discharging currents are
No. 3
equal when the output voltage equals to VBP1 , (2) can be rewritten as: Conclusion: A simple and effective circuit technique to remove the
current mismatch in the charge pump is proposed. The proposed dual
1 þ lp VBP1 ln
DIDIS1 ¼ DICH1 ð3Þ compensation method keeps the current mismatch and current variation
1 þ ln VBP1 lp below 3.2 and 1.7%, respectively, for the output voltage ranging from
Since the deviation of ICH2 (DICH2) is equal to that of IDIS1 (DIDIS1), the 0.2 to 1.0 V in the 0.13 mm CMOS process with 1.2 V supply. With
total current deviation of the proposed charge pump is the difference the proposed circuit, the distortion that leads to the static phase offset
between DICH1 and DIDIS1 and can be expressed as: and spur in the PLL can be significantly reduced even when short-
channel devices are used in the charge pump.
DICH Total ¼ jDICH1  DIDIS1 j
  # The Institution of Engineering and Technology 2009
 lp  ln  ð4Þ
¼  DICH1  23 September 2008
lp ð1 þ ln VBP1 Þ
Electronics Letters online no: 20092727
In the 0.13 mm process, ln and lp are about 1.43 and 0.88, respectively, doi: 10.1049/el:20092727
and the expected current variation of the proposed circuit is less than M.-S. Hwang and D.-K. Jeong (School of Electrical Engineering and
34% of the conventional charge-pump current variation. Besides, the Computer Sciences, Seoul National University, 599 Gwanangno,
proposed charge pump is free from the start-up problem because ICH1 Kwanak-gu, Seoul 151-742, Korea)
flows regardless of the output voltage level.
E-mail: msh@isdl.snu.ac.kr
IP IP IP
J. Kim (Rambus Inc., 4440 El Camino Real, Los Altos, CA 94022, USA)

ICH 2 ICH= ICH1 + ICH 2 References

IDIS 2 ICH1 IDIS1
VCP_OUT
Fig. 4 Concept of the proposed charge pump
Simulation results: Fig. 5 shows the simulation results of the conven-
tional charge pump (Fig. 5a) and the proposed charge pump (Fig. 5b).
Both circuits were carefully optimised and simulated in the 0.13 mm
standard CMOS process. The maximum mismatch was 3.2% for the pro-
posed charge pump, while that of the conventional charge pump
recorded 30.1%. Maximum current deviations were 1.7 and 20.6% for
the proposed circuit and the conventional circuit, respectively.
Assuming that tolerable current variation is +10%, the dynamic range
of the proposed charge pump is from 0.07 to 1.05 V, which covers
more than 80% of the 1.2 V supply voltage while the conventional
charge pump offers only 34% of the supply. The current deviation of
the proposed charge pump did not exceed 1.7% over the output
voltage from 0.2 to 1.0 V, while the maximum current deviation of
the single-compensated charge pump was 17.3%.
IDIS = IDIS1 + IDIS 2
1 Gardner, F.: ‘Charge-pump phase-lock loops’, IEEE Trans. Commun.,
VCP_OUT VCP_OUT
1980, 28, (11), pp. 1849–1858
2 Rhee, W.: ‘Design of high-performance CMOS charge pumps in phase-
locked loops’. Proc. ISCAS, Orlando, FL, USA, July 1999, Vol. 2,
pp. 542– 548
3 Lee, J.S., Jin, W.K., Choi, D.M., Lee, G.S., and Kim, S.: ‘A wide range
PLL for 64x speed CD-ROMs and 10x Speed DVD-ROMs’, IEEE Trans.
Consum. Electron., 2000, 46, (3), pp. 487 –493
4 Ha, K.S., and Kim, L.S.: ‘Charge pump reducing current mismatch in
DLLs and PLLs’. Proc. ISCAS, Kos, Greece, May 2006, pp. 2221–2224
5 Larsson, P.: ‘A 2 –1600-MHz CMOS clock recovery PLL with low-Vdd
capability’, IEEE J. Solid-State Circuits, 1999, 34, (12), pp. 1951– 1960
6 Hieu, N.T., Lee, T.W., and Part, H.H.: ‘A perfectly current matched
charge pump of CP-PLL for chip-to-chip optical link’. Conf. on Lasers
and Electro-Optics Pacific Rim, Seoul, Korea, August 2007, pp. 1 –2
7 Kim, K.K., Kim, Y.B., and Lee, Y.J.: ‘Phase-locked loop with leakage
and power/ground noise compensation in 32 nm technology’,
J. Semicond. Technol. Sci., 2007, 7, (4), pp. 241– 246

150
Current, µA

100

max. mismatch = 30.12 µA max. mismatch = 3.19 µA

50
max. error = 20.6 µA max. error = 1.67 µA

0
0 0.3 0.6 0.9 1.2 0 0.3 0.6 0.9 1.2
VCP_OUT , V VCP_OUT , V
a b

Fig. 5 Simulated output currents of

a Conventional charge pump
b Proposed charge pump

ELECTRONICS LETTERS 29th January 2009 Vol. 45 No. 3