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CMR INSTITUTE
OF TECHNOLOGY

Department of Electronics & Communication Engineering.

Question Bank
Digital Design of VLSI systems

Unit1.

1. What does a verilog module define

2. Explain in brief the three principal design taks that benefit the use of verilog.
3. What is meant by design methodology?
4. Explain the basis steps of design methodology, in brief.
5. What are the effects of capacitive loading and propagation delay on signal transitions between
logic levels?
6. Develop a sequential circuit that has a single data input data signal ‘S’ and produces an output
‘y’. The output is ‘1’ whenever ‘S’ has the same value over three successive clock cycles, and O
otherwise. Assume that the value of ‘S’ for a given clock cycle is defined at the time of the rising
clock edge, at the end of the clock cycle.
7. Describe the different types (styles) of descriptions , with suitable examples.
8. Explain the design methodology with flow chart.
9. Explain abstraction with example
10. Describe the design methodology for hardware/software co design with flow chart.

UNIT2.

11. Using AND-OR-INVERTER (AOI) logic implement the given Boolean function F= (x+yz’).(yz)’. Show
how the Boolean equation for F can be transformed in SOP form. Use the laws of Boolean
algebra for reduction and implement the SOP from the result.
12. Write a verilog model to devise a one-hot code to represent the days of the week (Monday
through Sunday).
13. Draw the circuit diagrams of parity trees for generating and checking odd parity for an 8 bit
code.
14. Develop a verilog model for a 7-segment decoder. Include an additional input ‘blank’ that
overrides the BCD input and causes all segments not to be lit.
15. What are the effects of bit errors on signal values in digital systems?
16. Write a verilog code for the burglar alarm to be a priority encoder, with zone 1 having highest
priority, down to zone 8 having lowest priority.
17. Develop a verilog model for a 7-segment decoder. Include an additional input, blank, that
overrides the BCD input and causes all segments not to be lit.
18. Draw a circuit diagram, for multiplexer that selects among four sources of data, each of which is
encoded with three bits. The circuit should be implemented 4-to-1 multiplexers.
19. Explain the concept of parity error checking. Discuss the parity trees for generation and checking
even parity to augment an 8 bit code.
20. Discuss BCD code and 7-segment decoders.
21. Develop a verilog model for a 7 segment decoder. Include an additional input bank, that
overrides the BCE input and causes all segments not to be lit
UNIT 3

22. With a neat figure , explain the equality comparator and inequality comparator.
23. Develop a verilog model of a converter that converts a 4 bit binary code input to a 4 bit gray
coded output.
24. What number is represented by the signal fixed – point binary number 111101 assuming the
binary point is four places from the right.
25. Implement a structural verilog model for 4 bit carry look ahead adder.
26. Write a note on the various operations that can be performed on fixed-point –numbers.
27. Write a verilog code for 3 bit ripple carry adder
28. Write a verilog code for 4 bit carry look ahead adder, behavioral description.
29. Develop a verilog model of a code converter to convert the 4 bit gray code to a 4 bit unsigned
binary integer, using data flow description.
30. Explain the operation of resizing unsigned integers.
31. Develop a verilog model of a code converter to convert the 4 bit gray code to a 4 bit unsigned
binary integer using behavioral description.
32. Write a verilog module declaration for a code converter that has an input representing an
unsigned number in the range 0 to 48 with a precision of at least 0.01 and an output
representing a signed number in the range-100 to 100 with a precision of at least .01

UNIT-4

33. Design a control sequence for the control signals of the sequential complex multiplier.
34. What is the main difference between a testbench for combinational circuit and a testbench for a
sequential circuit? Explain with an example
35. What is GALS? explain.
36. Design a circuit that counts 16 clock cycles and produces a control signal ctrl that is ‘1’ during
every eighth and twelfth cycle.
37. Explain the asynchronous timing methodologies.
38. Develop a verilog model of debouncer for a push-button switch that uses a debounce interval of
10ms. Assume the system clock frequency is 50MHz.
39. Describe the operation of latch with timing diagram and verilog model.
40. Design a circuit for a modulo 10 counter know as decade counter. Also develop a verilog model
for same.
41. Design a circuit for a modulo 6 counter . Also develop a verilog model for same.
42. Describe finite state machines(FSM) with schematic representation..

UNIT 5
43. Design a 1Gx8 bit memory using four 256Mx4bit memory components.
44. Develop a verilog model a dual port 4k x 16 bit flow through SSRAM. One port allows data to be
written and read, while the other port only allows data to be read.
45. Determine whether there is an error in the ECC word 000111000100 and if so correct it.
46. Explain the types of memory in detail.
47. Explain the field programmable gate arrays, in brief
48. Explain flow through SSRAM and pipelined SSRAM with verilog models.
49. Determine whether there is an Error in ECC word 101111000101, and if so correct it.
50. What is field programmable gate arrays FPGAs? With a diagram explain the internal organization
of an FPGA.

UNIT 6
51. What is the benefit of allowing PLD in a system to be reprogrammed? Explain.
52. What distinguishes a platform FPGA from a simple FPGA? Explain in brief.
53. Write a gumnut assembly language program to find the greater of two values.
54. Write a gumnut assembly language program to find least of two number
55. Write a gumnut assembly language to sort numbers in ascending order.
56. What are the different techniques that enable a higher rate of data transfer or memory
bandwidth?
57. Mention the different types of gumnut instruction sets. Describe any five.
58. Explain with block diagram, the organization of high performance embedded computer with
multiple busses.
59. What is meant by the term little endian and big endian memory layout for data words
60. Suppose the value in data memory location 100 represents the number of seconds elapsed in a
time interval. Write instruction to increment the value, wrapping around to 0 when the value
increments above 59.
61. Explain cache memory in processor. What are the advanced techniques use to enable a higher
rate of transfer or memory bandwidth.

Unit 7
62. Briefly explain the serial interface standards for I/O devices.
63. With a neat diagram, explain the architecture for sobel accelerator datapath.
64. What are the serial interface standards? briefly explain any four.
65. Explain the mechanism for input/output controllers to request an interrupt.
66. Show how a 64 bit data word can be transmitted serially between two parts of system. Assume
that the transmitter and the receiver are both within the same clock domain, and that the signal
start is set to 1 on a clock cycle in which data is to be transmitted.
67. Design an input controller that has 8 bit binary codded input from a sensor. The value can be
read from an 8 bit input register. The controller should interrupt the embedded GUMNUT core
when the input value changes. The controller is the only interrupt source in the system.
68. Develop verilog model for the GUMNUT controller.
69. With a neat diagram explain the R/2R ladder in DAC.
70. Discuss the three basic ways to synchronize transmitter and receiver in serial transmission.
Unit 8
71. Describe the three properties of design such as area, timing, and power for design optimization
72. Describe the Built in self test(BIST) technique used in design for test.
73. Briefly explain the design optimization.
74. Why BIST usefull after manufacturing test of a system.
75. Explain 4 bit LFSR, width block diagram.
76. Differentiate between the physical design of ASIC’s and FPGA’s
77. Develop a verilog RTL code to describe the address generator of FIG.

Input signals [Top –to-Bottom]: dat –I, O- base –ce, o-offset –cnt –en, D-base-ce, D-offset-cnt-
en, offset –reset, Clk.
78. Briefly describe the purpose of floor planning placement and routing.
79. With a neat circuit diagram, explain 4 bit LFSRs and 4 bit GFSR and their purpose.