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This document tracks the progress of multiple VIP team members on various tasks for an APB interface. It shows their completion percentages on items like interface coding, testbench development, test case implementation, and regression. Overall completion ranges from 53% to 73% across team members. Notes provide guidance that initial tasks should be split 50%-50% between coding and compilation, while later stages focus more on verification and ensuring correct behavior.
This document tracks the progress of multiple VIP team members on various tasks for an APB interface. It shows their completion percentages on items like interface coding, testbench development, test case implementation, and regression. Overall completion ranges from 53% to 73% across team members. Notes provide guidance that initial tasks should be split 50%-50% between coding and compilation, while later stages focus more on verification and ensuring correct behavior.
This document tracks the progress of multiple VIP team members on various tasks for an APB interface. It shows their completion percentages on items like interface coding, testbench development, test case implementation, and regression. Overall completion ranges from 53% to 73% across team members. Notes provide guidance that initial tasks should be split 50%-50% between coding and compilation, while later stages focus more on verification and ensuring correct behavior.
12 Scoreboard 12 Regression Current status 53.84615385 53.846154 72.735043 72.735043 65.641026
Note: Progress tracking
1 Coded 20% 2 Compiled 20% 3 Running 30% 4 Working 30% 5 For initial stages which contain only coding and compilation keep 50% each for the item 6 Working means you have observed the waveforms logs and are sure that all the behaviour is correct. Comments Interface coded and compiled Transaction coded and compiled Config coded and compiled
Tb_TOP coded and compiled, connect DUT
UVM skeleton coded and compiled
TB_TOP_skeleton coded and compiled
test case coded and compiled, Print trans in driver
Driver implementation coded and compiled,
Must see that driver read and write are working fine
Monitor Implementation coded and compiled,
Monitor packets must be printed in dummy scoreboard
Functional coverage coded and compiled, At
least one bin should be hitting from each test.
test case coded and compiled, 100% coverage
Data checking Regression coded and compiled
h for the item
ll the behaviour is correct. SN Testcase Code Asif Pujitha Sahana Santosh 1 Single read TC1 100 100 2 Single Write TC2 100 100 3 Write followed by read TC3 100 100 4 Random no of writes read TC4 70 70 5 Transaction outside address range TC5 6 Perr test TC6 7 Pready test TC7 8 disable-penable test TC8 20 20 9 disable-psel test TC9 20 20 Status 0 0 45.555556 45.5555556
Note: Progress tracking
1 Coded 20% 2 Compiled 20% 3 Running 30% 4 Working 30% 5 For initial stages which contain only coding and compilation keep 50% each for the item 6 Working means you have observed the waveforms logs and are sure that all the behaviour is correct. Srinath Comments 100 100 100 Write and read to random addresses