entity and2 is

port(a,b : in bit;
s: inout bit);
end and2;
architecture andarch of and2 is
begin
s <= a and b after 10 ps;
end andarch;

entity or2 is
port(a,b: in bit;
s : inout bit);
end or2;
architecture orarch of or2 is
begin
s <= a or b after 10 ps;
end orarch;

entity nand2 is
port(a:in bit;
anot : inout bit);
end nand2;
architecture nandarch of nand2 is
begin
anot <= a nand a after 10 ps;
end nandarch;

entity multiplexer is
port(a,b,s : in bit;
z : inout bit);
end multiplexer;
architecture muxarch of multiplexer is
component and2
port(a,b: in bit;
s : inout bit);
end component;
component or2
port(a,b : in bit;
s : inout bit);
end component;
component nand2
port(a : in bit;
anot : inout bit);
end component;
signal as,bns,ns : bit;
begin
a1 : and2
port map(a,s,as);
n1 : nand2
port map(s,ns);
a2 : and2
port map(b,ns,bns);
o1 : or2
port map(as,bns,z);
end muxarch;