Design For Test by Alfred L Crouch

Figures to Accompany
Design-for-Test
for Digital IC’s and
Embedded Core Systems
Alfred L. Crouch
© 1999 Prentice Hall, All Rights Reserved

Contents ii
Chapter 1 Test and Design-for-Test Fundamentals

Figure 1-1 Cost of Product
Figure 1-2 Concurrent Test Engineering
Figure 1-3 Why Test?
Figure 1-4 Definition of Testing
Figure 1-5 Measurement Criteria
Figure 1-6 Fault Modeling
Figure 1-7 Types of Testing
Figure 1-8 Manufacturing Test Load Board
Figure 1-9 Using ATE
Figure 1-10 Pin Timing
Figure 1-11 Test Program Components
Chapter 2 Automatic Test Pattern Generation Fundamentals

Figure 2-1 The Overall Pattern Generation Process
Figure 2-2 Why ATPG?
Figure 2-3 The ATPG Process
Figure 2-4 Combinational Stuck-At Fault
Figure 2-5 The Delay Fault
Figure 2-6 The Current Fault
Figure 2-7 Stuck-At Fault Effective Circuit
Figure 2-8 Fault Masking
Figure 2-9 Fault Equivalence Example
Figure 2-10 Stuck-At Fault ATPG
Figure 2-11 Transition Delay Fault ATPG
Figure 2-12 Path Delay Fault ATPG
Figure 2-13 Current Fault ATPG
Figure 2-14 Two-Time-Frame ATPG
Figure 2-15 Fault Simulation example
Figure 2-16 Vector Compression and Compaction
Figure 2-17 Some Example Design Rules for ATPG Support
Figure 2-18 ATPG Measurables
Chapter 3 Scan Architectures and Techniques

Figure 3-1 Introduction to Scan-based Testing
Figure 3-2 An Example Non-Scan Circuit
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch
Contents iii
Figure 3-3 Scan Effective Circuit

Figure 3-4 Flip-Flop versus Scan Flip-Flop
Figure 3-5 Example Set-Scan Flip-Flops
Figure 3-6 An Example Scan Circuit with a Scan Chain
Figure 3-7 Scan Element Operations
Figure 3-8 Example Scan Test Sequencing
Figure 3-9 Example Scan Testing Timing
Figure 3-10 Safe Scan Shifting
Figure 3-11 Safe Scan Vectors
Figure 3-12 Partial Scan
Figure 3-13 Multiple Scan Chains
Figure 3-14 The Borrowed Scan Interface
Figure 3-15 Clocking and Scan
Figure 3-16 Scan-Based Design Rules
Figure 3-17 DC Scan Insertion
Figure 3-18 Stuck-At Scan Diagnostics
Figure 3-19 At-Speed Scan Goals
Figure 3-20 At-Speed Scan Testing
Figure 3-21 At-Speed Scan Architecture
Figure 3-22 At-Speed Scan Interface
Figure 3-23 Multiple Scan and Timing Domains
Figure 3-24 Clock Skew and Scan Insertion
Figure 3-25 Scan Insertion for At-Speed Scan
Figure 3-26 Critical Paths for At-Speed Testing
Figure 3-27 Logic BIST
Figure 3-28 Scan Test Fundamentals Summary
Chapter 4 Memory Test Architectures and Techniques

Figure 4-1 Introduction to Memory Testing
Figure 4-2 Memory Types
Figure 4-3 Simple Memory Organization
Figure 4-4 Memory Design Concerns
Figure 4-5 Memory Integration Concerns
Figure 4-6 Embedded Memory Test Methods
Figure 4-7 Simple Memory Model
Figure 4-8 Bit-Cell and Array Stuck-At Faults
Contents iv
Figure 4-9 Array Bridging Faults

Figure 4-10 Decode Faults
Figure 4-11 Data Retention Faults
Figure 4-12 Memory Bit Mapping
Figure 4-13 Algorithmic Test Generation
Figure 4-14 Scan Boundaries
Figure 4-15 Memory Modeling
Figure 4-16 Black Box Boundaries
Figure 4-17 Memory Transparency
Figure 4-18 The Fake Word Technique
Figure 4-19 Memory Test Needs
Figure 4-20 Memory BIST Requirements
Figure 4-21 An Example Memory BIST
Figure 4-22 MBIST Integration Issues
Figure 4-23 MBIST Default Values
Figure 4-24 Banked Operation
Figure 4-25 LFSR-Based Memory BIST
Figure 4-26 Shift-Based Memory BIST
Figure 4-27 ROM BIST
Figure 4-28 Memory Test Summary
Chapter 5 Embedded Core Test Fundamentals

Figure 5-1 Introduction to Embedded Core Test and Test Integration
Figure 5-2 What is a CORE?
Figure 5-3 Chip Designed with Core
Figure 5-4 Reuse Core Deliverables
Figure 5-5 Core DFT Issues
Figure 5-6 Core Development DFT Considerations
Figure 5-7 DFT Core Interface Considerations
Figure 5-8 DFT Core Interface Concerns
Figure 5-10 Registered Isolation Test Wrapper
Figure 5-11 Slice Isolation Test Wrapper
Figure 5-12 Slice Isolation Test Wrapper Cell
Figure 5-13 Core DFT Connections through the Test Wrapper
Figure 5-14 Core DFT Connections with Test Mode Gating
Contents v
Figure 5-15 Other Core Interface Signal Concerns

Figure 5-16 DFT Core Interface Frequency Considerations
Figure 5-17 A Reuse Embedded Core’s DFT Features
Figure 5-18 Core Test Economics
Figure 5-19 Chip with Core Test Architecture
Figure 5-20 Isolated Scan-Based Core-Testing
Figure 5-21 Scan Testing the Non-Core Logic
Figure 5-23 Memory Testing the Device
Figure 5-24 DFT Integration Architecture
Figure 5-26 Selecting or Receiving a Core
Figure 5-27 Embedded Core DFT Summary
Chapter 1 Test and Design-for-Test Fundamentals 1
Chapter 1 Test and Design-for-Test Fundamentals
Total
Cost
Testing
Cost
Packaging
Cost
Silicon
Cost Increasing
Initial Final Time
Product Product
The goal over time is to reduce the cost of manufacturing

the product by reducing the per-part recurring costs:
- reduction of silicon cost by increasing volume and yield,
and by die size reduction (process shrinks or more
efficient layout)
- reduction of packaging cost by increasing volume,
shifting to lower cost packages if possible (e.g., from
ceramic to plastic), or reduction in package pin count
- reduction in cost of test by:
- reducing the vector data size
- reducing the tester sequencing complexity
- reducing the cost of the tester
- reducing test time
- simplifying the test program
Figure 1-1 Cost of Product
Behavioral Specification and Model

Test Architecture Functional Architecture
Development Development
Test Control
Test Interface Hardware Description Language
BIST HDL Register Transfer Level
JTAG HDL Timing Constraints
Gate-Level Library Mapping

Scan Insertion Gate-Level Synthesis
Insert
Scan Cells
Gate-Level Netlist
Scan Signals
Static Timing Assessment
Scan Ports
Test Timing
Physical Process Mapping

Scan Optimization FloorPlanning and
Place&Route
Macrocell FloorPlanning
Algorithmic
Timing Driven Cell Placement
Scan Signal
Timing Driven Routing
ReOrdering
Clock Tree Synthesis
Figure 1-2 Concurrent Test Engineering
WHY TEST?
Reasons
Measurement Incoming
of Defects & Inspection
Quality Level Contractual
Perceived Reliability
Product Quality Requirement
by Customer Contractual
Pro & Con Perceptions of DFT
Eases Adds Complexity

Generation of to Design
Vectors Methodology
Eases Impacts
Diagnosis Design Power
& Debugging & Package Pins
Provides a Impacts
Deterministic Design Speed or
Quality Metric Performance
Reduces Adds to
the Cost Silicon
of Test Area
Figure 1-3 Why Test?
DEFINITION of TESTING
Device or Circuit
under test
A KNOWN
DEVICE A KNOWN
STIMULUS
IN A EXPECTED
KNOWN RESPONSE
STATE
EXAMPLE
IN_A a
D Q 0
IN_B b
OUT_1
1
IN_C CLK S
IN_D
D Q a
OUT_2
b
Broadside CLK
Parallel
Vector with an unknown state
1 1 1
1 ^ X ?
^ X 1
?
X
1 ^
1
Figure 1-4 Definition of Testing
Vdd
S physical defects
source-to-drain
short
opens
G
shorts
D D is always metal bridges
at a logic 1
S process errors
G
D transistor faults
Vss S2 D G2 D
S2 G G2 SB
S 2 SB D2 SB
+
gate faults
A a@ 0 a@ 1
b@ 0 b@ 1
c@ 0 c@ 1
observed truth table

B
A B C failures
0 0 1 0
0 1 1 0
1 1 0 1
1 0 1 0
Transistor and Gate Representation of Defects, Faults, and Failures

Figure 1-5 Measurement Criteria
defects transistor faults stuck faults

open/short s2 d g2 d a@ 0 a@ 1
bridge s2 g g 2 sb b@ 0 b@ 1
mask s 2 sb d 2 sb c@ 0 c@ 1
process
6 gate faults
transition
delay faults
+
a 1- 0 a 0- 1
s
a g b1- 0 b0- 1
d c 1- 0 c 0- 1
6 transitions
c
Truth Table
with fail modes
b
nand ab a b c
ab c 0 1 1 0
00 1 1 1 1 0
01 1 1 0 1 0
10 1 1 1 0 0
A 11 0 1 0 0 0
a
e r
s path
S delay faults
f t
A2SR A2SF
B b A2CR A2CF
c B2SR B2SF
C B2CR B2CF
1 BIT ADDER with CARRY path
R=Slow-to-Rise
Figure 1-6 Fault Modeling F=Slow-to-Fall
Functional
4 4
3 a / / s 8
A
D
D
E
4 R 4
5 b / / c 0
3+5=8
Structural
A faultlist
a
a@ 0 a@ 1
r
e b@ 0 b@ 1
s S e@ 0 e@ 1
f
t f@ 0 f@ 1
r@ 0 r@ 1
B b
t@ 0 t@ 1
c s@ 0 s@ 1
C c@ 0 c@ 1
1 BIT ADDER with CARRY 16 faults
Figure 1-7 Types of Testing
Chip
under
Test
The chip will be accessed by the tester at its pins only
A custom (load) board will be made for this purpose
Each pin has a limited number of bits available (e.g., 2 MB)
The test program (set of vectors and tester control) will be

applied at tester speed (may be less than actual chip speed)
The primary goal of manufacturing test is structural verification
Figure 1-8 Manufacturing Test Load Board
2 Meg Clock Gen 1

Memory Clock Gen 2
Depth
Clock Gen 3
192
Channels
et
ock
pS
hi
C
Loadboard
Power Supply 1
Power Supply 2
Power Supply 3
Figure 1-9 Using ATE
Chip Point of View
1 2 3 DV 4
1. Input Setup Time: time the signal must arrive

and be stable before the clock
edge to ensure capture
2. Input Hold Time: time the signal must remain

stable after the clock edge
to ensure that capture is stable
3. Output Valid Time: time the signal takes to be

valid (or tristated) and stable on
the output after the clock edge
4. Output Hold Time: time that the signal remains

available after output valid
so that it can be used
Tester Point of View
CLK
NRZ 1 0 0
RZ 1 0 0
SBC 1 0 0
Figure 1-10 Pin Timing
DC Pin Parametrics
Test Logic Verification
DC Logic Stuck-At
DC Logic Retention
AC Logic Delay
AC Frequency Assessment
AC Pin Specification
Memory Testing
Memory Retention
Idd and Iddq
Specialty Vectors
Analog Functions
Test Escapes
Scan Scan
Path Delay Sequential
The Venn circles are
examples of DC fault
coverages of some of the
vector classifications
in the test program
Scan
Some of the fault Transition
coverages overlap Delay Scan
Stuck-At Parametric
Vector reduction can
be accomplished by
removing overlap or Functional
by combining vector Test Escapes
sets
Chapter 2 Automatic Test Pattern Generation Fundamentals 1
Chapter 2 Automatic Test Pattern Generation Fundamentals
Library Support
Netlist Conditioning
Observe Point Assessment
Vector Generation/Simulation
Vector Compression
Vector Writing
Figure 2-1 The Overall Pattern Generation Process
WHY ATPG?
Reasons
Greater Reduction
Measurement in Cycle
Ability Time
Perceived More
Competitive Efficient
Methodology Vectors
Pro & Con Perceptions of ATPG

Good Bad
Eases Adds Complexity
Generation of to Design
Vectors Methodology
Eases Requires
Diagnosis Design-for-Test
& Debugging Analysis
Provides a Requires
Deterministic Library
Quality Metric Support
Reduces Requires
the Cost Tool
of Test Support
Figure 2-2 Why ATPG?
Fault Selection
Fault Observe Point Assessment
Fault Excitation
Vector Generation
Fault Simulation
Fault Dropping
Figure 2-3 The ATPG Process
X
b
stuck-at-0 e
force to a 1
detected
c good = faulty
1 1
0 1 0
1
0 0 0
D
0 0 I
F
GOOD CIRCUIT F
E
R
E
1 1 N
T
0 0 1
0
0 0 0
0 0
FAULTY CIRCUIT
Figure 2-4 Combinational Stuck-At Fault
Delay from Strong Driver

Insufficient Transistor Doping
A Delay Model Element
B
Resistive Bridge
Z
C
Delay from Extra Load
D
Slow Gate Output
Slow Gate Input

E
F Capacitive or Resistive
Wire Delay from Opens
and Metal Defects
The Delay Fault Model

is an added delay
to net, nodes, wires, gates
and other circuit elements
Effect of Delay Fault

Delay of Transition Occurrence
Changing of Edge-Rate
Edge-Rate Layover
“Ideal” Signal
1
0 0
Added Rise Delay Added Fall Delay
Figure 2-5 The Delay Fault
Leakage from Bridge

Leakage from Metastability
A Leakage Fault Model
B
Resistive Bridge
Z
C
Leakage from Bridge
D
Internal Gate Leakage

E
F Capacitive or Resistive
Delay Extends Current
Flow Time
The Current Fault Model

is an added Leakage Effect of a Current Fault
is to add extra current
to net, nodes, wires, gates flow or to extend flow time
and other circuit elements
I(t)
Figure 2-6 The Current Fault
a
nand
X ab z
b
stuck-at-0 e 00 1
force to a 1
01 1
c 10 1
11 0
evaluate fault against
d the gate’s truth table
R
E
M
A
1 P
nor
ab z
c 00 1
e 01 0
10 0
d evaluate change against 11 0
the gate’s truth table
R
E
M
A
P
0 e Detectable
evaluate final result against
the circuit’s whole truth table
Figure 2-7 Stuck-At Fault Effective Circuit
stuck-at-0
force to a 1
a
X
b
e
not detected
good = faulty
1 1
0 1 0
0
X 0 1
X
S
GOOD CIRCUIT A
M
E
1 0
0 1 1
0
X 1 1
X
FAULTY CIRCUIT
Figure 2-8 Fault Masking
A faultlist
a
a@ 0 a@ 1
e r b@ 0 b@ 1
r s S
f e@ 0 e@ 1
t f@ 0 f@ 1
t r@ 0 r@ 1
B b
a’ t@ 0 t@ 1
c s@ 0 s@ 1
C
e c@ 0 c@ 1
GOOD - 1 BIT ADDER with CARRY
16 faults
1. Any fault that

a requires a logic 1 on
z the output of an
b AND-gate will also
a place 1’s on inputs
z
a 2. Similar analysis
z exists for all other
b gate-level elements
Fault Equivalence Table 3. If one fault is

detected, all
equivalent faults are
AND a@0 = b@0 = z@0 detected
INV a@1 = z@0 : a@0 = z@1 4. Fault selection only

needs to target one
of the equivalent
OR a@1 = b@1 = z@1 faults
Figure 2-9 Fault Equivalence Example
A 1 faultlist
a a@ 0 a@ 1
1
1 b@ 0 b@ 1
eX
r
1 s e@ 0 e@ 1
1 1 S f@ 0 f@ 1
0
f r@ 0 r@ 1
0 0 t
t@ 0 t@ 1
B b s@ 0 s@ 1
c@ 0 c@ 1
c 16 faults
C
1 BIT ADDER with CARRY

Set Up the Detect and Propagation Path 1. Set up the path to
pass the opposite of
e S @ 0, which is e = 1
2. Exercise by setting
e equal to1
A 3. Detect by observing
a
S for wrong value
1 r during fault
e
s simulation
S
f
t
B 0 b
c
C

Exercise the Fault
Figure 2-10 Stuck-At Fault ATPG
A 1 faultlist
a 1 a@ 0 a@ 1
1
eX r
1
b@ 0 b@ 1
1 s 1 S e@ 0 e@ 1
f 0 0
0 t f@ 0 f@ 1
r@ 0 r@ 1
B b t@ 0 t@ 1
c s@ 0 s@ 1
C c@ 0 c@ 1
1 BIT ADDER with CARRY 16 faults
Set Up the Detect Path to Pass a 1
A
a
0 1. Set up the path to
e 0 r pass the opposite of e
0 s 0 S=0 S @ 0, which is e = 1
f t S@Time 1 2. Pre-fail by setting
b e equal to 0
B 1
c 3. Exercise by setting
C e equal to 1 some
1 BIT ADDER with CARRY time period later
Pre-Fail the Fault by Passing a 0
4. Detect by observing
A S for wrong value
a during timing
1
e 1 r simulation
1 s 1 S=1
f t The Transition Delay
S@Time 2
Faultlist is identical to
B 0 b the Stuck-At Faultlist but
the goal is to detect a
c Logic Transition within
C a given time period
Exercise the Fault to Pass a 1
Figure 2-11 Transition Delay Fault
1->1 faultlist
A
a a@ 0 a@ 1
1->1
X r b@ 0 b@ 1
eX e@ 0 e@ 1
X s
0->0 X S f@ 0 f@ 1
f r@ 0 r@ 1
0 t
0 t@ 0 t@ 1
x
B X x->x b s@ 0 s@ 1
16.0 pt c@ 0 c@ 1
c 16 faults
C
1. Set up the path to pass
1 BIT ADDER with CARRY a transition on B-to-S
Set Up the Off-Path through e, r, and s by
setting the off-path
values to be stable for
2 time periods
A 2. Exercise by first setting

a B equal to 1 and then
1->0 to 0. This is known as a
0->1 r
e vector-pair
s
0->1
0->1 S@Time1 -> S@Time2
f
t
1. Detect by observing S
B b for wrong value during
1->0 fault simulation with
c respect to a time
C standard

Exercise the Fault (Path)
Figure 2-12 Path Delay Fault
faultlist
a@ 0 a@ 1
b@ 0 b@ 1
e@ 0 e@ 1
f@ 0 f@ 1
r@ 0 r@ 1
t@ 0 t@ 1
s@ 0 s@ 1
c@ 0 c@ 1
16 faults
1. Exercise by first
A setting e equal to1
a
1 r
e
s
S
f
t 2. Detect by measuring
current and accept
B 0 b vector by quietness
c
C

Exercise the Fault
Figure 2-13 Current Fault
Transition End of Path

bit bit
Gate
Elements
Q Defined D Expect
1 1->0 Critical Value
Path
second-order
cone of logic
0 1->1
establishes first-order
transition and combinational
0 off-path values 0->0 cone of logic
establishes contains path
the legal and off-path
1 next-state 1->1 logic
preset establish legal legal

next-state first state next-state next-next-state
Solve This Combinational Solve This Combinational

Cone of Logic As Second Step Cone of Logic As the First Step
after Middle Register Values to Combinational Multiple
Are Established by First Cone Time Frame Analysis
Slack Time
Propagation Delay Time
Register Setup Time
1 2 3
1. Launch 1st Value: establish path fail value at clock edge
2. Launch Transition: provide pass value at next clock edge
3. Capture Transition: observe transition value at this clock edge
Figure 2-14 Two-Time-Frame ATPG
A faultlist
a
a@ 0 a@ 1
e r b@ 0 b@ 1
s S
f e@ 0 e@ 1
t f@ 0 f@ 1
B b r@ 0 r@ 1
t@ 0 t@ 1
c s@ 0 s@ 1
C
c@ 0 c@ 1
GOOD - 1 BIT ADDER with CARRY
16 faults
A 1. Create multiple
a
copies of the netlist
e r for each fault.
s S
f t 2. Apply same
vectors to each
B b GND copy.
c 3. Compare each
C
copy to good
“t” S@0 - 1 BIT ADDER with CARRY simulation
(expected
response).
A
a 4. Fault is detected if
e r bad circuit and
s S good circuit differ
f t at a detect point.
B b VDD 5. Measurement is
+ faults detected
c divided by total
C
number of faults
“t” S@1 - 1 BIT ADDER with CARRY (8/16 = 50%).
Figure 2-15 Fault Simulation example
Simulation Post Processing Compression
Pattern Set Fault Re-Simulation

with Redundant
01101110001010 Vector Dropping
01101110101110
00101110111010
11111110001010 This Usually Drops
01100000001011 Early Vectors That
01001011001010 Are Fully Covered
01010101010101 by Later Vectors
11101100101010
11001110001010
01111000001010 and Eliminates Less
00000000001010 Efficient Vectors
X Dynamic ATPG Compression
X
1
0 During ATPG a Vector Is Not
Submitted to Fault Simulation
1 X until Multiple Faults have
one targeted been Targeted — “X”s Mapped
0 fault
X This can Greatly Increase
X Vector Generation Time
X But Usually Results in

X the Most Efficient Vectors
Figure 2-16 Vector Compression and Compaction
Transistor
Structure
Equivalent
Gate
Structure
ATPG May Only Operate

on Gate-level Elements
Combinational Feedback Results in

Latches, Oscillators, or Endless Loops
Propagation Timing Distance Must Be Less

Than One Test Clock Cycle
SET General CLR
D Q Combinational D Q
Logic
CLK CLK
Figure 2-17 Some Example Design Rules for ATPG
Sizing Complexity
Design ATPG
Description Library
Faultlist
Management Runscripts
Support
Files ATPG
TOOL Runtime
algorithms
rule checks
Vectors
Vector Features Detected

Compression Faults
Vector
Translation
Figure 2-18 ATPG Measurables
Chapter 3 Scan Architectures and Techniques 1
Chapter 3 Scan Architectures and Techniques
- >1,000,000 gates
- >5,000,000 faults
- >10,000 flip-flops
- > 1,000 sequential depth
- < 500 chip pins
* > 2,000 gates/pin
* > 2M = 21000
A deep sequential circuit
Chip under Test without Scan
- >1,000,000 gates
- >5,000,000 faults
- > no effective flip-flops
- > no sequential depth
- < 500 + 10,000 chip pins
* > 95.23 gates/pin
* > 2M = 20 = 1
A combinational circuit
Chip under Test with Full-Scan
Figure 3-1 Introduction to Scan-based Testing
Combinational &
Sequential Logic
input1
input2 output1
input3
D Q
input4
QN
D Q
clk
input5
D Q output2
D Q
input6
1 2 34
Sequential Depth of 4
Combinational Width of 6
26+4 = 1024 Vectors
Figure 3-2 An Example Non-Scan Circuit
Combinational-Only Logic
input1
input2 output1
input3
D Q
input4
QN
D Q
input5
D D Q output2
Q
input6
TPI1
TPI2 TPO1
TPI3 TPO2
TPI4 TPO3
TPI5 TPO4
A no-clock, combinational-only circuit with:
6 inputs plus 5 pseudo-inputs and
2 outputs plus 4 pseudo-outputs
Figure 3-3 Scan Effective Circuit
D D Q Q
QN
CLK clk
Regular D Flip-Flop
SDO
D
D Q Q
SDI
SDO
SE clk QN
CLK
Scannable D Flip-Flop
Figure 3-4 Flip-Flop versus Scan Flip-Flop
SET
SDO
D
D Q Q
SDI
QN
SE
clk
CLK
Set-Scan D Flip-Flop
with Set at Higher Priority
D SDO
SET D Q Q
SDI
QN
SE clk
CLK
Set-Scan D Flip-Flop
with Scan-Shift at Higher Priority
Figure 3-5 Example Set-Scan Flip-Flops
Combinational and
Sequential Logic
input1
input2 output1
input3
D Q
input4
SE SE
QN
scanin SDI
SDO D Q
clk
SE
input5 SDI
SDO scanout
D Q D Q output2
input6
SE SE
SDI SDI
SDO
SDO
1 0 1 1
4-Bit Scan Vector
Figure 3-6 An Example Scan Circuit with a Scan Chain
D a
D Q Q
SDI b
QN
SE clk SDO
CLK
Scannable D Flip-Flop
The scan cell provides observability and controllability of the signal

path by conducting the four transfer functions of a scan element.
Operate: D to Q through port a of the input multiplexer:

allows normal transparent operation of the element.
Scan Sample: D to SDO through port a of the input multiplexer:

gives observability of logic that fans into the scan element.
Scan Load/Shift: SDI to SDO through the b port of the multiplexer:

used to serially load/shift data into the scan chain while simultaneously
unloading the last sample.
Scan Data Apply: SDI to Q through the b port of the multiplexer:

allows the scan element to control the value of the output, thereby
controlling the logic driven by Q.
Figure 3-7 Scan Element Operations
From normal operation:

D
D Q Q
SDI While the clock is low,
QN
apply test data to SDI
SE=0 clk SDO and Place SE = 1
CLK
At the rising edge of the clock,
Functional Operation Mode test data will be loaded
D Apply clocks for scan length

D Q Q
SDI QN When chain is loaded, the last
SE=1 shift clock will apply scan data
clk SDO
CLK While the clock is low,

place SE = 0
Scan Shift Load/Unload Mode
Normal circuit response will be

D applied to D
D Q Q
SDI
QN The next rising edge of the clock
SE=1 will sample D
clk SDO
CLK Return to Load/Shift mode to

unload circuit response sample
Scan Apply Mode (Last Shift)
NOTE: unloading is simultaneous

D with loading the next test
D Q Q
SDI Repeat operations until all vectors
QN
have been applied
SE=0 clk SDO
CLK NOTE: the chip’s primary inputs

must be applied during the scan
Scan Sample Mode apply mode (after the last shift)
Figure 3-8 Example Scan Test Sequencing
The Scan Sample
The Last Shift In The First Shift Out
CLK
SE
Scan Enable De-assert Scan Enable Assert
The Output Pin Strobe
SHIFT SHIFT FAULT SAMPLE SHIFT SHIFT

DATA DATA EXERCISE DATA DATA DATA
Faults Exercised Interval
Figure 3-9 Example Scan Testing Timing
Gated Clock Nets clock tree

distribution
Provide an Enable Signal
f_seB
force the clock on
Asynchronous or Synchronous
Signals with Higher Priority
than Scan—or Non-Scan Elements
D Q D Q
HOLD HOLD
SET SET
CLR CLR
f_seB
CLK Provide a Blocking Signal CLK
Driven Contention
During Scan Shifting
D Q Q D
CLK CLK
D Q Q D
CLK CLK
t_seB
Provide a Forced Mutual Exclusivity
Figure 3-10 Safe Scan Shifting
The Scan Sample
The Last Shift In The First Shift Out
CLK
Faults Exercised Interval
SE
t_seB
a tristate scan enable may be
a separate signal that has
slightly different timing than
the flip-flop SE
Driven Contention
during the Capture Cycle
D Q Q D
CLK CLK
D Q Q D
CLK CLK
t_seB
de-asserted
Figure 3-11 Safe Scan Vectors
Combinational-Only Logic
input1
input2 output1
input3
D Q
input4
QN
D Q
input5
D D Q output2
Q
input6
TPI1
TPI2 TPO1
TPI3
TPO3
TPI5 TPO4
A clocked, sequential circuit with depth=1:
6 inputs plus 4 pseudo-inputs and
2 outputs plus 3 pseudo-outputs
Figure 3-12 Partial Scan
An Example Using a Chip with 1000 Scan Bits and 5 Scan Vectors
Red Space Is Wasted Tester Memory
1000 1000 Vector Data 1000 1000 One Channel

One Long
Scan Chain X’s on all Other Channels
not actively used for parallel pin data
Each Vector is 1000 Bits Long

So 5 Vectors Are 5000 Bits of Tester Memory
120 X 120 X Vector Data 120 X 120 X

80 XXX 80 XXX Vector Data 80 XXX 80 XXX
Many 100 XX 100 XX Vector Data 100 XX 100 XX
Variable Length 110 XX 110 XX Vector Data 110 XX 110 XX 10 Non-Balanced
Scan Chains
90 XXX 90 XXX Vector Data 90 XXX 90 XXX Channels
180 180 Vector Data 180 180
X20 XXXX X20 XXXX Vector Data X 20 XXXX X 20 XXXX
100 XX 100 XX Vector Data 100 XX 100 XX
Each Vector Is 180 Bits Long—So 900 Bits of Tester Memory

Differences from Longest Chain (180) Are Full of X’s—Wasted Memory
100 100 Vector Data 100 100

100 100 Vector Data 100 100
Many 100 100 Vector Data 100 100
Balanced 100 100 Vector Data 100 100 10 Balanced
100 100 Vector Data 100 100 Channels
Scan Chains 100 100 Vector Data 100 100
100 100 Vector Data 100 100
100 100 Vector Data 100 100
100 100 Vector Data 100 100
Vector Data
100 100 100 100
Each Vector Is 100 Bits Long—So 500 Bits of Tester Memory
No Wasted Memory Space
Figure 3-13 Multiple Scan Chains
Borrowed DC Scan Input on Bidirectional Pin
Combinational Output Data Path

Logic Blocked during Scan Shift
Output Enable
Captures through the with bus_se
Combinational Logic or scan_mode
Scan during the Sample Operation
Data
Input
Combinational Parallel Scan
Any D
Bidir Logic Input to Chip
Functional S Q Normal Input
Pin SE to Logic
Input
Pad Captures Directly from
the Input Pin During
the Shift Operation SE
Input Scan Interface—May Resolve to Functional during Sample Interval
Borrowed DC Scan Output on Bidirectional Pin

Last Scan Shift Bit Input Data Path Is a
D Don’t Care
from Scan Chain
Q during Scan Shift
S SE on Input
SE Combinational
Input Blocks Data
Normal Output Logic
from Logic
Scan
D Combinational Data
Output
S Q Logic a
SE Any
Output Bidir
b Pin
s
Added Scan Output Mux with bus_se or scan_mode

Pad
Functional Output Enable with bus_se or scan_mode added
Output Scan Interface—May Resolve to Functional during Sample Interval

Figure 3-14 The Borrowed Scan Interface
• Scan Bypass Clocks

• Scan Testing an On-Chip Clock Source
Bypass Clocks
Analog Digital 1 Digital 2
VCO
Raw VCO Counters &

Clock Dividers
On-Chip Clock Generation Logic
Figure 3-15 Clocking and Scan
Driven Contention
during Scan Shifting
D Q Q D
CLK CLK
D Q Q D
CLK CLK
t_seB
Provide a Forced Mutual Exclusivity
Asynchronous or Synchronous
Signals with Higher Priority
than Scan—or Non-Scan Elements
D Q D Q
HOLD HOLD
SET SET
CLR CLR
f_seB
CLK Provide a Blocking Signal CLK
Gated Clock Nets
Provide a Blocking Signal
f_seB
Figure 3-16 Scan-Based Design Rules
Basic Netlist Scan Insertion

Element Substitution
Ports, Routing & Connection of SE
Ports, Routing & Connection of SDI-SDO
Extras
Tristate “Safe Shift” Logic
Asynchronous “Safe Shift” Logic
Gated-Clock “Safe Shift” Logic
Multiple Scan Chains
Scan-Bit Re-Ordering
Clock Considerations All Non-Sampling

Clock Domains
Inhibit Sample
Clock Pulse
Last Shift
Only One Clock Domain

All Scan Chains (Clocks) Shift Conducts a Sample Clock
Figure 3-17 DC Scan Insertion
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Scan Fail Data Presented at

Chip Interface Automatically
Implicates the Cone of Logic
at One Flip-Flop
Multiple Fails under the

Single Fault Assumption
1 Implicate Gates
Common to Both
0 Cones of Logic 0
0
1 1
0
Figure 3-18 Stuck-At Scan Diagnostics
Basic Purpose
• Frequency Assessment
• Pin Specifications
• Delay Fault Content
Cost Drivers
• No Functional Vectors
• Fewer Overall Vectors
• Deterministic Grade
Figure 3-19 At-Speed Scan Goals
The Transition Launch
The First Shift Out

The Last Shift In
The Transition Capture
CLK
Transition Generation Interval Faults Exercised Interval
SE
T_SE
F_SE
Bus_SE
Separate Scan Enables for Tristate Drivers,

Clock Forcing Functions, Logic Forcing
Functions, Scan Interface Forcing Functions,
and the Scan Multiplexor Control
Because the Different Elements Have

Different Timing Requirements
Figure 3-20 At-Speed Scan Testing
Borrowed Scan Input with Scan Head Register

Output Data Path Blocked during Scan Shift
Output Enable with bus_se
Any Combinational
Parallel Scan
Bidir Logic D Input to Chip
Pin
S Q Normal Input
SE to Logic
D Q Input
Pad Input
At-Speed Scan Interface—Resolves to Functional During Sample Interval
Driven Contention
During Scan Shifting
D Q Q D
CLK CLK
D Q Q D
CLK CLK
t_seB
At-Speed Assert and De-Assert
Asynchronous or Synchronous Signals

with Higher Priority than Scan
or Non-Scan Sequential Elements
D Q D Q
HOLD HOLD
SET SET
CLR CLR
f_seB
CLK CLK
At-Speed Assert and De-Assert
Figure 3-21 At-Speed Scan Architecture
Borrowed AC Scan Input on Bidirectional Pin
Combinational Output Data Path

Logic Blocked during Scan Shift
Output Enable
with at-speed bus_se
Captures through the
Combinational Logic
Scan during the Sample Operation
Data
Input
Combinational Parallel Scan
Any D
Bidir Logic Input to Chip
Functional S Q Normal Input
Pin SE to Logic
Input
Pad D Q Captures Directly from
Input the Input Pin During
Head the Shift Operation
Input Scan Interface—Resolves to Functional during Sample Interval
Borrowed AC Scan Output on Bidirectional Pin

Last Scan Shift Bit Input Data Path Is a
D Don’t Care
from Scan Chain
Q during Scan Shift
S SE on Input
SE Combinational
Input Blocks Data
Normal Output Logic
from Logic
Scan
D Combinational Data
Output
S Q Logic a
SE Any
Output Bidir
D Q b Pin
Output s
Tail
Added Scan Output Mux with bus_se Pad
Functional Output Enable with bus_se Added
Output Scan Interface—Resolves to Functional During Sample Interval

Figure 3-22 At-Speed Scan Interface
Fast to Slow Slow to Fast

Transfers Transfers
Fast Slow
Logic Logic
Fast to Slow
Transfers
Fast Scannable Slow Scannable

System Registers System Registers
Clock A Clock B
Scan Enable A Scan Enable B
The Clock Domains and Logic Timing

should be crafted so that the very next
rising edge after the launch or last shift
is the legal capture edge
Last Scan Legal ATPG Illegal ATPG

Shift Edge Transfer Transfer
Applied
Fast Clock
Applied
Slow Clock
Only Fast-to-Slow
Legal ATPG Transfer
Figure 3-23 Multiple Scan and Timing Domains
Combinational Combinational Combinational

Logic Logic Logic
scanned
flip-flop
D Q D Q D Q
SDI SDI SDI
165 ps
CLK 120 ps
SE 150 ps
First Clock Domain — All Elements on Same Clock Tree

300ps+
Cross Domain Combinational Combinational Combinational
Clock Skew Logic Logic Logic
scanned
flip-flop
D Q D Q D Q
SDI SDI SDI
165 ps
CLK
120 ps
SE
150 ps
Second Clock Domain—All Elements on Same Clock Tree
Cross Domain Clock Skew must be managed to less than the fastest
flip-flop update time in the launching clock domain
If it is not, then the receiving flip-flop may receive new-new

scan data before the capture clock arrives
To prevent this outcome, constrain the ATPG tool to only

sample one clock domain at a time during the sample interval
Figure 3-24 Clock Skew and Scan Insertion
Specification
Development
Scan Mode
Bus_SE Simulation
Model Verification
Tristate_SE
Logic Force_SE
Architecture
Development Behavior
Synthesis
Scan Shift SE
Clock Force_SE Timing Specification
Scan Data Analysis Determination
Connection
Insertion
Gates
Place
and
Scan Chain Bit Route
Re-Ordering
Mask
Mask
Silicon
and
Test
Fab
Silicon
Design Flow Chart
Scan Mode: Fixed “Safe” Logic Scan Enable (SE): Scan Shift
Force_SE: Logic Forced States Force_SE: Clock Force States
Tristate_SE: Internal Tristates Bus_SE: Scan Interface Control
Figure 3-25 Scan Insertion for At-Speed Scan
Static Timing Analysis Provides Path Description

of Identified Critical Path from the Q-Output of R1
D Q 0>1 to the Device Output Pin—Out1
R1 A
U35
D Q B 0>1
R2 0 A
1>0
U37 A 1>0 Out1
In1 X B U38
A 1
U36 B
In2 1
B Isolated Combinational Logic
0
All Fan-in to Endpoint Is
Accounted at this Endpoint
In3 0 Fanout to other Endpoints is
A Evaluated atThose Endpoints
In4 U39
B
0
Period = 20ns : Output Strobe @ 15ns

Path Element Incremental Cumulative
Description Delay Delay
Clk 2.2ns Skew Amb.
R1.Q 0.0ns 0.0ns
U35.A 2.1ns 2.1ns
U35.Z 0.1ns 2.2ns
U37.A 3.2ns 5.4ns
U37.Z 0.2ns 5.6ns
U38.A 2.2ns 7.8ns
U38.Z 0.1ns 7.9ns
Out1 Dly=10.1 Slk=4.9ns
Timing Analysis Report
Figure 3-26 Critical Paths for At-Speed Testing
Polynomial: X3 + X +1 = X3 + X1 + X0 = 23 + 21 + 20 = 11
LFSR - PRPG: pseudo-random pattern generation

111
011
X3 X2 X1 X0 001
DQ DQ DQ 100
Seed 1 1 1 010
CLK 101
110
111
Chip with Full-Scan

and X-Management
DQ DQ DQ
CLK
LFSR - MISR: multiple input signature register
Figure 3-27 Logic BIST
Scan Testing Methodology

Advantages
Direct Observability of Internal Nodes
Direct Controllability of Internal Nodes
Enables Combinational ATPG
More Efficient Vectors
Higher Potential Fault Coverage
Deterministic Quality Metric
Efficient Diagnostic Capability
AC and DC Compliance
Concerns
Safe Shifting
Safe Sampling
Power Consumption
Clock Skew
Design Rule Impact on Budgets
Figure 3-28 Scan Test Fundamentals Summary
Chapter 4 Memory Test Architectures and Techniques 1
Chapter 4 Memory Test Architectures and Techniques
Chip-Level
Logic Embedded
Memory
Memory Access
PLL TAP
JTAG Boundary Scan
Figure 4-1 Introduction to Memory Testing
Row/Word-Address
Select Select
Column/Bit-Data Storage Column/Bit-Data
6 Transistor SRAM Cell
Row/Word-Address
Select
Storage
Column/Bit-Data
1 Transistor DRAM Cell
Row/Word-Address
Storage Select
Column/Bit-Data
2 Transistor EEPROM Cell
Figure 4-2 Memory Types
Data Bus: To Multiple Memory Arrays
Address Bus: To Multiple Memory Arrays
Bus
Enable
Data In Data Out

Memory: Data Width by Address Depth
32 x 512
Address In
Read/WriteBar Memory Array

Address Decode to Row Drivers
Data Decode to Column Drivers
Output Enable Control Circuitry to Read, Write,
and Data Output Enable
Control Signals: Individual Signals to This Memory Array
Figure 4-3 Simple Memory Organization
Chip FloorPlan
Memory 1
M
e
m Memory
o 2
r
y
- Aspect Ratio
3 - Access Time
- Power Dissipation
Memory 4
Figure 4-4 Memory Design Concerns
Chip FloorPlan
Memory 1
M
e
m Memory
o 2
r
y
- Routing
3 - Placement & Distribution
- Overall Power Dissipation
Processor
Local
Logic
Memory 4
Figure 4-5 Memory Integration Concerns
32
Data
Embedded 24 Embedded
Microprocessor Memory
Core Address Array
3
Control
Functional Memory Test
32
Data
24 Embedded
Address Memory
3 Array
Control
Direct Access Memory Test
BIST Controller
Invoke
Done
Reset Embedded
Memory Fail
Hold Array
BIST Memory Test
Figure 4-6 Embedded Memory Test Methods
column # —> 0 1 2 3
row # —> 0 1 0 0 1
row # —> 1 1 0 1 1
data bit cell
row # —> 2 0 1 0 1
Figure 4-7 Simple Memory Model
Data in Bit Cells
May Be Stuck-At
Logic 1 or Logic 0
word stuck-at
data value 1110 single bit stuck-at 1
address A031—> 1 0 1 1
address A032—>
1 1 1 0
address A033—>
1 0 1 0
single bit stuck-at 0
Figure 4-8 Bit-Cell and Array Stuck-At Faults
Data in Bit Cells
May Be Bridged
to Other Bit Cells
horizontal (row)
bit bridging
0 1 1 0
1 0 1 0
vertical (column)
bit bridging
1 1 1 0 random
bit bridging
0 0 1 1
word bridging
unidirectional 1 1 0 0
one-way short
word bridging
0 0 1 1 bidirectional
two-way short
1 1 0 0
Figure 4-9 Array Bridging Faults
Column Decode
C
X
O
X X
L
Select Lines
R
O
X W
0 1 1 1
Row Decode
stuck-at faults result R
1 0 1 1
in always choosing o
wrong address w
1 1 1 1
X
Row Decode D
bridging faults result e
in always selecting c
X
o 1 1 1 1
multiple addresses
d
e
Column Decode 0 1 1 1
bridging faults result
in always selecting
0 0 1 1
multiple data bits
Column Decode Select Line

stuck-at faults result faults result in
in always choosing similar array
wrong data bit fault effects
Figure 4-10 Decode Faults
Data around target
cell is written with
complement data
Complementary
Data around
Target Cell
Address 21 = A 1 0 1 0
Address 22 = 5 0 1 0 1
Address 23 = A 1 0 1 0
Address 24 = 5 0 1 0 1
alternating 5’s and A’s make for a natural checkerboard pattern
Figure 4-11 Data Retention Faults
Blue: Pass Column

Data Fault
Red: Fail
Physical Memory Organization
Row Address
Fault
Logical Memory Organization
Stuck-At
Bit Faults
Bridged
Cell Faults
Figure 4-12 Memory Bit Mapping
Addr(00) to Addr(Max) Address 00 —> 0 1 0 1 0 1 0 1

Write(5)-Initialize Address 01 —> 0 1 0 1 0 1 0 1
Increment Address
Address 02 —> 0 1 0 1 0 1 0 1
Read(5)-Write(A)-Read(A) Address 04 —> 0 1 0 1 0 1 0 1
Increment Address
Address 05 —> 0 1 0 1 0 1 0 1
Read(A)-Write(5)-Read(5) Address 07 —> 0 1 0 1 0 1 0 1
Increment Address
Address 08 —> 0 1 0 1 0 1 0 1
Addr(Max) to Addr(00) Address 09 —> 0 1 0 1 0 1 0 1
Read(5)-Write(A)-Read(A) Address 10 —> 0 1 0 1 0 1 0 1
Decrement Address
Address 11 —> 0 1 0 1 0 1 0 1
Read(A)-Write(5)-Read(5) Address 13 —> 0 1 0 1 0 1 0 1
Decrement Address
Address 14 —> 0 1 0 1 0 1 0 1
Read(5) Address 16 —> 0 1 0 1 0 1 0 1
Decrement Address
Address 17 —> 0 1 0 1 0 1 0 1
Read (A)-------> Address 18 —> 1 0 1 0 1 0 1 0
Write (5)
Read (5) Address 19 —> 1 0 1 0 1 0 1 0
Increment Address Address 20 —> 1 0 1 0 1 0 1 0
March C+ Algorithm Address 21 —> 1 0 1 0 1 0 1 0
Address 22 —> 1 0 1 0 1 0 1 0
Address 23 —> 1 1 1 0 1 0 1 0
Memory Array with 24 Addresses

with Algorithm at Read (A) Stage
Figure 4-13 Algorithmic Test Generation
Boundary at some level

of scanned registration
or “pipelining” away
from the memory
array
Data Data
Detection of Memory Control of

incoming Array outgoing
signals signals
Address
Control
scan-memory
boundary
Minimum Requirement Concern: the Logic between
Detection up to Memory Input the Scan Test Area and the
and Control of Memory Output Memory Test Area Is not
Adequately Covered
Non-Scanned Registration inside the Boundary

but Before the Memory Test Area Results in
a Non-Overlap Zone
Figure 4-14 Scan Boundaries
The Memory Array is modeled

for the ATPG Engine so the
ATPG Tool can use the memory
to observe the inputs
and control the outputs
Data In Din Dout Data Out
Memory
Array
ATPG
Address Ain
Model
Control Read/Write
Scan
Architecture
Figure 4-15 Memory Modeling

is blocked off
as if the memory was
cut out of the circuit
Scan Mode Control of

outgoing
signals
Data In Gated Data Out
Detection of Memory
incoming
Array
signals
can be
Address removed Multiplexed Data Out
from
All Registers
netlist for are in the
scan chain
ATPG purposes architecture
Control
scan black-box
boundary
Observe-only registers Gate or Multiplexor is used
used for detection of memory to Block—fix to a known
input signals value—the Memory
Output Signals
Figure 4-16 Black Box Boundaries

is blocked off
cut out of the circuit Input is passed
to output as the
form of output
control
Data In Bypass Data Out
Detection of Memory
incoming
array
signals
can be
Address removed
from
netlist for
ATPG purposes
Control
scan black-box
boundary
Observe-only registers Multiplexor is used to
used for detection of memory pass the input directly
input signals to the output
Figure 4-17 Memory Transparency
Detection of incoming
data signals done here
is blocked off
cut out of the circuit
Input is passed
to output with
registration
Data In Bypass Data Out
Memory In ideal sense,

array timing should
can be also be matched
Address removed
from
netlist for
ATPG purposes
Control
scan black-box
boundary
Observe-only registers Register and multiplexor
not needed on data since is used to emulate memory
register emulates memory timing and output
Figure 4-18 The Fake Word Technique
Data Bus: Possibly to Multiple Memory Arrays
Address Bus: Possibly to Multiple Memory Arrays
Data In Data Out

Memory: data width by address depth
32 x 512
Address
Read/WriteB Memory Array

Address Decode to Row Drivers
Data Decode to Column Drivers
Output Enable Control Circuitry to Read, Write,
and Data Output Enable
Control Signals: Individual Signals to This Memory Array
Test Must Access the Data, Address, and Control Signals

in order to Test This Memory
Figure 4-19 Memory Test Needs
Chip Level
Invoke Algorithm Controller

Done
Retention Address Generator Fail
Debug Data Generator Debug_data
Memory Array(s)
Comparator
INPUTS
Invoke: Start BIST
Retention: Pause BIST and Memory Clocking
Debug: Enable BIST Bitmap Output
OUTPUTS
Fail: A Memory Has Failed a BIST Test
Done: Operation of BIST Is Complete
Debug_data: Debug Data Output
OPERATIONS
Address: Ability to Apply Address Sequences
Data: Ability to Apply Different Data Sequences
Algorithm: Ability to Apply Algorithmic Control Sequences
Comparator: Ability to Verify Memory Data
Figure 4-20 Memory BIST Requirements
Invoke done
Comparator
Algorithm Controller
Retention Fail
Address Generator
Release Data Generator Hold_out
Bitmap Bitmap_out
Memory
Dout
Din DI Array Do
Ain A
Write_en WRB
Read_en CEB
Clk
INPUTS
Invoke: invoke the BIST (apply muxes and release reset)
Retention: enable retention algorithm and pause
Release: discontinue and release pause
Bitmap: enable bitmap output on fail occurrence
OUTPUTS
Fail: sticky fail flag—dynamic under bitmap
Done: operation of BIST is complete
Bitmap_out: fail data under bitmap
Hold_out: indication of pause
Figure 4-21 An Example Memory BIST
Chip Level
bitmap_out1
Memory Array
Invoke with BIST
Reset done1 fail1

bitmap_out2
Memory Array
Bitmap with BIST
done2 fail2
Hold_1 bitmap_out3
Memory Array
with BIST
Hold_2
done3 fail3
Hold_3 bitmap_out4
Memory Array
with BIST
Hold_4
so
s1
done4 fail4
fail 1-4
done 1-4
Invoke: a global signal to invoke all BIST units

Reset: a global signal to hold all BIST units in reset done fail diag_out
Bitmap: a global signal to put all BIST units in debug mode
Hold_#: individual hold signals to place memories in retention
or to select which memory is displayed during debug
done: all memory BISTs have completed
fail: any memory BIST has detected a fault or a failure
diag_out: the memory BIST not in hold mode will present debug data
Figure 4-22 MBIST Integration Issues
bitmap_out1
Memory Array
Invoke with BIST
Reset done1 fail1

bitmap_out2
Memory Array
Bitmap with BIST
done2 fail2
Hold_1 bitmap_out3
Memory Array
with BIST
Hold_2
done3 fail3
Hold_3 bitmap_out4
Memory Array
with BIST
Hold_4
so
s1
done4 fail4
fail 1-4
done 1-4
Invoke: must be a logic 0 when BIST is not enabled

Reset: should be a logic 0 when BIST is not enabled done fail diag_out
Bitmap: should be a logic 0 when BIST is not enabled
Hold_#: should be a logic 0 when BIST is not enabled
done: should not be connected to package output pin when BIST is not enabled
fail: should not be connected to package output pin when BIST is not enabled
diag_out: should not be connected to package output pin when BIST is not enabled
Figure 4-23 MBIST Default Values
done invoke
1-m done
M A 1-n M A 1-m
e r e r
n m r m m r
Invoke o a o a
r y r y
n y s y s
Reset
n with fail with fail
Bitmap 1-n 1-m
I M m I M
n B debug n B
Hold_1 d I d I
e S hold_l1 e S
p T p T
e s hold_l2 e s
Hold_2 n n
d d
e hold_1m e
Hold_n
n n
t t
Bank 1 Bank 2
scan_out m
1-n n n
diag_out
1-m
so
s1
Invoke: global signal invokes bank 1 BIST
Reset: global signal holds bank 1 BIST in reset
diag_out fail done
Bitmap: global signal that enables BIST debug
Hold_#: paired hold signals to place memories in retention
or to select which memory is displayed during debug
done: bank n memory BISTs have completed

fail: any memory BIST has detected a fault or a failure
diag_out: the memory BIST not in hold will present debug data
Figure 4-24 Banked Operation
LFSR - PRPG
DQ DQ DQ
CLK
MBIST
Address
Functional
5
A Memory Array
MBIST Data In
0
F Data
Functional Data In
Algorithm MBIST
Sequencer
Functional Control
Functional & MBIST Data Out Data Out
DQ DQ DQ
CLK
LFSR - MISR
Figure 4-25 LFSR-Based Memory BIST
The Address sequence can be shifted

both forward and backward to provide
all addresses
The Data sequence can be shifted

across the data lines, and can also
provide data for a comparator
0
0
1 Address
0
1
1 Memory Array
0
0
1 1 Data
1 0
1 1
0 0
0 1
0 0
1 1
1 0
1 1
1 0
0 1
0 0
0 1
0 0
1 1 0 Read/Write
1 0 1
1 1 0
1 0 0
1 1 1
0 0 0 The Control sequence can be
shifted across the read-write
or output enable or other
control signals
Figure 4-26 Shift-Based Memory BIST
MBIST
Functional Address
Read-Only Memory Array
MBIST
Functional Read Control
Functional Data Out Data Out
MBIST
DQ DQ DQ
CLK
LFSR - MISR
Figure 4-27 ROM BIST
Memory Testing Fundamentals Summary
Memory Testing Is Defect-Based
Memory Testing Is Algorithmic
Different Types of Memories—Different Algorithms
A Memory Fault Model Is Wrong Data on Read
Memory Testing Relies on Multiple-Clue Analysis
A Memory Test Architecture May CoExist with Scan
A Memory Can Block Scan Test Goals
Modern Embedded Memory Test Is BIST-Based
BIST Is the Moving of the Tester into the Chip
BIST-Based Testing Allows Parallelism
Parallel Testing Impacts Retention Testing
Parallel Testing Impacts Power Requirements
Parallel Testing Requires Chip-Level Integration
Figure 4-28 Memory Test Summary
Chapter 5 Embedded Core Test Fundamentals 1
Chapter 5 Embedded Core Test Fundamentals
Chip-Level
TCU
Core 4 Core 5
Core 1
Core 2
General
Logic
Core 3
Memory Access
Embedded Embedded
Memory Memory
PLL TAP
JTAG Boundary Scan
Figure 5-1 Introduction to Embedded Core Test and Test Integration
WHAT IS A CORE?
SOFT
HDL HDL
Model with Model with
No Test Modeled Test
RTL RTL
Model with Model with
No Test Modeled Test
FIRM
Gate-Level Gate-Level
Netlist with Netlist with
No Test Synthesized Test
Gate-Level Gate-Level
Netlist with Netlist with
Inserted Test Mixed Test
HARD
Layout Layout
GDSII with with Test from
No Test Synthesis
Layout Layout
with Test from with Test
Gate-Level Optimization
Figure 5-2 What is a CORE?
TMode[3:0]
4
Chip-Level
CTCU
3
UDL Core
2 1
Embedded Embedded
Memories Memories
Wrapper
5
PLL TAP
6 JTAG Boundary Scan
- A Core-Based Device May Include -

1. Core(s) with Test Wrapper + Embedded Memory Arrays
2. Chip-Level User Defined Logic + Embedded Memory Arrays
3. Chip-Level Test Selection and Control Logic
4. Dedicated Chip-Level Test Pins
5. Chip-Level Clock Generation and Clock Control Logic
6. IEEE 1149.1 Controller and Boundary Scan Logic
Figure 5-3 Chip Designed with Core
A Reuse
Embeddable
Core
Business Deliverables
1. The Core
2. The Specification or Data Sheet
3. The Various Models
4. The Integration Guide
5. The Reuse Vectors

Figure 5-4 Reuse Core Deliverables
CORE-BASED DESIGN DFT ISSUES
Chip-Level
Device
ACCESS
A KNOWN
A KNOWN TO THE
EXPECTED
STIMULUS EMBEDDED
RESPONSE
CORE
Other
Chip-Level Logic
• If the Core is HARD — DFT must exist before

delivery — how is access provided at the chip level?
• If the Core is HARD — and delivered with pre-generated

vectors — how are vectors merged in the whole test program?
• If the Core is HARD — and part of the overall chip test

environment — how is the core test scheduled?
• If the Core is HARD — and part of the overall chip test

environment — what defaults are applied when not active?
• If the Core is HARD — what is the most economical and

effective test mix — Scan? LBIST? MBIST? Functional?
• If the Core is SOFT — is the overall chip test environment

developed as a Core and UDL or as a unified design?
• If the Core operates at a different frequency from the pin

I/O or other chip logic — how does this affect DFT and Test?
Figure 5-5 Core DFT Issues
A Reuse
Embeddable
Core
• DFT Drivers During Core Development

Target Market/business — Turnkey versus Customer Design
Target Cost-Performance Profile — Low to High
Potential Packages — Plastic versus Ceramic
Potential Pin Counts
• Core Test Architectures and Interfaces

Direct Access — Mux Out Core Terminals
Add-On Test Wrapper — Virtual Test Socket
Interface Share-Wrapper — Scanned Registered Core I/O
At-Speed Scan Or Logic Built-in Self-test (LBIST)
• Design For Reuse Considerations

Dedicated Core Test Ports — Access Via IC Pins
Reference Clocks — Test and Functional
Test Wrapper — Signal Reduction/No JTAG/No Bidi’s
Virtual Test Socket — Vector Reuse
Figure 5-6 Core Development DFT Considerations
A Chip Package with

44 Functional Signals
A ReUse
Embeddable
Core with
60 Functional
Signals
• Core DFT Interface Considerations

Note — none of this is known a priori
Access to core test ports via IC pins (integration)
I/O port count less restrictive than IC pin count
Impact of routing core signals to the chip edge
- Dedicated test signals to place in test mode
- Number of test signals needed to test core
- Frequency requirements of test signals
Embedded
UDL Logic At the time of Core Development, Core
the UDL logic is not available
and i’s configuration is not known
DQ
DQ
For example:
- registered inputs or outputs
- combinational logic
- bidirectional signals or tristate busses
QD
QD
How are vectors generated for a Hard
Core before integration?
How are vectors delivered that can

assess the signal timing or frequency?
UDL CORE
Domain How is test access planned to be Domain
provided — through the UDL or directly
from the package pins?
Figure 5-8 DFT Core Interface Concerns
A Chip Package with

44 Functional Signals
Test Wrapper with 10 Test Signals
A Reuse
Embeddable
Core with
60 Functional
Signals
• Core DFT Interface Considerations

Wrapper for interface signal reduction
Wrapper for frequency assessment
Wrapper as frequency boundary
Wrapper as a virtual test socket (for ATPG)
Note: bidirectional functional signals can’t

cross the boundary if wrapper or scan
“Land between the Lakes”

The Isolation Test Wrapper Embedded
UDL Logic Hard Core
D Q
DQ DQ DQ
D Q
QD
QD QD
D Q
UDL Scan CORE Scan
Domain Domain
Core-Wrapper Scan
Domain
where the wrapper is the registered
core functional I/F that is
scan-inserted separately
Note: Wrapper and core are on same clock
and path delay is used to generate vectors
Figure 5-10 Registered Isolation Test Wrapper

UDL Logic Hard Core
DQ DQ
DQ D Q
QD
QD
Q D QD
UDL Scan CORE Scan

Domain Domain
Wrapper Scan
Domain
where the wrapper is an added “slice”

between the core functional I/F
and the UDL functional I/F
Wrapper and core are on different clocks
Figure 5-11 Slice Isolation Test Wrapper

UDL Logic Hard Core
Core_Test TR_SDO
DQ DQ
DQ D Q
QD
QD
UDL Scan TR_SE TR_CLK CORE Scan

Domain Domain
TR_SDI TR_Mode
Wrapper Scan
Domain
System Clock
the wrapper is an added “slice”

between the core functional I/F
and the UDL functional I/F
Wrapper and core are on different clocks

Figure 5-12 Slice Isolation Test Wrapper Cell
Internal BIST In
D Q
Direct Test Internal BIST Out

Signals go Q D
to Package
Pins
Internal Scan In
D Q
Internal Scan Out

Q D
QD
QD QD
Wrapper Scan In
D Q
UDL Scan CORE Scan
Domain Domain
Core-Wrapper Scan
Domain Embedded
UDL Logic Hard Core
The Isolation Test Wrapper
All Core Test Interface Signals pass through the

Test Wrapper without being acted upon
All Core I/O are part of the Wrapper Scan Chain
So Total Core Test I/F is:
Internal Scan
Internal MBIST
Wrapper Scan
Figure 5-13 Core DFT Connections through the Test Wrapper
Internal BIST In
D Q
Direct Test Internal Scan In

Signals Go D Q
to Package
Pins
Test Mode Control Core Test

Controller
QD
QD QD
Wrapper Scan In
D Q
UDL Scan CORE Scan
Domain Domain
Core-Wrapper Scan
Domain Embedded
UDL Logic Hard Core
The Isolation Test Wrapper
All Core Test Interface Signals pass through the

Test Wrapper and may be acted upon by a Test Mode
All Core I/O are part of the Wrapper Scan Chain
So Total Core Test I/F is:
Gated Internal Scan
Gated Internal MBIST
Gated Wrapper Scan
Figure 5-14 Core DFT Connections with Test Mode Gating
Can’t Use
the
Wrapper
Cell
Wrapper Cell
UDL Test Wrapper Core
PLL Clock Out

A Reuse Signal(s)
Embeddable
Bypass
Hard Core
Test Clock
with Pre-Existing
Clock Trees
Mul/Div
Clocks
• DFT Considerations
Can’t Support Bidirectional Core Ports
Input and Reference Clocks
Figure 5-15 Other Core Interface Signal Concerns
A Chip Package with

a 25 MHz Interface
Test Wrapper with 10 Test Signals
A Reuse
Embeddable
Core with
Fmax = 100MHz
Logic
• Core DFT Frequency Considerations

Wrapper for frequency boundary
Test signals designed for low frequency
Package interface designed for high frequency
Wrapper as a multi-frequency ATPG test socket
Note: functional high/low frequency signals can

cross the wrapper—the test I/F is the concern
Figure 5-16 DFT Core Interface Frequency Considerations
The Core’s Test Port A Test Wrapper

Internal Scan Data In
Internal Scan Enable
Wrapper Scan Data In
Wrapper Scan Enable
Wrapper Test Enable A Reuse
MemBIST Invoke Embeddable
MemBIST Retention Core with
MemBIST Bitmap
Internal Scan Data Out Existing DFT
Wrapper Scan Data Out and Test Features
MemBIST Fail
MemBIST Done
MemBIST Bitmap Out
• Core DFT Goals and Features

Embedded Memory Test by MBIST
- Few Signals — High Coverage — Less Test Time
- Bitmap Characterization Support
Structure by Stuck-At Scan
- High Coverage — Fewer Vectors — Ease of Application
Frequency by At-Speed Scan (Path & Transition Delay)
- Deterministic — Fewer Vectors — Ease of Application
Reuse of Core Patterns Independent of Integration
Test Insulation from Customer Logic
Embedded Core I/O Timing Specifications with Wrapper
Minimize Test Logic Area Impact
Minimize Test Logic Performance Penalty
DFT Scannability Logic
Full-Scan Single-Edge Triggered MUX DFF
Tristate Busses - Contention/Float Prevention
Negedge Inputs and Outputs
Iddq—No Active Logic and Clock Stop Support
Figure 5-17 A Reuse Embedded Core’s DFT Features
The Core’s Test Port A Test Wrapper

Internal Scan Data In
Internal Scan Enable
Wrapper Scan Data In
Wrapper Scan Enable
Wrapper Test Enable A Reuse
MemBIST Invoke Embeddable
MemBIST Retention Core with
MemBIST Bitmap
Internal Scan Data Out Existing DFT
Wrapper Scan Data Out and Test Features
MemBIST Fail
MemBIST Done
MemBIST Bitmap Out
• Core Economic Considerations

Test Integration (Time-to-Market)
Core Area and Routing Impact (Silicon/Package Cost)
Core Power and Frequency Impact (Package/Pin Cost)
Core Test Program Time/Size/Complexity (Tester Cost)
Chip Retention Testing

Test
Program Chip Logic Testing
Budget(s)
Total
Memory Testing
Time Embedded Core Testing
and/or
Tester
Chip Parametrics
Memory
Figure 5-18 Core Test Economics
TMode[3:0]
Chip-Level
CTCU
UDL Core
Embedded Embedded
Memories Memories
Wrapper
PLL TAP
JTAG Boundary Scan
- A Core-Base Device May Include -

Core(s) with Test Wrapper and Embedded Memory Arrays
Chip-Level Non-Core Logic with Embedded Memory Arrays
Chip-Level Test Selection and Control Logic
Dedicated Chip-Level Test Pins
Chip-Level Clock Generation and Control Logic
IEEE 1149.1 Controller and Boundary Scan Logic
Figure 5-19 Chip with Core Test Architecture
Pre-Existing
Vectors
Wrapper and
Chip-Level Core Scan
CTCU Package Pin
Test Selection Connections
UDL Core
PLL TAP
Clock Bypass
JTAG Boundary Scan
Figure 5-20 Isolated Scan-Based Core-Testing
Development
Generated Vectors
Wrapper and
Chip-Level UDL Scan
CTCU Package Pin
Connections
Test Selection
UDL
Clock Bypass
PLL TAP
JTAG Boundary Scan
Development
Generated Vectors
Wrapper and
Chip-Level UDL Scan
CTCU Package Pin
Connections
Test Selection
UDL
Clock Bypass
PLL TAP
JTAG Boundary Scan
I/O specification testing—bus_SE

Tristate busses - contention/float prevention
Iddq—HighZ pin
Pin requirements—(open drains)
Development
Generated Vectors
Chip-Level
CTCU
Test Selection
UDL Core
Embedded Embedded
Memories Memories
Wrapper
PLL TAP
Clock Bypass
JTAG Boundary Scan
Figure 5-23 Memory Testing the Device
Chip-Level
CTCU
Core 4 Core 5
Core 1
Core 2
General
Logic
Core 3
Memory Access
Embedded Embedded
Memory Memory
PLL TAP
JTAG Boundary Scan
• Chip-level DFT integration considerations

each core/vector set must have:
1. Power Rating during Test
2. Frequency/Data Rate of Test Vectors
3. Fault Coverage of the Test Vectors
4. Required Test Architecture to Reuse Vectors
5. ATPG Test Wrapper or Encrypted Sim Model
6. The Vector Set’s Format
7. The Vector Set Sizing
Figure 5-24 DFT Integration Architecture
Chip Parametrics
Chip Iddq (Merged)
Core 1 Test Components
Chip-Level Memory
Chip-Level Analog
Core 1 Components
Core 1 Iddq
Core 1 Scan
Core 1 Memory Test
Core 1 Analog
Test
Time
in (s)
1 2 3 4
# of Cores
• Receiving Core DFT Specification
• Driven by Fab and Integration Requirements
• Core DFT Specification Items

- Test Mix
- Style of Test
- Maximum Number of Integration Signals
- Minimum-Maximum Test Frequency
- Maximum Vector Sizing
- Minimum Fault Coverage
- Clock Source
Figure 5-26 Selecting or Receiving a Core
• Core Test Driven by Cost-of-Test and TTM

• Two Concerns: Reuse and Integration
• Reuse: Interface, Clocks, Test Features
- number of dedicated test signal
- size of test integration interface
- ability to test interface timing
- no functional bidirectional ports
- specifications and vectors based on clock-in
- specifications and vectors based on clock-out
- ability to stop clock for retention or Iddq
- number of clock domains
- at-speed full scan
- at-speed memory BIST
- use of a scan test wrapper
- self-defaulting safety logic
• Integration: Core Connections, Chip Test Modes
- simple core integration
- reuse of pre-existing vectors
- application of test signal defaults
- shared resources (pins and control logic)
- shared testing (parallel scheduling)
- chip level test controller
Figure 5-27 Embedded Core DFT Summary

Design For Test by Alfred L Crouch

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Figures to Accompany

© 1999 Prentice Hall, All Rights Reserved

Chapter 1 Test and Design-for-Test Fundamentals

Chapter 2 Automatic Test Pattern Generation Fundamentals

Chapter 3 Scan Architectures and Techniques

Figure 3-3 Scan Effective Circuit

Chapter 4 Memory Test Architectures and Techniques

Figure 4-9 Array Bridging Faults

Chapter 5 Embedded Core Test Fundamentals

Figure 5-15 Other Core Interface Signal Concerns

Chapter 1 Test and Design-for-Test Fundamentals

The goal over time is to reduce the cost of manufacturing

Behavioral Specification and Model

Gate-Level Library Mapping

Physical Process Mapping

Figure 1-2 Concurrent Test Engineering

Pro & Con Perceptions of DFT

Eases Adds Complexity

observed truth table

Transistor and Gate Representation of Defects, Faults, and Failures

defects transistor faults stuck faults

Figure 1-7 Types of Testing

The chip will be accessed by the tester at its pins only

A custom (load) board will be made for this purpose

Each pin has a limited number of bits available (e.g., 2 MB)

The test program (set of vectors and tester control) will be

The primary goal of manufacturing test is structural verification

Figure 1-8 Manufacturing Test Load Board

2 Meg Clock Gen 1

Figure 1-9 Using ATE

Chip Point of View

1. Input Setup Time: time the signal must arrive

2. Input Hold Time: time the signal must remain

3. Output Valid Time: time the signal takes to be

4. Output Hold Time: time that the signal remains

Tester Point of View

Figure 1-10 Pin Timing

Figure 1-11 Test Program Components

Chapter 2 Automatic Test Pattern Generation Fundamentals

Observe Point Assessment

Figure 2-1 The Overall Pattern Generation Process

Pro & Con Perceptions of ATPG

Fault Observe Point Assessment

Figure 2-3 The ATPG Process

Figure 2-4 Combinational Stuck-At Fault

Delay from Strong Driver

A Delay Model Element

Slow Gate Input

The Delay Fault Model

Effect of Delay Fault

Added Rise Delay Added Fall Delay

Figure 2-5 The Delay Fault

Leakage from Bridge

A Leakage Fault Model

Internal Gate Leakage

The Current Fault Model

Figure 2-6 The Current Fault

Figure 2-7 Stuck-At Fault Effective Circuit

1. Any fault that

Fault Equivalence Table 3. If one fault is

INV a@1 = z@0 : a@0 = z@1 4. Fault selection only

Figure 2-9 Fault Equivalence Example

1 BIT ADDER with CARRY