Expt.

5: Study of Operational Amplifiers

Pin-Diagram of IC-741
IC-741 is a 8-pin IC. The pin diagram is shown in Fig. 1. Every IC should be supplied
with positive and negative dc voltages of +12 and –12 volts respectively. +12V should be
supplied to pin-7 and –12V to pin-4. Pin-2 is the inverting input pin and Pin-3 is the non-
inverting input pin. Output can be measured at the output pin-6 with respect to the breadboard
ground. Pins 1 and 5 are used for output offset voltage compensation. These two pins are not
required for normal applications.

Fig. 1 Pin Diagram

Breadboard:

Fig. 2 Physical diagram of a breadboard

The physical diagram of a typical breadboard is shown in Fig.2. This board can be divided
into 4 regions. The top and bottom regions marked by red and blue lines represent horizontal
short. In these regions, all the pins in a row are shorted internally. In regions 2 and 3 each
column is shorted internally. IC should be placed in between the regions 2 and 3. Fig. 3
clearly shows the vertically and horizontally shorted regions.

Fig.3 Vertical and Horizontal Shorted regions

Part1: Inverting Amplifier/ Non Inverting Amplifier

Aim: To verify the characteristics of inverting amplifier

Circuit Diagram:

Inverting Amplifier Non-Inverting Amplifier

Design Procedure:
1. Select the desired gain of the amplifier.
2. The gain of inverting amplifier is given by
Vo R
AF = =− F
Vin R1
3. The gain for non-inverting amplifier is given by
 Vo R
AF = =1+ F
Vin R1
4. For example, if AF = 2, Select R1= 5 kΩ, RF = 10 kΩ and RL = 10 kΩ.
Experimental Procedure:
1. Connect the circuit as shown in Fig.
2. Apply +12V to pin 7 and –12V to pin 4. Connect common terminal of power supply
to ground on the breadboard.
3. Apply a dc voltage of 0.1V to the pin-2 of IC. Measure output.
4. Increase voltage in steps of 0.1V upto 1.0V and measure output.

Part2: Low-pass filter

Aim: To verify the function of low-pass filter, and to verify the gain of filter at different input
frequencies.
Circuit Diagram:

Fig. 1 Frequency Response

Fig. 2 Circuit Diagram

Theory:
 The frequency response of a low-pass filter is shown in Fig.1. The filter has a constant
gain from 0 Hz to a high cut-off frequency fH. At fH the gain is down by 3 dB; after f > fH the
gain decreases with an increase in input frequency at a rate of –20 dB per decade. The
frequencies between 0 Hz and fH are known as pass band frequencies, where as the range of
frequencies those beyond fH are called stop band frequencies.

Design Procedure:
1. Select high cut-off frequency fH of the filter. Let f H = 700 Hz.
2. Select value of C less than 1 µF. (As the maximum value of ceramic capacitor
available is 1 µF). Let C = 0.01 µF.
3. Calculate R from Eq. (1).
1
fH = (1)
2πRC
For fH = 700 Hz and C = 0.01 µF, from Eq. (1) R = 22.7 kΩ.
Select nearest value of standard resistance available R = 22 kΩ .
4. Select R1 and Rf such that required pass band gain is obtained.
Pass band gain = 1+(RF/R 1).
Let R1= RF = 10 kΩ for a pass band gain of 2.
5. Final values of components:
R1 = 10 kΩ, RF = 10 kΩ, R = 22 kΩ, C = 0.01 µF, fH=700 Hz.
Experimental Procedure:
1. Apply sinusoidal inputs with different frequencies as shown in table and check the
gain of the filter.
2. Fill in the table and see if the following observations can be made.
At f < fH
V0
= Pass-band gain (AF)
V in

At f = fH
V0 A
= F = 0 .707 A F
V in 2

At f > fH
V0
< AF
V in
 Also at f = 10 fH, the gain decreases by ten times to that at f = fH.

S.No Frequency (Hz) I/P (V) O/P (V) Gain

1 FDes/10. 1.
2 FDes 1.
3 FDes *10 1.

Part3: High-pass filter

Circuit Diagram:

Fig. 1 Frequency Response

Fig. 2 Circuit Diagram

Theory:
The frequency response of a high-pass filter is shown in Fig.1. The filter has a
constant gain above the low cut-off frequency fL. At fL the gain is down by 3 dB the pass
band gain; below f < fL it decreases with an decrease in input frequency at a rate of –20 dB
per decade. The frequencies above fL are known as pass band frequencies; where as the
frequencies from 0 Hz to fL are called stop band frequencies.

Design Procedure:
1. Select low cut-off frequency fL of the filter. Let fL = 800 Hz.
2. Select value of C less than 1 µF. (As the maximum value of ceramic capacitor
available is 1 µF). Let C = 0.01 µF.
 3. Calculate R from Eq. (1).
1
fH = (1)
2πRC
For fL = 700 Hz and C = 0.01 µF, from Eq. (1) R = 22.7 kΩ.
Select nearest value of standard resistance available R = 22 kΩ.
4. Select R1 and Rf such that required pass band gain is obtained.
Pass band gain = 1+(RF/R 1).
Let R1= RF = 10 kΩ for a pass band gain of 2.
5. Final values of components:
R1 = 10 kΩ, RF = 10 kΩ, R = 22 kΩ, C = 0.01 µF, fL=700 Hz.
Experimental Procedure:
1. Apply sinusoidal inputs with different frequencies as shown in table, fill in the blank
columns and check the gain of the filter.

S.No Frequency (Hz) I/P (V) O/P (V) Gain

1 F Des/10 1.
2 FDes 1.
3 FDes *10 1.