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M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
DESCRIPTION
The M5M29KB/T641AVP are 3.3V-only high speed M5M29KB/T641AVP provides for Software Lock Release
67,108,864-bit CMOS boot block FLASH Memories with function. Usually, all memory blocks are locked and can not
alternating BGO(Back Ground Operation) feature. The BGO be programmed or erased, when WP# is low. Using Software
feature of the device allows Program or Erase operations to be Lock Release function, program or erase operation can be
performed in one bank while the device simultaneously allows executed.
Read operations to be performed on the other bank. FEATURES
This BGO feature is suitable for mobile and personal Access time Flash 70ns (Max.)
computing, and communication products. Supply voltage VCC= 3.0 ~ 3.6V
The M5M29KB/T641AVP are fabricated by CMOS technology Ambient temperature Ta=-40 ~ 85 °C
for the peripheral circuit and DINOR IV(Divided bit-line NOR IV) Package 48pin TSOP(Type-I), Lead pitch 0.5mm
architecture for the memory cell, and are available in 48pin
Outer-lead finishing : Sn-Cu
TSOP(I) for lead free use.
APPLICATION
Digital Cellar Phone, Telecommunication,
PDA, Car Navigation System, Video Game Machine
A15 1 48 A16
A14 2 47 BYTE#
A13 3 46 GND
A12 4 45 DQ15/A-1
A11 5 44 DQ7
A10 6 43 DQ14
A9 7 42 DQ6
A8 8 41 DQ13
A19 9 40 DQ5
12.0 mm
A20 10 39 DQ12
WE# 11 38 DQ4
RP#
A21
12
13 M5M29KB/T641AVP 37
36
VCC
DQ11
WP# 14 35 DQ3
RY/BY# 15 34 DQ10
A18 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
A3 22 27 GND
A2 23 26 CE#
A1 24 25 A0
Outline
20.0 mm 48P3R-C
1 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Vcc GND
A0 to A21 RY/BY#
Capacitance
2 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
3 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Status / ID Register
4 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Read
Deep Power Down
The 64M-bit DINOR IV Flash Memory has four read
modes, which accesses to the memory array ,the Page
When RP# is at VIL, the device is in the deep power down
read, the Device Identifier and the Status Register. The
mode and its power consumption is substantially low.
appropriate read commands are required to be written to
During read modes, the memory is deselected and the data
the CUI. Upon initial device power up or after exit from
input/output are in a high-impedance (High-Z) state. After
deep power down, the 64M-bit DINOR IV Flash Memory
return from power down, the CUI is reset to Read Array,
automatically resets to read array mode. In the read array and the Status Register is cleared to value 80H.
mode and in the conditions are low level input to OE#, high
level input to WE# and RP#, low level input to CE# and During block erase or program modes, RP# low will abort
address signals to the address inputs (A21 - A0:Word either operation. Memory array data of the block being
Mode, A21-A-1:Byte Mode) the data of the addressed altered become invalid.
location to the data input/output (DQ15-DQ0:Word Mode,
DQ7-DQ0:Byte Mode) is output. Automatic Power Down (Auto-PD)
The Automatic Power Down minimizes the power
consumption during read mode. The device automatically
Write turns to this mode when any addresses or CE# isn't
changed more than 200ns after the last alternation. The
Writes to the CUI enables reading of memory array data, power consumption becomes the same as the stand-by
device identifiers and reading and clearing of the Status mode. During this mode, the output data is latched and can
Register. They also enable block erase and program. The be read out. New data is read out correctly when
CUI is written by bringing WE# to low level and OE# is at addresses are changed.
high level, while CE# is at low level. Address and data are
latched on the earlier rising edge of WE# and CE#. BBR(Back Bank array Read)
Standard micro processor write timings are used.
In the 64M-bit DINOR IV Flash Memory , when one
memory address is read according to a Read Mode in the
case of the same as an access when a Read Mode
command is input, an another Bank memory data can be
read out (Read Array or Page Read) by changing an
Alternating Background Operation (BGO) another Bank address.
5 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
6 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Data Protection
The 64M-bit DINOR IV Flash Memory has a master Write
Protect pin (WP#). When WP# is at VIH, all blocks can be
programmed or erased. When WP# is low, all blocks are in
locked mode which prevents any modifications to memory
blocks. Software Lock Release function is only command
which allows to program or erase.
7 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
x8 (Byte x16 (Word x8 (Byte x16 (Word x8 (Byte x16 (Word x8 (Byte x16 (Word
Mode) Mode) Mode) Mode) Mode) Mode) Mode) Mode)
1A0000H- D0000H- 3C0000H- 1E0000H- 5E0000H- 2F0000H- 7F0000H- 3F8000H-
1AFFFFH D7FFFH 32Kword 33 3CFFFFH 1E7FFFH 32Kword 67 5EFFFFH 2F7FFFH 32Kword 101 7FFFFFH 3FFFFFH 32Kword 134
190000H- C8000H- 3B0000H- 1D8000H- 5D0000H- 2E8000H- 7E0000H- 3F0000H-
19FFFFH CFFFFH 32Kword 32 3BFFFFH 1DFFFFH 32Kword 66 5DFFFFH 2EFFFFH 32Kword 100 7EFFFFH 3F7FFFH- 32Kword 133
180000H- C0000H- 3A0000H- 1D0000H- 5C0000H- 2E0000H- 7D0000H- 3E8000H-
18FFFFH C7FFFH 32Kword 31 3AFFFFH 1D7FFFH 32Kword 65 5CFFFFH 2E7FFFH 32Kword 99 7DFFFFH 3EFFFFH 32Kword 132
170000H- B8000H- 390000H- 1C8000H- 5B0000H- 2D8000H- 7C0000H- 3E0000H-
17FFFFH BFFFFH 32Kword 30 39FFFFH 1CFFFFH 32Kword 64 5BFFFFH 2DFFFFH 32Kword 98 7CFFFFH 3E7FFFH- 32Kword 131
BANK(III)
BANK(IV)
BANK(IV)
C0000H- 60000H- 2E0000H- 170000H- 500000H- 280000H- 710000H- 388000H-
BANK(III)
CFFFFH 67FFFH 32Kword 19 2EFFFFH 177FFFH 32Kword 53 50FFFFH 287FFFH 32Kword 87 71FFFFH 38FFFFH 32Kword 120
B0000H- 58000H- 2D0000H- 168000H- 4F0000H- 278000H- 700000H- 380000H-
BFFFFH 5FFFFH 32Kword 18 2DFFFFH 16FFFFH 32Kword 52 4FFFFFH 27FFFFH 32Kword 86 70FFFFH 387FFFH- 32Kword 119
A0000H- 50000H- 2C0000H- 160000H- 4E0000H- 270000H- 6F0000H- 378000H-
AFFFFH 57FFFH 32Kword 17 2CFFFFH 167FFFH 32Kword 51 4EFFFFH 277FFFH 32Kword 85 6FFFFFH 37FFFFH 32Kword 118
90000H- 48000H- 2B0000H- 158000H- 4D0000H- 268000H- 6E0000H- 370000H-
9FFFFH 4FFFFH 32Kword 16 2BFFFFH 15FFFFH 32Kword 50 4DFFFFH 26FFFFH 32Kword 84 6EFFFFH 377FFFH- 32Kword 117
80000H- 40000H- 2A0000H- 150000H- 4C0000H- 260000H- 6D0000H- 368000H-
8FFFFH 47FFFH 32Kword 15 2AFFFFH 157FFFH 32Kword 49 4CFFFFH 267FFFH 32Kword 83 6DFFFFH 36FFFFH 32Kword 116
70000H- 38000H- 290000H- 148000H- 4B0000H- 258000H- 6C0000H- 360000H-
7FFFFH 3FFFFH 32Kword 14 29FFFFH 14FFFFH 32Kword 48 4BFFFFH 25FFFFH 32Kword 82 6CFFFFH 367FFFH- 32Kword 115
60000H- 30000H- 280000H- 140000H- 4A0000H- 250000H- 6B0000H- 358000H-
6FFFFH 37FFFH 32Kword 13 28FFFFH 147FFFH 32Kword 47 4AFFFFH 257FFFH 32Kword 81 6BFFFFH 35FFFFH 32Kword 114
50000H- 28000H- 270000H- 138000H- 490000H- 248000H- 6A0000H- 350000H-
5FFFFH 2FFFFH 32Kword 12 27FFFFH 13FFFFH 32Kword 46 49FFFFH 24FFFFH 32Kword 80 6AFFFFH 357FFFH- 32Kword 113
40000H- 20000H- 260000H- 130000H- 480000H- 240000H- 690000H- 348000H-
4FFFFH 27FFFH 32Kword 11 26FFFFH 137FFFH 32Kword 45 48FFFFH 247FFFH 32Kword 79 69FFFFH 34FFFFH 32Kword 112
30000H- 18000H- 250000H- 128000H- 470000H- 238000H- 680000H- 340000H-
3FFFFH 1FFFFH 32Kword 10 25FFFFH 12FFFFH 32Kword 44 47FFFFH 23FFFFH 32Kword 78 68FFFFH 347FFFH- 32Kword 111
BANK(I)
0BFFFH 05FFFH 4Kword 5 20FFFFH 107FFFH 32Kword 39 42FFFFH 217FFFH 32Kword 73 63FFFFH 31FFFFH 32Kword 106
08000H- 04000H- 1F0000H- F8000H- 410000H- 208000H- 620000H- 310000H-
09FFFH 04FFFH 4Kword 4 1FFFFFH FFFFFH 32Kword 38 41FFFFH 20FFFFH 32Kword 72 62FFFFH 317FFFH- 32Kword 105
06000H- 03000H- 1E0000H- F0000H- 400000H- 200000H- 610000H- 308000H-
07FFFH 03FFFH 4Kword 3 1EFFFFH F7FFFH 32Kword 37 40FFFFH 207FFFH 32Kword 71 61FFFFH 30FFFFH 32Kword 104
04000H- 02000H- 1D0000H- E8000H- 3F0000H- 1F8000H- 600000H- 300000H-
05FFFH 02FFFH 4Kword 2 1DFFFFH EFFFFH 32Kword 36 3FFFFFH 1FFFFFH 32Kword 70 60FFFFH 307FFFH- 32Kword 103
02000H- 01000H- 1C0000H- E0000H- 3E0000H- 1F0000H- 5F0000H- 2F8000H-
03FFFH 01FFFH 4Kword 1 1CFFFFH E7FFFH 32Kword 35 3EFFFFH 1F7FFFH 32Kword 69 5FFFFFH 2FFFFFH 32Kword 102
00000H- 00000H- 1B0000H- D8000H- 3D0000H- 1E8000H-
01FFFH 00FFFH 4Kword 0 1BFFFFH DFFFFH 32Kword 34 3DFFFFH 1EFFFFH 32Kword 68
A21-A-1 A21-A0 A21-A-1 A21-A0 A21-A-1 A21-A0 A21-A-1 A21-A0
(Byte (Word (Byte (Word (Byte (Word (Byte (Word
Mode) Mode) Mode) Mode) Mode) Mode) Mode) Mode)
8 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
x8 (Byte x16 (Word x8 (Byte x16 (Word x8 (Byte x16 (Word x8 (Byte x16 (Word
Mode) Mode) Mode) Mode) Mode) Mode) Mode) Mode)
210000H- 108000H- 430000H- 218000H- 650000H- 328000H- 7FE000H- 3FF000H-
21FFFFH 10FFFFH 32Kword 33 43FFFFH 21FFFFH 32Kword 67 65FFFFH 32FFFFH 32Kword 101 7FFFFFH 3FFFFFH 4Kword 134
200000H- 100000H- 420000H- 210000H- 640000H- 320000H- 7FC000H- 3FE000H-
20FFFFH 107FFFH 32Kword 32 42FFFFH 217FFFH 32Kword 66 64FFFFH 327FFFH 32Kword 100 7FDFFFH 3FEFFFH 4Kword 133
1F0000H- F8000H- 410000H- 208000H- 630000H- 318000H- 7FA000H- 3FD000H-
1FFFFFH FFFFFH 32Kword 31 41FFFFH 20FFFFH 32Kword 65 63FFFFH 31FFFFH 32Kword 99 7FBFFFH 3FDFFFH 4Kword 132
1E0000H- F0000H- 400000H- 200000H- 620000H- 310000H- 7F8000H- 3FC000H-
1EFFFFH F7FFFH 32Kword 30 40FFFFH 207FFFH 32Kword 64 62FFFFH 317FFFH 32Kword 98 7F9FFFH 3FCFFFH 4Kword 131
BANK(III)
1D0000H- E8000H- 3F0000H- 1F8000H- 610000H- 308000H- 7F6000H- 3FB000H-
1DFFFFH EFFFFH 32Kword 29 3FFFFFH 1FFFFFH 32Kword 63 61FFFFH 30FFFFH 32Kword 97 7F7FFFH 3FBFFFH 4Kword 130
1C0000H- E0000H- 3E0000H- 1F0000H- 600000H- 300000H- 7F4000H- 3FA000H-
1CFFFFH E7FFFH 32Kword 28 3EFFFFH 1F7FFFH 32Kword 62 60FFFFH 307FFFH 32Kword 96 7F5FFFH 3FAFFFH 4Kword 129
1B0000H- D8000H- 3D0000H- 1E8000H- 5F0000H- 2F8000H- 7F2000H- 3F9000H-
1BFFFFH DFFFFH 32Kword 27 3DFFFFH 1EFFFFH 32Kword 61 5FFFFFH 2FFFFFH 32Kword 95 7F3FFFH 3F9FFFH 4Kword 128
BANK(I)
1A0000H- D0000H- 3C0000H- 1E0000H- 5E0000H- 2F0000H- 7F0000H- 3F8000H-
1AFFFFH D7FFFH 32Kword 26 3CFFFFH 1E7FFFH 32Kword 60 5EFFFFH 2F7FFFH 32Kword 94 7F1FFFH 3F8FFFH 4Kword 127
190000H- C8000H- 3B0000H- 1D8000H- 5D0000H- 2E8000H- 7E0000H- 3F0000H-
19FFFFH CFFFFH 32Kword 25 3BFFFFH 1DFFFFH 32Kword 59 5DFFFFH 2EFFFFH 32Kword 93 7EFFFFH 3F7FFFH- 32Kword 126
180000H- C0000H- 3A0000H- 1D0000H- 5C0000H- 2E0000H- 7D0000H- 3E8000H-
18FFFFH C7FFFH 32Kword 24 3AFFFFH 1D7FFFH 32Kword 58 5CFFFFH 2E7FFFH 32Kword 92 7DFFFFH 3EFFFFH 32Kword 125
170000H- B8000H- 390000H- 1C8000H- 5B0000H- 2D8000H- 7C0000H- 3E0000H-
17FFFFH BFFFFH 32Kword 23 39FFFFH 1CFFFFH 32Kword 57 5BFFFFH 2DFFFFH 32Kword 91 7CFFFFH 3E7FFFH- 32Kword 124
160000H- B0000H- 380000H- 1C0000H- 5A0000H- 2D0000H- 7B0000H- 3D8000H-
16FFFFH B7FFFH 32Kword 22 38FFFFH 1C7FFFH 32Kword 56 5AFFFFH 2D7FFFH 32Kword 90 7BFFFFH 3DFFFFH 32Kword 123
150000H- A8000H- 370000H- 1B8000H- 590000H- 2C8000H- 7A0000H- 3D0000H-
15FFFFH AFFFFH 32Kword 21 37FFFFH 1BFFFFH 32Kword 55 59FFFFH 2CFFFFH 32Kword 89 7AFFFFH 3D7FFFH- 32Kword 122
140000H- A0000H- 360000H- 1B0000H- 580000H- 2C0000H- 790000H- 3C8000H-
14FFFFH A7FFFH 32Kword 20 36FFFFH 1B7FFFH 32Kword 54 58FFFFH 2C7FFFH 32Kword 88 79FFFFH 3CFFFFH 32Kword 121
BANK(IV)
BANK(III)
13FFFFH 9FFFFH 32Kword 19 35FFFFH 1AFFFFH 32Kword 53 57FFFFH 2BFFFFH 32Kword 87 78FFFFH 3C7FFFH- 32Kword 120
120000H- 90000H- 340000H- 1A0000H- 560000H- 2B0000H- 770000H- 3B8000H-
12FFFFH 97FFFH 32Kword 18 34FFFFH 1A7FFFH 32Kword 52 56FFFFH 2B7FFFH 32Kword 86 77FFFFH 3BFFFFH 32Kword 119
110000H- 88000H- 330000H- 198000H- 550000H- 2A8000H- 760000H- 3B0000H-
11FFFFH 8FFFFH 32Kword 17 33FFFFH 19FFFFH 32Kword 51 55FFFFH 2AFFFFH 32Kword 85 76FFFFH 3B7FFFH- 32Kword 118
100000H- 80000H- 320000H- 190000H- 540000H- 2A0000H- 750000H- 3A8000H-
10FFFFH 87FFFH 32Kword 16 32FFFFH 197FFFH 32Kword 50 54FFFFH 2A7FFFH 32Kword 84 75FFFFH 3AFFFFH 32Kword 117
BANK(II)
F0000H- 78000H- 310000H- 188000H- 530000H- 298000H- 740000H- 3A0000H-
FFFFFH 7FFFFH 32Kword 15 31FFFFH 18FFFFH 32Kword 49 53FFFFH 29FFFFH 32Kword 83 74FFFFH 3A7FFFH- 32Kword 116
E0000H- 70000H- 300000H- 180000H- 520000H- 290000H- 730000H- 398000H-
EFFFFH 77FFFH 32Kword 14 30FFFFH 187FFFH 32Kword 48 52FFFFH 297FFFH 32Kword 82 73FFFFH 39FFFFH 32Kword 115
D0000H- 68000H- 2F0000H- 178000H- 510000H- 288000H- 720000H- 390000H-
DFFFFH 6FFFFH 32Kword 13 2FFFFFH 17FFFFH 32Kword 47 51FFFFH 28FFFFH 32Kword 81 72FFFFH 397FFFH- 32Kword 114
C0000H- 60000H- 2E0000H- 170000H- 500000H- 280000H- 710000H- 388000H-
CFFFFH 67FFFH 32Kword 12 2EFFFFH 177FFFH 32Kword 46 50FFFFH 287FFFH 32Kword 80 71FFFFH 38FFFFH 32Kword 113
B0000H- 58000H- 2D0000H- 168000H- 4F0000H- 278000H- 700000H- 380000H-
BFFFFH 5FFFFH 32Kword 11 2DFFFFH 16FFFFH 32Kword 45 4FFFFFH 27FFFFH 32Kword 79 70FFFFH 387FFFH- 32Kword 112
A0000H- 50000H- 2C0000H- 160000H- 4E0000H- 270000H- 6F0000H- 378000H-
AFFFFH 57FFFH 32Kword 10 2CFFFFH 167FFFH 32Kword 44 4EFFFFH 277FFFH 32Kword 78 6FFFFFH 37FFFFH 32Kword 111
BANK(IV)
9 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Bus Operation
Pins CE# OE# WE# RP# DQ0-15* RY/BY#
Mode
Array VIL VIL VIH VIH Data Output VOH(Hi-Z)
Status Register VIL VIL VIH VIH Status Register Data X2)
Read
Identifier Code VIL VIL VIH VIH Identifier Code VOH(Hi-Z)
Page VIL VIL VIH VIH Data Output VOH(Hi-Z)
Output Disable VIL VIH VIH VIH High-Z X2)
Program VIL VIH VIL VIH Command/Data in X2)
Write Erase VIL VIH VIL VIH Command X2)
Others VIL VIH VIL VIH Command X2)
Stand by VIH X1) X1) VIH High-Z X2)
Deep Power Down X1) X1) X1) VIL High-Z VOH(Hi-Z)
10 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
11 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
12 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Block Locking
Write Protection Provided
RP# WP# Bank(I) Bank(II) Bank(III) Bank(IV) Notes
Boot Parameter/Main Main Main Main
VIL X Locked Locked Locked Locked Locked Deep Power Down Mode
All Blocks Locked(Valid to operate
VIL Locked Locked Locked Locked Locked
VIH Software Lock Release)
VIH Unlocked Unlocked Unlocked Unlocked Unlocked All Blocks Unlocked
WP# pin must not be switched during performing Read / Write operations or WSM busy (WSMS=0).
Status Register
Symbol Definition
Status
(I/O Pin)
"1" "0"
S.R. 7 (DQ7) Write State Machine Status Ready Busy
S.R. 6 (DQ6) Suspend Status Suspended Operation in Progress/Completed
S.R. 5 (DQ5) Erase Status Error Successful
S.R. 4 (DQ4) Program Status Error Successful
S.R. 3 (DQ3) Block Status after Erase Error Successful
S.R. 2 (DQ2) Reserved - -
S.R. 1 (DQ1) Reserved - -
S.R. 0 (DQ0) Reserved - -
13 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Device ID Code
Pins A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Hex. Data
Code
Manufacturer Code VIL "0" "0" "0" "1" "1" "1" "0" "0" 1CH
Device Code (Top Boot) VIH "1" "0" "1" "1" "1" "0" "0" "0" B8H
Device Code (Bottom Boot) VIH "1" "0" "1" "1" "1" "0" "0" "1" B9H
DC electrical characteristics (Ta= -40 ~85 °C and Flash VCC=3.0V~3.6V, unless otherwise noted)
Limits
Symbol Parameter Test Conditions Units
Min. Typ.1) Max.
ILI Input Leakage Current 0V< VIN< VCC -1 1 µA
ILO Output Leakage Current 0V< VOUT< VCC -10 10 µA
VCC= 3.6V, VIN= GND/VCC, F-CE#= F-RP#=
ISB2 VCC Stand by Current 0.1 6 µA
F-WP#= VCC±0.3V
ISB3 VCC= 3.6V, VIN= VIL/VIH, F-RP#= VIL 5 25 µA
VCC Deep Power Down Current VCC= 3.6V, VIN= GND or VCC, F-RP#= GND±
ISB4 0.1 6 µA
0.3V
Vcc = 3.6V, VIN = VIL/VIH,
5MHz 20 30 mA
ICC1 VCC Read Current for Word F-RP# = OE# = VIH,
F-CE# =VIL, Iout = 0mA 1MHz 4 8 mA
Vcc = 3.6V, VIN = VIL/VIH,
ICC1P VCC Page Read Current F-RP# = OE# = VIH, 5MHz 5 10 mA
F-CE# =VIL, Iout = 0mA
14 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC electrical characteristics (Ta=-40 ~85 °C and Flash VCC=3.0V~3.6V, unless otherwise noted)
15 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC electrical characteristics (Ta=-40 ~85 °C and Flash VCC=3.0V~3.6V, unless otherwise noted)
-Read timing parameters during command write operations mode are the same as during read only operation mode.
-Typical values at Flash VCC=3.3V and Ta=25 °C.
16 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
17 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
3.0V
V CC tVHEL
GND tVCS
V IH
RP#
V IL
V IH
CE#
V IL tPS tPS
V IH
WE#
V IL
V IH 1N914
WE# V IL ta(OE) tOH 3.3kohm
tCLZ tOLZ
V OH High-Z High-Z
DATA Output Valid
VO tPS DUT
V IH tPHZ
CL=30pF
RP# V IL
- After inputting Read Array FFH, it is necessary to make F -CE# “H” pulse more than 30ns (tCEPH).
And after inputting Read Array Command FFH, it is also necessary to keep 30ns to recover before starting read
after WE# rises “H” in case of changing address(es) and F-CE#=“L”.
18 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
VIH
A21 - A2 Page Address Valid
VIL
Address Valid(Voluntary Address)
VIH
A1 - A0 1st Address 2nd 3rd 4th
VIL
VIH
F-CE# ta(OE) ta(OE)
VIL
tCEPH
VIH
OE#
VIL
VIH
WE# ta(AD)
VIL ta(PAD) ta(PAD) ta(PAD)
VIH ta(CE)
High-Z
DATA F3H Valid Valid Valid Valid
VIL
- After inputting Page Read Command F3H, it is necessary to make F-CE# “H” pulse more than 30ns (tCEPH).
And after inputting Page Read Command F3H, it is also necessary to keep 30ns to recover before starting read
after WE# rises “H” in case of changing address(es) and F-CE#=“L”.
- Once Page Read mode is valid, the mode is kept until F-RP# is set to VIL or the chip is powered off.
V IH
ADDRESS Address Valid Address Valid
A21-A0 V IL
V IH ta(AD)
CE#
V IL tDF(CE)
V IH ta(CE)
OE# tBCD
V IL tDF(OE)
tBAD
V IH ta(OE) tBAD
tOH
BYTE# V IL tOLZ
ta(BYTE)
tCLZ tBHZ
DATA V OH High-Z
Output Valid Valid Valid
D7-D0 V OL ta(BYTE)
DATA V OH High-Z
Valid
D14-D8 V OL
ta(AD)
V IH
D15/A-1 Address Valid D15 A-1
V IL
When BYTE# = VIH, CE# = OE# = VIL, D15/A-1 is output status. At this time, input signal must not be applied.
19 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
VIH
ADDRESS Bank Address Valid Address Valid Bank Address Valid
A21-A0 VIL tAH Program Read Status Register Write Read Array Command
VIH tWC tAS
CE#
VIL
ta(CE)
VIH
OE#
VIL tWS tCEP tWH ta(OE)
VIH
WE#
VIL tOEH
tDS
VIH High-Z
DATA 40H DIN SRD FFH
VIL
tPS tDH
VIH
RP# tDAP
VIL
tBLS
VIH
WP#
VIL
tBS tBH
VIH
BYTE#
VIL
VOH
RY/BY#
VOL tEHRL tBLH
20 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
21 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
VIH
ADDRESS Bank Address Valid Address Valid Bank Address Valid
A21-A0 VIL tAH Erase Read Status Register Write Read Array command
VIH tW C tAS
CE#
VIL
tCS tCH ta(CE)
VIH
OE# tW P tWPH
VIL
ta(OE)
VIH
WE# tOEH
VIL
tDS
VIH High-Z
DATA 20H D0H SRD FFH
VIL
tPS tDH
VIH
RP# tBLH
VIL tBLS tDAE
VIH
WP#
VIL
tBS tBH
VIH
BYTE# VIL
VOH tWHRL
RY/BY#
VOL
VIH
ADDRESS Bank Address Valid Address Valid Bank Address Valid
VIL
A21-A0 tAH Erase Read Status Register Write Read Array command
VIH tWC tAS
CE#
VIL tCEPH
ta(CE)
VIH
OE#
VIL tWS tCEP tWH
ta(OE)
VIH
WE# tOEH
VIL
tDS
VIH High-Z
DATA 20H D0H SRD FFH
VIL tPS tDH
VIH
RP# tBLH
VIL tBLS tDAE
VIH
WP#
VIL
tBS tBH
VIH
BYTE# VIL
VOH tEHRL
RY/BY#
VOL
22 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
23 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BYTE#=VIL
(A6-A-1) VIH 00H 01H-FEH FFH Valid Valid
BYTE#=VIH 00H 01H-7EH 7FH
(A6-A0) VIL ta(CE)
tWC tAS tAH
VIH
CE#
VIL
tCS tCH ta(OE)
VIH
OE#
VIL tWP tWPH tOEH
\
VIH
WE#
VIL
tDH
VIH High-Z
DATA 41H DIN DIN DIN SRD DOUT DOUT
VIL
VOH
RY/BY#
VOL tDS tWHRL
24 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
25 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
ADDRESS VIH
Bank Address Valid Bank Address Valid
A21 - A0 VIL
tAH Read Status Register
VIH tAS
CE#
VIL
tCS tCH ta(CE)
VIH
OE# tWP
VIL tOEH
ta(OE)
VIH
WE#
VIL Suspend Time
S.R.6,7=1
VIH High-Z
DATA B0H SRD
Valid
VIL
VIH
RP#
VIL tBLH
VIH
WP#
VIL
VOH
RY/BY#
VOL
ADDRESS VIH
Bank Address Valid Bank Address Valid
A21 - A0 VIL
tAH Read Status Register
VIH tAS
CE#
VIL tOEH ta(CE)
VIH
OE# tCEP
VIL
tWS tWH ta(OE)
VIH
WE#
VIL Suspend Time
S.R.6,7=1
VIH High-Z
DATA B0H SRD
Valid
VIL
VIH
RP#
VIL tBLH
VIH
WP#
VIL
RY/BY# VOH
VOL
26 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
ADDRESS VIH
Bank Address Valid Address Valid Bank Address Valid Address Valid
A21 - A0 VIL
tWC ta(CE) ta(CE) ta(CE)
VIH
CE#
VIL tCH
tCS
VIH
OE#
VIL
tWP ta(OE) ta(OE) ta(OE)
VIH
WE# ta(AD) ta(AD) ta(AD)
VIL
VIH High-Z
DATA 90H ID Dout ID
VIL
AC Waveforms for Status Register Read Operation with BBR(Back Bank Read)
Change Bank Address Return Bank Address
27 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Write 40H
Write 41H
Write Address,
n=0
Data
NO NO NO
Write n = 7FH?(Word)
SR.7 = 1? n = FFH?(Byte)
BOH?
YES YES
YES
Full Status Check Status Register
If Desired Read
Suspend Loop
Write 20H
NO Block Erase
SR.5 = 0?
NO NO Error
Write
SR.7 = 1?
BOH? YES
YES NO Program Error
YES SR.4 = 0?
(Page Program)
Full Status Check
If Desired YES
Suspend Loop
NO Block Erase Error
SR.3 = 0?
Write D0H (Block Fail)
Erase
Completed YES
YES
Pass
(Block Erase, Program)
28 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Load NO NO
Finished? S.R. 7=1?
YES YES
Single Data Load
NO Erase/ Program
To Page Buffer S.R. 6=1?
Completed Finished
YES
Write FFH
Read NO
Write 0EH Finished?
YES
Status Register
Read
29 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
50H
Clear
Status Register
Read
Read/Standby State
Status Register
(Random Read Mode)
70H 70H
90H
Read
Back Bank Read State Device Identifier
FFH
90H
Read Array Read Array
(Random Read)
Change Bank FFH (Random Read)
Address
Others 3)
D0H WD D0H
Setup State 55H 74H F1H 0EH 41H 40H 20H A7H
B0H B0H
Program & Erase &
Ready Verify Verify
D0H D0H
Read Read
Status Register Status Register
Change
Bank Address
Read State with BGO Read
Status Register
Read Array
Suspend 70H
(Random Read)
State
1) In case of Page Read, F3H is used instead of FFH in Operation Status (F-WP#=VIH).
2) Once Page Read mode is set, Page Read mode is kept until power off or F-RP# is set to VIL.
3) After setting up Clear Page Buffer, D0H enables to clear Page Buffer.
4) To access any bank during Erase All Unlocked Block results Status Register Read.
Although Read Status Register Command and Read Array Command can be issued under Suspend State,
output data make no sense.
30 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Read
Read/Standby State Status Register
(Random Read Mode)
70H 70H
90H
Read
Back Bank Read State Device Identifier
90H FFH
Read Array Read Array
(Random Read) Change Bank (Random Read)
FFH
Address
55H 74H
Setup State F1H 0EH 41H 40H 20H
Wdi
Other D0H WD
I=0-127 D0H Other
Internal State
B0H B0H
Program & Erase &
Ready Verify Verify
D0H D0H
Read Read
Status Register Status Register
Change Bank
Address
1) In case of Page Read, F3H is used instead of FFH in Operation Status (F-WP#=VIL).
2) Once Page Read mode is set, Page Read mode is kept until power off or F-RP# is set to VIL.
3) BA, BA#: Block Address, Block Address# (Shown in Command List(F-WP#=VIL) in detail).
4) After setting up Clear Page Buffer, D0H enables to clear Page Buffer.
31 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Package Dimension
48P3R-C
32 Rev.1.3_48a_bezz
Renesas LSIs
M5M29KB/T641AVP
67,108,864-BIT (8,388,608-WORD BY 8-BIT /4,194,304-WORD BY 16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
REJ03C0024
© 2003 Renesas Technology Corp.
New publication, effective April 2003.
Specifications subject to change without notice
This datasheet has been download from:
www.datasheetcatalog.com