United States Patent [15] 3,689,899

[451 Sept. 5, 1972

Franaszek
[54]‘ RUN-LENGTH-LIMITED VARIABLE [57] ABSTRACT
LENGTH CODING WITH ERROR
PROPAGATION LIMITATION ~
This is a 'run-length-limited, variable-length coding
scheme which reduces the implementation needed to
7 [72] Inventor: .Petér A. Franaszek, Mount Kisco, - _ perform encoding and decoding functions and which
‘NT ' limits the propagation of framing errors caused by in
[73] vAssignee: International Business Machines correct coding or faulty bit detection. All code .words
’ . Corporation, Armonk, NY. utilized in this scheme are constrained to have distinc
tive word-ending bit sequences. Word-ending tests are
[22] Filed: June 7, 1971 performed repeatedly at strategic points in the bit
[21] Appl. No.: 150,317 stream in order to detect bit patterns that may denote
word endings, and framing decisions are based upon
these tests. Decoding functions are suspended while
[52] US. Cl ............. ...... ..340/172.5, 340/146.1 D each new code word or frame is being serially entered I
. [51] Int. Cl. ....................... ..G08c 25/00, G06f 11/00 into the input register for decoding. Where misframing
[58] Field of Search ........... ..340/172.5, 146.1 D, 347 occurs due to the presence of an erroneous bit in a
code word, the propagation of such a framing error
['56] References Cited through subsequent words is limited by the fact that
~ subsequent word-ending tests are performed indepen
1 ' UNITED STATES PATENIS ,
dently of the framing decisions that preceded them,
3,626,167 12/1971 Guck et al. .......... ..340/347 X and also due to the fact that the average code word
3,576,947 5/1971 Kruger .............. ..340/146.1 X length is much less than in a fixed-length code system.
3,457,562 7/1969 Fano ................. ..340/347 DD .> Synchronism is quickly restored upon detecting a valid
3,456,234 7/1969 Glasson ................ ..340/146.1 word-ending bit pattern following the erroneous bit.
3,444,522 5/1969 Polhemus ............. ..340/172.5 While the code words are of variable length, the rate
3,336,467 8/1967 Frey ..... .. ........... ..340/ 146.1 X of data transmission is constant due to a ?xed ratio
3,208,049 9/ 1965 Doty et al ............. ..340/1 72.5 between the number of original data bits and the cor
3,016,527 1/ 1962 Gilbert et al ............. ..340/347 responding encoded data bits.
3,05 1 ,940 8/1962 Fleckenstein ............ ..340/347

Primary Examiner—Paul J. Henon 22 Claims, 14 Drawing Figures

Assistant Examiner-Ronald F. Chapuran
Attorney-l-lani?n and Jancin and C. P. Boberg

LEGEND
= MAXIMUM ENCUDED WORD LENGTH
:RA‘HO 0F EXDODED BITS/ORIGINAL B115,
1! WHERE N ANDG ARE LEAST INTEGERS.
L=LEl1GTH 0F ORIGINAL Bll STRING (VARIABLE)

ASSOCIATE
W BITS

“LN
w, -

(DECODING)

"77'7" “ bscoosn'b'i
._._‘:§.[w
,. ,Hv
ASSOC. ENCODED ORIGINAL L ' ‘55%’ E
mzmonv wonos worms
CONTROLS a. o
---~vans»~'~~- ans ’

m a a
an
m use inn
8, ss m4

m2 m4 DATA are. DATA REG.

52 , (ENCODING) (DECODING)
mo
§un DEC/f2‘
Eu
mourn
8115
E12 50R
 PATENTEDSEP 5 I972 3.689.899
SHEET 010E I3

LEGEND
W: MAXIMUM ENGODED WORD LENGTH
_N_: RATIO OF ENOODED BITS/ORIGINAL BITS,
‘ ' _ 0 WHERE M AND G ARE LEAST INTEGERS.
L‘ILENGTH OF ORIGINAL BIT STRING (VARIABLE)

w BITS
05 E2
E6 I r—E9 . '54
ASSOCIATE Assoclmj SHIFT
0R I
6/ OREGIITNAL
I
‘ I_— STREAM
204A ARG. REG. ARG. REG. I
(DECODING) (ENCODING) OR
( I
I DECODIED 0:0 E3 HO
ASSOC. ENCODED ORIGINAL L /AmCAQIWE
MEMORY wORDs WORDS 2O
CONTROLS . aw . ORIG. aw
III BITS ———--——- BITs—>- WORD T
N LENGTH

E I 22 , A _ 2_6 . 46»\ G __H

4/s49s\ READ ,’ 5 _ III & 1061 I

82 OR OR L9e 104’ 6 "TE? v244/ G 04 G h.‘

E502
IT E704
I DATAIT REG. DATAIN REG. ‘ m6 7
'4 52, (ENCODING) (DECODING) - E
SHIFT DECODE
4BITS
44
J SHIFT
.
' 7 6 ED G \278 06
5400050 I
BITS 180A ENCODED D5 DECODED
‘ EI2 EOR EOR ~32o
DETECTOR DETECTOR -
FINAL FINAL
WORD 132 522 WORD
ENCODED I _OR I DECODED
I84 RESET OR

END ' N
FF Ff 44
I 0 I 186
I86“ / ' - ' INVENTOR

I EIIIII3 I PETER A. FRANASZEK

' I92 END 524 ENDI I'm BY 2

H04 . FIG 5 I ATTORNEY
 PATENTEDSEP 5 I972 3.689.899
SHEET 03 [IF 13‘

H6. 2 START?. } E1
ENCODING PROCEDURE SET LENGTH'CTR=QNIE
LEGEND REsET END FF T0 0.
'w=MAxIMuM ENCODED WORD ‘LENGTH E2. I W
—2—=RATIO 0F ENCODED BITS/ORIGINAL .sRIFT ARG. REG. oNE BIT f
_ BITS, WHERE N AND a ARE ' 53 I
LEAST INTEGERS INGATE ONE BIT T0 ARC. REC.
>L= LENGTH OF ORIGINAL BIT STRING OECREMENT LENGTH CTR. BY I .
(VARIABLE). E4 I
Is LENGTH cTR. ATO?
I M5 55 NOI
SET MATCH INDICATORS
I E6
AssocIATE 0N QM! BITS
sToREII IN ARG. REG.
I ' ET
READ LENGTH INDICATIOMLITO LENGTH CTR.
I - READ NATGIIING CODE WORD To DATA REG.
I . sETENII KFEFETTII IF EOR IS READ OUT; OTHERWISE
END FF AT 0.
I E8
SET INPUT BIT CTR. T0 oz.
SET OUTPUT BIT CTR. TON.

I E12 I I
GIITGATE ONE BIT FRoN DATA REG. SHIFT ARO. RECEONE BIT
E13 I EIO
' SHIFT DATA REG.0NE BIT. INGATE ONE BIT TO ARCREO.
DECREMENT oIITPIIT BIT GTR. OECREMENT INPUT BIT CTR. ’
DECREMENT LENGTH CTR.
E14 I ~ I EII
Is OUTPUT BIT CTR.ATO?
I Is INPUT BIT cTR. ATO?
INPUT BIT cTR ' AT 0-—-N0 0R YESISS Y ‘
OUTPUTBITCTRATOj I i \134 < E5 "0
a [138 136
E15 I I
IS LENGTH GTR. AT 0 ?
E16 M0 IEsI_ 1 E17
SET INPUT BIT CTR. TO(!
SET OUTPUT BIT CTR. TON IIAS FINAL WORD BEEN ENCODED ?
I NO YES .
 PATENTEDSEP 5 I972 9.699.999
‘SHEET on or 13

START D1 F“
SET INPUT BIT CTR.T0 N.
FIG. 3 SET OUTPUT BIT CTR. TO d.
RESET END FF TO 0.
DECODING PRCCEDURE SET LENGTH CTR. ACCORDING
TO OUTPUT 0F LOGIC CIRCUITRY
I02.
GATE W BITS FROM INPUT REG.
TO ARGUMENT REG.
LEGEND SET MATCH INDICATORS.
w; MAXIMUM ENDODED I05
worm LENGTH ASSOCIATE ON W BITS STORED IN
ARGUMENT REG.
l=RATIo OF ENCODED I04
'1 BITS/DECODED BITS,WHERE v
N AND a ARE LEAST INTEGERS READ MATCHING WORD TO DATA REG.

I 05 . , 0a

OUTGATE ONE BIT FROM DATA REG. SHIFT INPUT REG. oN BIT
I O6 n9
SHIFT DATA REC; ONE BIT. INGATE ONE BIT TO INPUT REG.
DECREMENT OUTPUT BIT CTR. DECREMENT INPUT BIT CTR.
DECREMENT LENGTH CTR.
I D? . 010
IS OUTPUT BIT CTR. AT 0 ? ISINPUT CTR. ATO? I
___IIo YES. . 288_ ’_T__‘IYEs N0
304
'- zany-0R
INPUT BIT CTR. ATO
r—-0UTPUT BIT CTR.ATO

I 011
= ' IS LENGTH COUNTER ATO? .

_ [m ml
012 I ' . , 01s

sET INPUT BIT CTR. TON ,

SET OUTPUT BIT Cm To a HAS FINAL WORD BEEN DECODED .
. YES NO]

END
PATENTEDSEP 5 I972 3.6851899
SHEET OBUF 13

2
o; . wxz0ao4m
k
H
E
:N
E
T

mommmoli
and
2i.9
E
m
2m
gm\ .
mag
“Kb
_
w
5
9Eon
gum
2%
Na:M
2w
2%:5
a
2
2
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momm83mm ad
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.

1:mm11mm.
1%02E
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,
 PA'TENIEDSER 5:912 3.689.899
SHEET [17 OF 13

CODE CONVERSION TABLE FOR (1,8) CODE

ORIGINAL
ENCODED WORDS OR DECODED L
' WORDS

20

01. VA01 X VAX10. OU 0 XVA10 X.1O 0 1 ,O 0

/

X= OONT CARE

wNd 932
a:
:
10. 1XVAO 110 0

0 o o 0 0 o \L DUMMY WORD
(READ OUT IF IIO
~—.— 6BITS—+5BITS* MATCH FOUND
DURING DECODING)
24/ 26]

CODE CONVERSION TABLE FOR (2,7) CODE _

W
E

10N 010mPM01 VA XDO 10DIC104W InVAR10Dv “VA.01 8 DL10

? w
V A 0 1v
E ,C Du s
FIG. 7 3NED

X=DONT CARE

01 VA01 BD
VA O, 0.1
|=|
6000B.

Mu01 _.___I_' DUMMY WORD

ZJ
(READ OUT IF NO
MATCH FOUND
DURING DECODING)
221 24]‘ I 26!
 PAIENIEIISEP 5'97? 3.689.899
SHEET UBIIF I3

FRAMING

INPUT
REILEIfEMCE
0 N .
REGISTER w = 9 BITS
200 I
' EM000E0
BIT 10 s 7 e 5 4 3 2 1 <—— BM
PosmoM/ - STREAM
NUMBERS

I 'I I I I I 215 w- M X!
212/ OR I OR \ I - A MMM w0R0 LENGTH
208 . I 210 ‘
I
210/ a 214v va.

A, _\B \FRAMING LOGIC

FOR < 1,0) CODE
I I
I I
218
\ /202
a a

I I
OR OR
]_1 Y . sEI LENGTH COUNTER
/T0 2 /5 FRAME LENGTH

I D ENUIIBEEDRBIIS
C 0 ' I I TH u IT R
TO BE READ 0ME\*~ 4 2 1 & 52° N E

FRAMING DECISION TABLE FOR (1,8) CODE

FRAME LENGTH COUNTER
ID SETTING
LENGTH DECIMAL
6 I

LA'QNCDO 4
2
?
1
0 ‘
0
 PATENTED 8E1’ 51912 9.699.899
SHEET 09 0F 13

FRAMING '

INPUT REG. 20o

REFEWCE w - M'AXIMUMEWORD LENGTH
> \ w= 8B1TS
an I
POSITION 1o 9 a 1' >6 5 4 3‘ 2 1
NUMBERS I
- ‘ 511000130

1 F j /230 an STREAM
OR OR OR 226 224
L FRAMING LOG1C
I I E: FOR(2,7)CODE
236 228 /
'l
a a a
/. 202
240 A’ BA -c -/

242\ 9 OR OR

‘__
220V 6 To‘
SET LENGTH COUNTER T0
LENGTH COUNTER 34\ 1/2 FRAMELENGTH
NUMBER OF DECODED 4 2 1
ans TO BE READOUT

FRAMING DECISION TABLE

FOR>(2,7)CODE
LENGTH COUNTER
A B C 55:31.2 SETTING
DECIMAL ' BINARY
0 0 0 8 4 1 0 0
0 0' 1 6 5 0 1 1
0 1 0 4 2 0 1 0
1 0 0 2 1 0 0 1
1 0 1 6 3 0 1 1
PATENTED 3f? 5 I972 - 3 .6 8 9,8 9 9
sum 1001 13

FIG. 10
EXAMPLE 1=(1,8) CODE
CORRECTSEQUENCE=101010010100001000'"
CORRECT FRAMING= ' _ E

ERROR' ERRORS
' F1
DETECTED SEQUENCE: 10001 00 -1 1 0 0 0 00 1 0 0 0""
ACTUAL FRAMING= L 4*

SELECTED BIT POSITION NUMBERS’ SH H

. 1
FRAME LENGTH‘ 109 a 1 e s 4 s 2 1 1111mm
9BIT5 0000000000 T0
1 0000000001 T1
INITIAL 000000001012
INGATING 00 0 0-0 00 1 0 0 T3
OPERA-HON 0000001000 T4
1 000001000115
(DECODING SUSPENDED) 0 0 0 0 1 O 010 1 0 T6
0001000100 T7
0010001001 10
SBITS 0100010011 T9
* - ~1000100110- T10
(DECODING SyUSPENDED) 0 0 0 1.0 0 I 1 0 0 w
30115 0010011000 T12
* 0100110000 113
(DECODING S‘USPENDED) 1 0 0 1 1 0 O 0 O 0 H4
00113 0011000001 115
0110000010 T16
1100000100 T17
(DECODING SUSPENDED) 1 0 0 0 0 0 1 0 0 0 T18
000001000 T19
00001000. T20
6B|TS 0001000 T21

1
FRAMING REFERENCE
POINT
PATENTEUSEP‘SIQYZ , 3.689.899
‘SHEET 1111f 13

FIG."
EXAMPLE 212,?) com;
CORRECTSEQUENCB1000100100000001000100~--
CORRECT FRAMING: l -L -L .1 .

'ER‘ROR ' ERP‘IOR

DETECTEDSEQUENCE10011001000100010001C0'~"
ACTUAL FRAMING= L "L -- -; 1

SELECTED B” POSITION NUMBERS SHIFT

FRAME LENGTH 10987654321|NTERVAL
0011s 000000000010
1* 000000000111
INITIAL 000000001012
INGATING 0000000100T3
QPERA‘HQN 0000001001 T4
- 000001001115
(DECODINGSUSPENDED) 0000100110 T6
000100110011
0011s 001001100110
010011001019
1001100100110
- 0011001000111
DECODING SUSPENDED 0110010001‘ 112
1100100010113
1001000100114
0010001000115
SBITS 0100010001T16
I 1000100010111
0001000100110
oscoome SUSPENDED 0010001000 119
0100010001120
1000100010121
4011s 0001000100122
1 001000100 123
DECODING SUSPENDED 01000100 T24
1 1000100 125
40115 000100 120
1
FRAMING REFERENCE
POINT
PATENTEDSEP 5 I97? 3. 689 .899
SHEET 12oF 13

F|G.12 20
\ /
\

ASSOCIATIVE | ASSOCIATIVE
MEMORY MEMORY
CONTROLS (Fa-STATE)
"_-'_

l l ' .
MISMATCH

96
____ '

/
MI FIF A6
r
100 l 260
u a 8!

| READ ___
? 102/
. -/

1W8‘ a.260 I
READ > _____

Z‘; J if i
2/
10 J l
T
MISMATCj/
l I 1 90
MI F F f-86
|

100* a a. 460
102
READ \ _____

N0 MATCH ____
- READ
84L “98 266 DUMMY woao

smrs READ
 3,689,899
1 2
RUN-LENGTH-LIMITED VARIABLE-LENGTH problems which result whenever the bit pattern of a
CODING WITH ERROR PROPAGATION code word is incorrectly represented, due to faulty bit
LIMITATION detection, for example. To meet this problem, it has
BACKGROUND OF THE INVENTION been customary to rely upon the statistical probability
that a true word-ending will be found by chance as the
Various ways have been proposed for increasing the decoding progresses, without an unduly extended
density with which data can be recorded on disks or propagation of the framing error through the succeed
similar media in data utilization systems or the rate at ing portions of the bit stream. Variable-length coding
which it can be reliably transmitted through existing schemes which have been designed to limit error
channels. One such technique is run-length-limited 10
propagation upon a statistical probability basis have
coding, which requires that each 1 in a coded bit been found unsatisfactory for a number of reasons.
sequence must be separated from the nearest adjacent First, they do not work well in practice, since many, if
l by a number of 0’s at least equal to a minimum quan not most, data bases will not lend themselves to the
tity d in order to insure freedom from inter-symbol in
terference during recording or transmission but not ex 15 statistical approach to error propagation limitation.
Under some conditions, synchronism may never be
ceeding a maximum number k which is required for regained without stopping and restarting the system.
self-clocking purposes. Such codes also may be Secondly, such codes do not have the run-length
referred to as “dk-limited” codes. The present inven limited constraints which have been found to be highly
tion is directed particularly to data processing systems 20 desirable for achieving ef?cient data transmission and
which utilize this type of coding. recording operations. For these reasons, and others,
Prior run-length-limited coding systems have been the statistical approach to error propagation limitation
designed on the assumption that the information which is not generally regarded with favor.
is being recorded or transmitted will be handled in
processable units or “words” of ?xed length. Coding 25 SUMMARY OF THE INVENTION
efficiency requires that these ?xed-length words be of An object of the present invention is to provide a
substantial length, such as a standard 8-bit “byte”, for
example, shorter words being much less efficient. On novel data encoding and decoding process that will
the other hand, the complexity of the encoding and take advantage of the savings in processing time and
decoding apparatus increases at a very great rate ( i.e., 30 cost of equipment which can be realized by the com
exponentially) as the word length increases. As one bined use of run-length-limited coding and variable
aspect of the present invention, it has been found that length coding. It is a further object to accomplish this
the desired coding ef?ciency can be achieved without without incurring the disadvantage of slow or unrelia
unduly complicating the design of the encoding and ble performance and without sacri?cing the constant
decoding apparatus if the encoded information is han 35
data transmission rate which characterizes ?xed-length
dled in the form of variable-length words rather than coding systems.
?xed-length words. The maximum word length To explain how the present system achieves a high
required for achieving a given degree of data density in rate of data handling without a sacri?ce of reliability, it
a variable-length system is considerably less than the may be observed ?rst that decoding of variable-length
word length needed in a ?xed-length system having the 40 code words can be speeded up if the framing test has to
same data density, and the encoding-decoding equip be performed only once per code word, instead of
ment in the variable-length system does not even ap being performed repeatedly upon each code word or
proach in complexity that which is needed in a ?xed argument as it is being built up by increments prior to
length system. decoding. This mode of operation requires that the
The use of variable-length coding may present other 45 frame length be determined only at the time when the
problems, however. There being no fixed “frame complete code word is available and at about the same
length” or code word length in such a system, special time that the actual decoding of that word takes place.
measures must be taken to insure that the encoded bit The frame length determines the number of shift opera
stream is subdivided or “framed" at the proper places tions which the input register must perform in order to
to demarcate the respective code words therein. One 50 bring the bits. of the next succeeding code word into
prior system which has been proposed for this purpose proper position for decoding. The correct code word
requires the use of special marker bits, one of which is length can be derived from the decoded information it
inserted as a pre?x ahead of each variable-length code self only if the code word used as an argument was free
word that is to be decoded in order to mark with cer~ of error. If any of the bits in that word had been errone
tainty the beginning of that word. This code word, with 55 ously encoded or erroneously detected prior to decod
its pre?x bit, then is entered bit-by-bit as an argument ing, no reliable indication of the code word length can
into a shift register, and as each new bit enters the re be derived from the decoded information. Con
gister, a test is made to see whether the bit pattern that sequently, the system would be likely to make an incor
has been built up behind the marker bit can be recog rect framing decision if it relied upon such information,
nized as a complete code word by a table lookup and once a framing error of this kind is made, it will
procedure. This means, in effect, that a decoding tend to be propagated in an unpredictable fashion
operation must be attempted upon each new fragment through succeeding code words or frames. Such an out
of the argument as it is being incrementally built up in of-frame condition ordinarily would require stopping
the argument register, until a match is found. A decod
65 and restarting the transmission, thereby wasting time.
ing process of this kind is relatively slow. A feature of the present invention is that it enables a
A further disadvantage of variable-length coding, as ‘system of the kind just described to function in a relia
currently practiced, is its susceptibility to framing ble manner despite even very serious errors in the code
 3,689,899
3 4
representations of the data words. Any framing error ing decision in order not to delay its processing of the
which is caused by a faulty code bit representation will succeeding data. Any out-of-frame condition which
have only a limited effect upon subsequent framing may develop as the result of these decisions, however,
decisions made by the system.- Instead of being will be corrected when the next word-ending test is
propagated for an inde?nite interval and in an unpre satis?ed, and no further propagation of the framing
dictable fashion through the succeeding parts of the bit error can take place. This limits the effect of misfram
stream, the out-of-frame condition will be ‘propagated ing to a tolerable amount.
through only a very limited portion of the stream, The word-ending tests described above are useful not
usually through one or two words only. Moreover, only to limit the propagation of any misframing caused
since the average code word length is relatively small, 10 by coding errors but also to determine the coding “
word-endings occur with relative frequency, and this, state”. Some codes of the class herein contemplated
too, tends to limit the effect of error propagation. are “state-dependent”, which is to say that the coding
As one aspect of the invention, there is proposed of any particular word depends upon the terminal state
herein a new class of run-length-limited, variable of the immediately preceding code word, this being
length codes having a constant ratio of encoded bits to done in order to avoid violating the desired run-length
decoded bits and having novel constraints which cause limiting constraints when the code words are con
each code word to terminate in a selected one of catenated. The number of 0’s which intervene between
several prede?ned word-ending bit sequences, no other the last 1 in the preceding code word and the first 1 in
word-terminating sequences being permitted. In one 20 the current code word must be in the range of values
such coding system, for example, each code word is at from d to k, inclusive. Some of the codes described
least four bits long and must end in a string of not less herein are state-independent, meaning that every word
than two and not more than three consecutively posi may be encoded from the same encoding table without
tioned O’s. As each successive portion of the detected reference to any other code word, and all such code
bit stream is presented for decoding, certain word-end 25 words may be freely concatenated in any desired
ing tests are made at strategically located points within fashion without violating the established (d,k) con
the series of bits presented. When a pattern of bits straints. Other codes of this class, which are state-de
identical with one of the permissible word-terminating pendent, require that each word be encoded from a
sequences is found, a satisfaction signal is generated for selected one of several encoding tables according to
that group of bit positions. Several such tests may be 30 the terminal state of the preceding code word. This
performed simultaneously upon different parts of the restriction also may apply in some instances to the
bit series in an effort to locate any sequence of bits decoding process as well. The type of word-ending test
whose pattern of 1's and O’s may indicate a word-end which is proposed herein to limit framing error
ing point. Depending upon the outputs of these tests, propagation may serve also to identify the current cod
the system decides where to divide the hit series for 35 ing state for selectively decoding and/or encoding each
decoding purposes and how many bits are to be word in accordance with the previous word ending.
brought in for the next word-termination or framing The foregoing and other objects features and ad
test. Each framing test is made concurrently with a vantages of the invention will be apparent from the fol
word-decoding operation, as a phase of that operation, lowing more particular description of a preferred em- '
so that it adds nothing to the time otherwise required bodiment of the invention, as illustrated in the accom
for decoding. Once a framing decision is made, all panying drawings.
framing and decoding functions then are suspended
until the number of succeeding bits indicated by the DESCRIPTION OF DRAWINGS
framing decision has entered the decoding argument 45 FIGS. 1A and 1B constitute a general circuit diagram
register and has been properly positioned therein for of an illustrative encoding-decoding system embodying
decoding. No intermediate framing tests need be made, the principle of the invention, this particular arrange
thus saving considerable time. ment being suited for the processing of state-indepen
This framing technique simultaneously checks the bit dent codes.
stream at many different points, not just at one place, 50 FIG. 2 is a general ?owchart of an encoding
and it forces the system back into synchronism when procedure which can be executed by the system shown
ever the conditions of any framing test are satis?ed. It in FIGS. 1A and 1B.
has the further advantage that all of the information FIG. 3 is a general ?owchart of a decoding procedure
needed for making correct framing decisions is con which can be executed by the system shown in FIGS.
tained within the code words themselves, as they come 55 1A and 1B.
from the encoded data base. No marker bits or other FIG. 4 is a circuit diagram of an encoding clock or
extraneous information need be added. When perform pulse generator which furnishes timing pulses for the
ing each word-termination test, the system in a sense encoding functions performed by the system of FIGS.
forgets what it did previously and treats each new series 1A and 18.
of bits as though they occupy the leading positions of a FIG. 5 is a circuit diagram of a decoding clock or
new bit stream. It is possible, of course, for the system pulse generator which furnishes timing pulses for the
to receive a false indication of a word ending if a set of decoding functions performed by the system of FIGS.
bits not at the end of a word but resembling a permissi 1A and 1B.
ble word-terminating set happens to occupy the posi FIGS. 6 and 7, respectively, are representations of
tions at which the word-ending test is then being per 65 code conversion tables utilized by a system of the kind
formed. Moreover, if none of the word-ending tests is shown in FIGS. 1A and 1B for the performance of en
satisfied, the system has to make some arbitrary decod coding and decoding operations in dk-limited, variable
 3,689,899
5 6
length coding systems wherein the ( d,k) constraints are convenience of processing and has no necessary rela
( 1,8) and( 2,7), respectively. tionship to the intelligence that is being conveyed by
FIGS. 8 and 9, respectively, are diagrams of the the bit stream. That is to say, no attempt is made herein
framing logic circuitry utilized by the system shown in to frame the bit stream so that the code group within
FIGS. 1A and 1B for making the framing decisions with each frame will de?ne an individual character or other
respect to dk-limited, variable-length codes in which readily identi?able unit of numerical or textual infor~
the( d,k) constraints are( 1,8) and ( 2,7), respectively. mation.
FIGS. 10 and 11 are tabular diagrams showing the The code conversion tables shown in FIGS. 6 and 7
framing operations that are performed by the present illustrate the nature of the coding scheme which is util
system upon specimen code trains in the ( 1,8) and 10 ized herein. The table shown in FIG. 6 is designed for a
( 2,7) coding systems, respectively. run-length-limited code in which d=l and k-——8. That
FIG. 12 is a diagram of the associative memory con shown in FIG. 7 is designed for a code whose run
trol circuitry. length constraints are #2 and k=7. Considering the
FIG. 13 is a fragmentary circuit diagram of a table of FIG. 6, as an example, it is seen that according
modi?ed encoding-decoding system designed to handle to the (l,8) code, each time a bit sequence 00 is en
state-dependent codes. countered at the point which marks the beginning of a
word in the original bit stream, the 00 bit string is en
DETAILED DESCRIPTION OF PREFERRED coded into the word 010. As another example, if the bit
EMBODIMENT sequence 1000 is encountered immediately following a
20
FIGS. 1A and 1B, in conjunction with the clock cir word beginning point, it will be encoded into the word
cuitry shown in FIGS. 4 and 5, illustrate the essential 101000. In each instance it will be noted that there are
parts of an apparatus which is designed to perform en~ three encoded bits for two original bits, this 3/2 ratio
coding and decoding functions in accordance with the being constant for the ( 1,8) code. Similarly, in the case
invention. Exemplary codes which may be processed 25 of the (2,7) code, the ratio between the numbers of en
by a system of this kind are represented in the code coded bits and original bits is 2/l. In general, for any
conversion tables of FIGS. 6 and 7. All such codes have given code system which is constructed on the princi
the following characteristics in common: ples of this invention, the ratio of encoded bits to
a. They are run-length-limited codes in which the original bits remains constant at N/a, where N and a
succeeding l’s of each encoded bit sequence are 30 are the least integers expressing that ratio. ( These two
separated by no fewer than d and no more than k O’s, symbols have the same meaning herein that they do in
the choice of d and k depending upon the speci?c code the inventor’s published article, cited above.)
that is being used. I One signi?cant fact that may be noted with regard to
b. The coded information is processed in code code conversion tables that are constructed according
groups or code words of variable length, and the to this invention is their very small size. Thus, in the
lengths of the encoded words have a constant ratio to case of the ( 1,8) code, FIG. 6, the entire code dictiona
the respective lengths of their corresponding original ry includes only 16 code words, whose lengths vary
( or decoded) bit strings, thereby insuring a constant from 3 to 9 bits, in multiples of 3. In the case of the
data transmission or data recording rate. ( 2,7) code, FIG. 7, the code dictionary includes only 7
0. Each encoded word (if it has been properly en code words with lengths varying from 2 bits to 8 bits, in
coded and detected) will terminate in one of several multiples of 2. If information were to be encoded with
distinctive bit sequences which can readily be recog an equivalent bit-per-symbol value in a run-length
nized as a word ending in order to establish a framing limited coding system having ?xed word lengths, the
point in the encoded bit stream. size of the code dictionary would increase enormously
45 ( in orders of magnitude) due to the relative inflexibility
The present description is concerned more with the
practical implementation of procedures whereby infor of coding in a ?xed-length, run-length limited system.
mation is encoded and decoded according to the above This would greatly increase the complexity of the ap
principles than it is with theoretical factors underlying paratus needed for table lookup operations or
the formation of the code conversion tables them 50 equivalent encoding and decoding functions. As men
selves. However, some of the considerations which un
tioned in the above-cited article ( page 380), a (4,9)
code has a code dictionary of 512 words in a ?xed
derlie the design of code conversion tables for use in
length format but only six words in a variable-length
the present type of system will be explained herein. For format.
a more complete treatment of the mathematical theory, The code tables are represented in FIGS. 6 and 7 in
reference may be had to the article entitled “Sequence the form that they would have if stored in the associa
state Methods for Run-length-limited Coding”, by P. A. tive memory 20, FIG. 1A, which contains three-state
Franaszek, in the July 1970 issue of the IBM Journal of memory cells in its sections 22 and 24 wherein the en
Research and Development, pages 376-383. coded words and original words, respectively, are
Before commencing the detailed description of the stored. The symbol “X” in FIG. 6 and FIG. 7 represents
illustrated system, an explanation will be given of the a three-state memory cell in its third or “don’t care”
term “code word” or “code group” as used herein. A state, to which it is set when it is not storing any of the
“word” is considered to be any individually processa signi?cant bits of a word. Each storage cell in the
ble sequence of bits, Le, a string of bits, of whatever memory sections 22 and 24 is settable to one of the fol
length, that can be handled as a unit by the system. For lowing three states, as desired:
65
the purpose of this invention, the manner in which a 1. A binary 1 state, in which the cell will respond
stream of bits is subdivided or “framed” into its con with a mismatch signal if interrogated by a 0 bit but will
stituent words or bit strings is determined entirely by generate no output if interrogated by a 1 bit.
 3,689,899
7 8
2. A binary 0 state, in which the cell will respond tion L is read out of memory section 26 and is entered
witha mismatch signal if interrogated by a 1 bit but will into a length counter 34, FIG. 1B. Thus, the length of
generate no output if interrogated by a 0 bit. the original matching word now is registered in the
3. A “don’t care” state ( indicated by “X”, FIGS. 6 length counter 34.
and 7) in which the cell is incapable of generating a There follows a period during which the code word
mismatch signal regardless of whether it is interrogated stored in the data register 32 is serially read out
by a l or 0 bit. In this state the cell is effectively masked
therefrom. Concurrently with this action, new bits from
from interrogation. the original bit stream are serially entered into the ar
The speci?c construction of the associative memory gument register 30, the contents of which are progres
20 with its three-state cells is not disclosed in detail 0 sively shifted leftward in order to accommodate the
.

herein. Such memories are well known. Reference may newly entered bits. It is necessary that the number of
be had, for example, to U.S. Pat. No. 3,543,296 issued bits read out of the data register 32 be equal to the
on Nov. 24, 1970 to P. A. E. Gardner et al. (IBM length of the code word and that the number of new
Docket No. UK9-67-02l) for a showing of a three bits entered into argument register 30 equal the
state cell that can be used in the present associative number of bits in the original word that has just been
memory. An associative memory using another form of encoded. This word will be progressively shifted out of
three-state cell for decoding purposes is shown in the the argument register while the new entry is being
copending application of Josef Raviv and Michael A. made. The length counter 34, which has been set ac
Wesley, Ser. No. 62,306, ?led Aug. 10, 1970 (IBM cording to the L value as described above, will control
Docket No. YO9-70-040). The advantage of a three both of these actions so that the proper number of bits
state cell is that it can be individually masked from in
terrogation without requiring that all other cells in the is read out or entered, respectively. The setting of the
same column be masked. length counter 34 is decremented by 1 each time a new
The third section 26 of associative memory 20, FIG. bit is entered into the argument register 30, and when
25 the length counter setting has been reduced to 0, the
1A, stores length indicia L, which are used during the
encoding process to denote the number of signi?cant entry of new bits into the register 30 ceases until the
bits in the original word that is being encoded. As an next encoding operation takes place.
example, referring to FIG. 6, the original word 00 is as The data register 32 has a capacity suf?cient to ac
sociated with a binary length designation ( L) of 010, or 30 commodate a code word having the maximum length
2 in decimal notation, which indicates that there are W. If the code word which was read out during the as
two bits in this original word. Since the ratio ( N/a) of sociation performed by memory 20 has a length less
encoded bits to original bits in this particular code than W, only the appropriate number of bits will be
system is 3/2, the length of the corresponding code read out of register 32 into the encoded bit stream. In
word( 010) is 3 bits. The length indicia L are used only 35 any event, thev ratio between the number of bits read
during encoding operations. During decoding opera out of register 32 and the number of bits entered into
tions the necessary word length information is derived the register 30 must be kept constant at the value N/a.
as an incident to the framing function. Stating this another way, for every 02 bits fed into the ar
gument register 30, N bits must be read out of the data
ENCODING
40 register 32. This ratio is maintained by intermittently
The encoding procedure will be described with par setting two bit counters 36 and 38, FIG. IE, to the ap
ticular reference to FIGS. 1A, 1B, 2, 4, 6 and 7. As ex propriate values. Counter 36, herein designated the
plained hereinabove, it is assumed for present purposes “output bit counter”, is set initially to the value N dur
that the system will process information according to a ing the encoding operation and is decremented by I
state~independent coding scheme, such as the ( 1,8) 45 each time a bit is outgated from data register 32.
code or the ( 2,7) code chosen for illustration herein Counter 38, herein designated the “input bit counter”,
(FIGS. 6 and 7). This means that a single encoding initially is set to the value a during encoding operations
decoding table may be used, and the code words and is decremented by 1 each time a bit enters the ar
generated by this table. may be freely concatenated gument register 30.
without violating the specified (d,k) constraints. 50 The functions of reading out encoded bits and enter
If one should choose to use a state-dependent coding ing new original bits are performed in such a manner
scheme, the encoding procedure will be similar except that they are approximately contemporaneous with
that it will involve a choice among several code tables each other. To explain this further, when any group of
according to the terminal state of the word that previ a bits has entered register 30, thereby reducing the
ously was encoded. The required modi?cations of the setting of input bit counter 38 to 0, the entry of the next
illustrated system for enabling it to perform state-de succeeding group of a bits into the register 30 will be
pendent coding will be brie?y explained hereinafter. deferred until the current group of N encoded bits has
The encoding procedure is conducted in the follow been read out of the data register 32. Then, when the
ing general manner: The bits of information to be en setting of the output bit counter 36 reduces to 0, the
coded are entered serially into an argument register 30, two bit counters 36 and 38 are again set to N and a,
FIG. 1A. Initially a number of bits equal to aW/N will respectively, to control the ingating of a bits into the
be entered into the register 30, this number cor register 30 and the outgating of N bits from the register
responding to the maximum length of the words stored 32, until the current code word has been completely
in memory section 24. The association is performed on read out of register 32. This fact is indicated when the
this argument, and the matching code word is read out 65 setting of length counter 34 reduces to 0.
from memory section 22 and entered into a' data re While new bits are being entered into the argument
gister 32. At the same time, the related length indica register 30, the contents of this register are cor
 9
3,689,899
respondingly being shifted to the left. The length FIGS. 18 and 4, and thence through OR circuit 48 to
counter setting determines the number of leftward the single shot 50, causing this single shot to be again
shifts that will be performed according to the length of turned on for generating an E2 clock pulse. Referring
the bit group or bit string that was just encoded. Con to FIG. 2, this reinitiates the sequence of steps E2, E3
sequently, as the last bit of the old group is shifted out and E4, during which the argument register 30, FIG.
of the argument register 30, the leading bit of the new 1A undergoes a left shift, a new bit enters this register
group becomes positioned at the proper place for a new 30, the setting of length counter 34 is reduced by l and
association to be performed thereon by the associative the length counter again is tested to see whether it has
memory 20. been reset to 0. This sequence of steps E2, E3 and E4
A more detailed explanation of the encoding will repeat itself as many times as needed to bring the
procedure now will be presented with speci?c ?rst set of aW/N bits into the argument register 30.
reference to the ?owchart shown in FIG. 2. The various When all of these bits have been entered, the next test
steps of this ?owchart are designated by reference of the length counter setting ( at step E4) reveals that
numbers having an “E” pre?x (e.g., El, E2, etc.). this setting has gone to 0.
These indicate steps of the procedure that are initiated Referring to FIG. 1B, the activation of gate 60 by
by timing or clock pulses generated on wires bearing clock pulse E4, occurring when the 0 output line 64
the same designations in the encoding clock circuitry from converter 62 is energized, causes such energiza
shown in FIG. 4. Each of these clock pulses is tion to be extended through gate 60, wire 70 and OR
generated by a single shot ( SS) when it is turned on. 20 circuit 72, FIG. 4, to a single shot 74, which thereupon
For instance, when the single shot 40, FIG. 4, is turned turns on to generate clock pulse E5. This initiates a new
on in response to a start pulse applied on wire 42, it sequence of steps E5, E6 and E7, FIG. 2, during which
generates a clock pulse on wire E1. This initiates the the decoding actually is performed.
step of the encoding procedure designated E1 in FIG. Thus, when the clock pulse E5 is generated, it sets
2, during which the length counter 34, FIG. 1B, is set to 25 the various match indicators of the associative memory
an initial value aW/N, and a ?ip-flop 44, FIG. 1A,( the controls 80, FIGS. 1A and 12, to their 1 states. Speci?
“END” ?ip-?op) is reset to its 0 setting. These two ac cally, the E5 clock pulse is extended through an OR cir
tions are accomplished by applying the El pulse to a cuit 82, FIG. 1A, to a wire 84, FIG. 12, which is con
gate 46, FIG. 1A, thereby enabling this gate to pass a nected in parallel to the 1 input terminals of the match
preselected initial value aW/N into the length counter indicator ?ip-?ops 86 in the associative memory con
34, FIG. 1B, and applying an E1 pulse also to the 0 trols 80. This conditions the associative memory con
input side of the END ?ip-?op 44, FIG. 1A. trols for a search operation.
When the single shot 40 goes off, FIG. 4, it sends a When single shot 74 goes off, FIG. 4, it turns on a sin
pulse through an OR circuit 48 to a single shot 50, gle shot 88 to generate an E6 clock pulse, which ener
which turns on to generate the E2 clock pulse for in gizes as “associate” line for the argument register 30,
itiating step E2 of the encoding procedure, FIG. 2. FIG. 1A. This causes the associative memory 20 to
Referring to FIG. 1A, in conjunction with FIG. 2, it can search for a word in memory section 24 that will match -
be that the E2 pulse is applied to a means for effecting a the contents of the argument register 30. A match oc
leftward shift of the argument register 30 by one bit
40 curs when the pattern of signi?cant bits in any of the
position, preparing this register to receive an incoming words stored in memory section 24 matches the cor
bit from the original bit stream. respondingly positioned bits in argument register 30.
As single shot 50, FIG. 4, goes off, it causes the single Thus, for instance, assuming that the ( 1,8) code is
shot 52 to turn on and generate the E3 clock pulse. being used, if the two leftmost positions of argument re
This initiates step E3, FIG. 2, wherein the E3 pulse is 45 gister 30 contain O’s, then a match will exist between
applied to a gate 54, FIG. 1A, enabling a bit to be in this argument and the topmost word in memory section
gated to the argument register 30. Also,.at this time, the 24, FIG. 6. The remaining bits in the argument register
E3 clock pulse is applied through an OR circuit 56, 30 would be ignored in this case, because the remaining
FIG. 1B, to a device for decrementing the length cells of that row in the associative memory section 24
counter setting by 1. Thus, a bit has entered the argu 50 are set to their “don't care” state. Hence a match
ment register 30 and the length counter setting has would be established between the argument 00 and the
been correspondingly decremented. stored word 00, regardless of the remaining bits in ar
When single shot 52, FIG. 4, goes off, it causes single gument register 30.
shot 58 to turn on and generate an E4 clock pulse. This The words stored in section 24 of associative
initiates a test of the length counter setting to see 55 memory 20, which represent all original bit strings that
whether it has been reduced to 0. The E4 pulse is ap may be encoded, are so selected that no word may con
plied to a gate 60, FIG. 1B, for passing the 0 or not-O stitute the beginning of a longer word in this same set.
output, as the case may be, from a converter 62 as Thus, referring to FIG. 6, for example, since the first
sociated with the length counter 34. The function of word in memory section 24 is 00, none of the other en
the converter 62 is to energize an output line 64 if the 60 codable words stored in section 24 may begin with 00.
length counter setting is 0 and to energize an output In this connection, however, it should be noted that
line 66 if this setting is other. than 0. In the present in there is a special row of cells in section 24 which con
stance it will be assumed that the not-0 line 66 is ener tains a dummy word consisting entirely of 0's. This
gized, since the length counter setting has not yet been dummy word is in a different category, representing a
65
reduced to 0. In this condition, when gate 60 is ac “no match” condition which may be encountered only
tivated by the clock pulse E4, energization will be ex during decoding operations. It is not utilized during en
tended from wire 66 through this gate 60 to a wire 68, coding operations and will be dealt with speci?cally
 II
3,689,899
when the decoding operations are described. During
encoding operations it is assumed that for every argu
ment which is stored in argument register 30, FIG. 1A,
there will be a unique match between it and one of the
words stored in memory section 24, exclusive of this
dummy word.
Referring again to FIG. 12, the presence of a non
matching word in any row of the associative memory
section which is being searched ( section 24, in this in
stance) will cause a signal to be generated on the
mismatch line 90 for that row of cells. This mismatch
signal is applied to the 0 input terminal of the related
match indicator ?ip-?op 86, resetting it to its 0 state.
Since it is assumed that there will be only onerow of
cells which contains a matching word, mismatch signals
will be generated for all rows except the one in which
this matching word is stored. Hence, only one of the
match indicators 86 will remain in its 1 state, the others
being reset to 0.
When single shot 88, FIG. 4, goes off, it sends a pulse
through a wire 92 for turning on the next single shot 94
to generate an E7 clock pulse, which is applied through
an OR circuit 96, FIG. 1A, to a read line 98, FIG. 12.
Associated with each match indicator 86 is an AND 25 of argument register 30, FIG. 1A, leftward one bit.
circuit 100. One input terminal of each AND circuit
100 is connected to the read-line 98, the other input
terminal being connected to the 1 output terminal of
the respective match indicator 86. If the match indica
tor is in its 1 state, energization is extended through the 30 gument register 30. Second, it causes the input bit
respective AND circuit 100 to the respective read wire
102, thereby conditioning for readout the row of
memory cells which stores the matching word, i.e., the
word that matches the argument stored in argument re
gister 30, FIG. 2A. All other read lines 102 will remain
inactive. As mentioned hereinabove, there will be one
and only one matching word during every encoding
operation.
Section 22 of associative memory 20, FIG. 1A, now
has been conditioned for readout of the encoded word
stored in the row of cells which contains the matching
original word in memory section 24. When the E7 tim
ing pulse is generated as above described, this pulse is
applied also to a gate 104, FIG. 1A, for thereby
coupling the output of memory section 22 to the input
side of data register 32. This enables the encoded word
corresponding to the encoding argument to be gated
into the data register 32, where it is now available for
serial readout.
As still another incident to generation of the E7 tim
ing pulse, a gate 106, FIG. 1A, is activated for transfer
ring the related length indication L from the memory
section 26 into the length counter 34, FIG. 1B. The
length setting therefore denotes the number of signi? 55 130 extends energization from the 0 line 126 to a wire
cant bits contained in the original word that was just
used as an encoding argument.
When single shot 94, FIG. 4, goes off it turns on sin
gle shot 108 to generate an E8 clock pulse. As in
dicated in the flowchart, FIG. 2, this has the effect of 60 remains inoperative until a third input is supplied to it
setting the input bit counter 38, FIG. IE, to the value a
and setting the output bit counter 36 to the value N. As
explained above, the value N represents the number of
data bits to be read out of the data register 32, FIG. 1A,
for every 0: bits of data entered into the argument re
gister 30. That is to say, the ratio N/a is the ?xed rela
tionship between the number of bits in the encoded
12
word and the number of bits in the original bit string
from which this encoded word was derived.
Referring again to FIG. 4, when single shot 108 goes
off it sends a pulse through OR circuits 110 and 112 to
a single shot 114, and also sends a pulse through OR
circuits 110 and 116 to a single shot 118. There now
follows a phase of the encoding operation during which
two subsequences E9-El1 and El2-El4, FIG. 2, are
performed concurrently. During steps E9-Ell, 0: bits
of data are serially fed into the argument register 30,
FIG. 1A, the contents of which are shifted leftward ac
cordingly. During steps BIZ-E14, N bits of data are
serially read out of the data register 32, the contents of
which are shifted leftward accordingly. These two con
current subsequences are performed as many times as
needed ( as determined by the length counter setting)
for bringing a new argument into position for associa
tion in the argument register 30 and to complete the
20 readout from data register 32 of the code word that has
_ just been encoded.
To consider the operations just described in detail,
when single shot 114, FIG. 4, goes on, it generates an
E9 clock pulse, which is effective to shift the contents
When single shot 114, FIG. 4, goes off, it causes single
shot 120 to go on for generating an E10 clock pulse.
This action has three effects. First, it activates the gate
54, FIG. 1A, for enabling a bit to be entered into the ar
counter 38, FIG. 18, to be decremented by 1. Third, it
causes the setting of length counter 34 to be decre
mented by 1.
When single shot 120 goes off, it causes single shot
122, FIG. 4, to turn on, thereby generating the E11
clock pulse. This causes the setting of the input counter
38, FIG. IE, to be tested for determining whether the
same has been reduced to 0. Associated with the input
bit counter 38 is a converter 128, which produces an
40
output signal on a line 124 if the input bit counter
setting is not 0 and produces a signal on another output
line 126 if the input bit counter setting has gone to 0.
The E11 clock pulse is applied to a gate 130, FIG. 1B,
and if the not-0 line 124 is energized (as will be as
sumed for the present), such energization will be ex
tended through gate 130 to a wire 132, FIGS. 1B and 4,
and OR circuit 112 to the single shot 114. Therefore,
until the input bit counter setting is reduced to 0, the
50 sequence of steps E9-El 1, FIG. 2, is repeated.
Eventually, when a new bits have entered the argu
ment register 30, FIG. 1A, the setting of input bit
counter 38, FIG. 18, returns to 0. Under these condi
tions, when the E11 clock pulse is generated, the gate
134 and thence through OR circuit 136 to one terminal
of an AND circuit 138, FIGS. 1B and 2. A second input
to AND circuit 138 is supplied by the 0 line 126 from
the input hit counter. However, the AND circuit 138
when the setting of the output bit counter 36 returns to
0. Hence, the return of the input bit counter setting to 0
has the effect of suspending further performance of
steps E9-El 1, FIG. 2, but has no further effect until the
65
setting of the output bit counter has returned to 0.
When single shot 118, FIG. 4, is turned on as
described above, it generates the E12 clock pulse for