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org/semiconductors/devices/intel-
finds-moores-laws-next-step-at-10-nanometers
• https://www.edn.com/design/integrated-circuit-
design/4429282/Gate-level-simulations--verification-flow-
and-challenges
• https://www.edn.com/design/test-and-
measurement/4458672/Modified-clock-filters-improve-at-
speed-test
• http://www.newelectronics.co.uk/electronics-news/design-
challenges-for-7nm/157380/
• http://ece-
research.unm.edu/jimp/vlsi_test/slides/
• http://coreel.com/coreel-irsi-6/
• https://www.altencalsoftlabs.com/contact-us/
• https://moschip.com/contact-us/
Module-1 Fault Modelling
• Importance of Testing –
• Testing during the VLSI Lifecycle –
• Challenges in the VLSI Testing: Test Generation –
• Fault Models –
• Levels of Abstraction in VLSI Testing –
• Historical Review of VLSI Test Technology –
• Functional Versus Structural Testing –
• Levels of Fault Models –
• Fault Equivalence –
• Fault Dominance –
• Fault Collapsing –
• Check point Theorem –
• Delay Fault.
DESIGN FOR TESTING
Fundamentals on Testing
and Design for Testability
Chap1.
Design Verification, Testing
and Diagnosis
• Design Verification: Ascertain the design
perform its specified behavior
• Testing: Exercise the system and analyze
the response to ascertain whether it
behaves correctly
• Diagnosis: To locate the cause of
misbehavior after the incorrect behavior is
detected
Chap1.
Some Real Defects in Chips
• Processing Faults
– missing contact windows
– parasitic transistors
– oxide breakdown
• Material Defects
– bulk defects (cracks, crystal imperfections)
– surface impurities (ion migration)
• Time-Dependent Failures
– dielectric breakdown
– electromigration
• Packaging Failures
– contact degradation
– seal leaks
Chap1.
Scenario for Manufacture
Test
TEST VECTORS
MANUFACTURED
CIRCUIT
CIRCUIT RESPONSE
CORRECT
RESPONSES
COMPARATOR PASS/FAIL
Chap1.
Purpose of Manufacture
Testing
• Verify Manufacture of Circuit
– Improve System Reliability
– Diminish System Cost
• Cost of repair goes up by an order of
magnitude each step away from fab line
1000
500
100
Cost
per 50
10
fault
(Dollars)
5
1
0.5
IC Board System Warranty
Test Test Test Repair
Chap1.
Testing and Quality
Shipped Parts
ASIC Testing
Fabrication Yield: Quality:
Fraction of Defective parts
good parts per million (DPM)
Rejects
Chap1.
Fault Coverage
T= # of detected faults
# of possible faults
Chap1.
Defect Level
DL = 1 - Y (1-T )
Y: yield
T: fault coverage
Chap1.
Relating Defect Level to Fault Coverage
1
Y=.01
.9 DL = 1 -Y(1-T)
.8 Y = Yield
Y=.10
.7
.6 Y=.25
.5
.4 Y=.50
.3
Y=.75
.2
Y=.90
.1 Y=.99
0
0 10 20 30 40 50 60 70 80 90 100
Fault Coverage, T (%)
Chap1.
Defect Level, Yield and Fault Coverage
Chap1.
ASIC
Chap1.
ASICs' Demand
Chap1.
Test Development Time vs. Testability
40
35
30
25
20
15
10
Measured development times
5 Extrapolated curve
0 20 40 60 80 100
Chap1.
Time-to-Market Model
Lost revenue
due to delay
Delay in Time
reaching market
Chap1.
Why Testing is Difficult ?
Chap1.
How To Do Test
• Fault Modeling
– Identify target faults
– Limit the scope of test generation
– Make analysis possible
• Test Generation
– Automatical or Manual
• Fault Simulation
– Assess completeness of tests
• Testability Analysis
– Analyze a circuit for potential problem on test
generation
• Design For Testability
– Design a circuit for guaranteed test generation
– Introduce both area overhead and performance
degradation Chap1.
The New Challenges for VLSI Testing
Chap1.
Reference:
Chap1.
DEC Alpha Chip (1994)
* 64-bit RISC
* 200 MHz
* 400 MIPS
* 200 Mflops
* 16.813.9-mm die
* 1.68 million Txs
* 431-pin package
* 3.3-V
* 30W power consumption.
Chap1.
Multi-Chip Module (MCM)
Chap1.
Wafer Scale Integration (WSI)
Chap1.
Traditional Design Flow
Yes No
Done
Chap1.
The Infamous Design/Test Wall
30 years of experience proves that
test after design does not work!
Oh no!
What does
Functionally correct! this chip do?!
We're done!
Chap1.
New Design Mission
TESTABILITY
PERFORMANCE AREA
Chap1.
New VLSI Design Flow
No
Yes
Design Function/ Structure Logic Satisfied
Spec. Behavior Synthesis ?
Test Testable
plan Design Circuit ATPG
Rules Synthesis
TESTS
Testability Placement/
Analysis Routing
MASK
Chap1.
Introduction to VLSI Testing
• A 32 bit adder
• A 32 bit counter
• A 107-transistor CPU
• A 109-transistor SOC
0 0
0
0 0 0/1
Related fields
Verification: To verify the correctness of a
design
Diagnosis: To tell the faulty site
Reliability: To tell whether a good system will work
correctly or not after some time.
Debug: To find the faulty site and try to eliminate the fault
VLSI Testing Introduction.44 NCKUEE-KJLEE
Why Studying Testing?
• Economics!
Reduce test cost (enhance profit)
Automatic test equipment (ATE) is extremely
expensive
Shorten time-to-market
Market dominating or sharing
Guarantee IC quality and reliability
Defects detected in Cost
Rule of Ten: Wafer 0.01 – 0.1
Cost to detect faulty Packaged chip 0.1 – 1
IC increases by an Board 1 – 10
order of magnitude System 10 – 100
Field 100 – 1000
VLSI Testing Introduction.45 NCKUEE-KJLEE
Principle of Testing
Input Patterns Output Response
-1011 Circuit 1-001
11-00 under 0011-
-0-1- -1101
01--0 Test 1001-
0-101 (CUT) 01-11
Stored
Correct Comparator
Response
Test Result
• Testing typically consists of
Applying set of test stimuli (input patterns, test vectors)
to inputs of circuit under test (CUT), and
Analyzing output responses
• The quality of the tested circuits will depend upon
the thoroughness of the test vectors
VLSI Testing Introduction.46 NCKUEE-KJLEE
Importance of testing
N = # transistors in a chip
p = prob. (a transistor is faulty)
Pf = prob. (the chip is faulty)
Pf = 1- (1- p) N
If p = 10-6
N = 106
Pf = 63.2%
Vss
• Logic simulation
• Fault simulation ATPG
• Test generation
C C
4 1
B
C3 C2
• Gate level
A E • Higher/ System level
B
G
C
D F
A E
A s-a-1 B s-a-1 C s-a-1 D s-a-1
B A s-a-0 B s-a-0 C s-a-0 D s-a-0
G
E s-a-1 F s-a-1 G s-a-1
C E s-a-0 F s-a-0 G s-a-0
D F
14 faults
• Other fault models:
- Break faults, Bridging faults, Transistor stuck-open faults,
Transistor stuck-on faults, Delay faults
Faulty Chip
Defects
Wafer
Shipped Parts
IC
Testing
Fabrication
Yield: Quality:
Fraction of Defective parts
good parts per million (DPM)
Rejects
A I C
A D B C
CC
CC
IR
1
2
B F
G
B RB
F IF
E CD C
C E E
JE
H
D E
No
More faults? Exit
Yes
Select a fault
Fault
dropping
Test generation
Fault simulation
1. Reconvergent fanout
Combinational part
PIs POs
Y J
K
Y CK clk
MUX
T/N
Combinational Combinational
logic logic
SO
FF SFF
FF SFF
FF SFF
T/N
VLSI Testing Introduction.67 SI NCKUEE-KJLEE
Scan Cell Design
Q DI Q,SO
DI D Q D Q
SI
CK CK
N/T
(SE)
Q Q,SO
DI DI
F
F
SI
F FT F + FT
Most cell libraries now have scan cells!
Combinational
Circuits
Q D Q D Q D Q D
SO SI SI SI SI
SE
CLK
TRST*
TRST* TRST*
TRST* TRST*
Response
generator
Analyzer
pattern
BIST good/fail
Controller
biston bistdone
VLSI Testing Introduction.72 NCKUEE-KJLEE
Built-In-Self Test (BIST) (Cont.)
Remainder Quotient
R x x 2 x 4 1 x2
VLSI Testing Introduction.75 NCKUEE-KJLEE
Signature Analyzer (SA) (cont.)
• A LFSR performs polynomial division
Px : x 5 x 4 x 2 1
Q x : x 2 1
x7 x6 x 4 x 2 x5 x 4 x 2 1
x7 x6 x5 1
Before After
sys_di
sys_addr data
di
sys_wen
clk
data hold_l Memory q
addr Memory
Module rst_l Module
test_h
wen si so
se
sys_addr
Pattern Generator
Algorithm-Based
di
sys_d addr Memory data
isys_wen wen
Module
rst_l
Compressor
clk q
compress_h clk
hold_l
rst
test_h si so
se
BIST Circuitry
logic
rst_l
clk
Bist Memory
hold_l
control
test_h
bist_se
compressor bist_so TDO
bist
decoder
int_scan mbist
scan
decoder
decoder
TDI
TCK IR
TAP Controller
TMS
• An SOC
Introduction
117
What is this chapter about?
• Introduce fundamental concepts and various
aspects of VLSI testing
• Focus on
– Importance of testing in the design and manufacturing
processes
– Challenges in test generation and fault modeling
– Levels of abstraction in VLSI testing
118
Introduction to VLSI Testing
• Introduction
• Testing During VLSI Life Cycle
• Test Generation
• Fault Models
• Levels of Abstraction
• Overview of Test Technology
• Concluding Remarks
119
Introduction
• Integrated Circuits (ICs) have
grown in size and complexity 1.E+09
since the late 1950’s 1.E+08
– Small Scale Integration (SSI) 1.E+07
Number of Transistors
– Medium Scale Integration (MSI) 1.E+06
– Large Scale Integration (LSI) 1.E+05
– Very Large Scale Integration (VLSI) 1.E+04
• Moore’s Law: scale of ICs 1.E+03 VLSI
doubles every 18 months 1.E+02
M LSI
– Growing size and complexity poses 1.E+01
S
S S
many and new testing challenges I I
1.E+00
1960s 1970s 1980s 1990s 2000s
120
Importance of Testing
• Moore’s Law results from decreasing feature size
(dimensions)
– from 10s of m to 10s of nm for transistors and
interconnecting wires
• Operating frequencies have increased from
100KHz to several GHz
• Decreasing feature size increases probability of
defects during manufacturing process
– A single faulty transistor or wire results in faulty IC
– Testing required to guarantee fault-free products
121
Importance of Testing
• Rule of Ten: cost to detect faulty IC increases by
an order of magnitude as we move from:
– device PCB system field operation
• Testing performed at all of these levels
• Testing also used during
– Manufacturing to improve yield
• Failure mode analysis (FMA)
– Field operation to ensure fault-free system operation
• Initiate repairs when faults are detected
122
Testing During VLSI Life Cycle
• Testing typically consists of
– Applying set of test stimuli to
– Inputs of circuit under test (CUT), and
– Analyzing output responses
• If incorrect (fail), CUT assumed to be faulty
• If correct (pass), CUT assumed to be fault-free
Input1 Output1
Input Circuit Output
Test Under Test Response Pass/Fail
Inputn Outputm
Stimuli (CUT) Analysis
123
Testing During VLSI Development
• Design verification
targets design errors Design Specification
– Corrections made prior
to fabrication Design Design Verification
• Remaining tests target
Fabrication Wafer Test
manufacturing defects
– A defect is a flaw or
Packaging Package Test
physical imperfection
that can lead to a fault
Quality Assurance Final Testing
124
Design Verification
• Different levels of abstraction
during design Design Specification
– CAD tools used to synthesize
design from RTL to physical level Behavioral (Architecture) Level
• Simulation used at various
level to test for Register-Transfer Level
125
Yield and Reject Rate
• We expect faulty chips due to manufacturing
defects
number of acceptable parts
– Called yield yield
total number of parts fabricated
• 2 types of yield loss
– Catastrophic – due to random defects
– Parametric – due to process variations
• Undesirable results during testing
– Faulty chip appears to be good (passes test)
number of faulty parts passing final test
• Called reject rate reject rate
total number of parts passing final test
– Good chip appears to be faulty (fails test)
• Due to poorly designed tests or lack of DFT
126
Electronic System Manufacturing
• A system consists of
– PCBs that consist of
• VLSI devices PCB Fabrication Bare Board Test
• Faults occur 0t t1 t2 t3 t4 t
0
129
System-Level Testing
• Testing required to ensure system availability
• Types of system-level testing
– On-line testing – concurrent with system operation
– Off-line testing – while system (or portion of) is taken
out of service
• Performed periodically during low-demand periods
• Used for diagnosis (identification and location) of faulty
replaceable components to improve repair time
130
Test Generation
• A test is a sequence of test patterns, called test
vectors, applied to the CUT whose outputs are
monitored and analyzed for the correct
response
– Exhaustive testing – applying all possible test
patterns to CUT
– Functional testing – testing every truth table entry
for a combinational logic CUT
• Neither of these are practical for large CUTs
• Fault coverage is a quantitative measure of
quality of a set of test vectors
131
Test Generation
• Fault coverage for a given set of test vectors
number of detected faults
• 100% fault coverage may
fault cove impossible due
ragebe
total number of faults
to undetectable faults
132
Test Generation
• Goal: find efficient set of test vectors with
maximum fault coverage
• Fault simulation used to determine fault
coverage
– Requires fault models to emulate behavior of
defects
• A good fault model:
– Is computationally efficient for simulation
– Accurately reflects behavior of defects
• No single fault model works for all possible
defects
133
•
Fault Models
A given fault model has k types of faults
– k = 2 for most fault models
• A given circuit has n possible fault sites
• Multiple fault model –circuit can have multiple faults
(including single faults
– Number of multiple fault = (k+1)n-1
• Each fault site can have 1-of-k fault types or be fault-free
• The “-1” represents the fault-free circuit
– Impractical for anything but very small circuits
• Single fault model – circuit has only 1 fault
– Number of single faults = k×n
– Good single fault coverage generally implies good multiple
fault coverage
134
Fault Models
• Equivalent faults
– One or more single faults that have identical
behavior for all possible input patterns
– Only one fault from a set of equivalent faults
needs to be simulated
• Fault collapsing
– Removing equivalent faults
• Except for one to be simulated
– Reduces total number of faults
• Reduces fault simulation time
• Reduces test pattern generation time
135
Stuck-at Faults
Truth table for fault-free behavior
Any line can be and behavior of all possible stuck-at faults
x1x2x3 000 001 010 011 100 101 110 111
Stuck-at-0 (SA0) y 0 1 0 0 0 1 1 1
a SA0 0 1 0 0 0 1 0 0
Stuck-at-1 (SA1) a SA1 0 1 1 1 0 1 1 1
b SA0 0 1 0 1 0 1 0 1
# fault types: k=2 b SA1 0 0 0 0 1 1 1 1
c SA0 0 0 0 0 0 0 1 1
Example circuit: c SA1 1 1 0 0 1 1 1 1
# collapsed faults = a
a
SA0
SA1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
2×(PO+FO)+GI-NI b
b
SA0
SA1
0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
PO= # primary outputs c
c
SA0
SA1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
1
1
FO= # fanout stems d SA0 0 1 0 0 0 1 0 0
d SA1 0 1 0 0 1 1 1 1
GI= # gate inputs e SA0 0 1 0 1 0 1 1 1
e SA1 0 0 0 0 0 0 1 1
NI= # inverters f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1
d g SA0 0 1 0 0 0 1 0 0
x2 b g g SA1 1 1 1 1 1 1 1 1
i y h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
138
Stuck-at Faults
• # collapsed faults = 2×(PO+FO)+GI-NI
– PO= number of primary outputs
– FO= number of fanout stems
– GI= total number of gate inputs
for all gates including inverters
– NI= total number of inverters
• For example circuit, # collapsed faults = 10
– PO= 1, FO= 1, GI= 7, and NI= 1
• Fault collapsing typically reduces number of
stuck-at faults by 50% - 60%
139
VDD
Transistor Faults A P1
2-input
• Any transistor can be CMOS
B P2
Z
NOR
– Stuck-short gate N N
• Also known as stuck-short 1 2
– Stuck-open VSS
Truth table for fault-free circuit
• Also known as stuck-open and all possible transistor faults
AB 00 01 10 11
# fault types: k=2 Z 1 0 0 0
• Example circuit
N1 stuck-open 1 0 last Z 0
N1 stuck-short IDDQ 0 0 0
VSS gate N N
VSS
steady-state power supply Truth table for fault-free circuit
current IDDQ and all possible transistor faults
AB 00 01 10 11
• Stuck-open faults cause Z 1 0 0 0
143
Bridging Faults AS
source
A
destination
D
• Three different models BS B
– Wired-AND/OR AS
bridging fault
D
AD AS AD
– Dominant
– Dominant-AND/OR BS BD BS BD
AS BS 0 0 0 1 1 0 1 1 BS BD BS BD
AD BD 0 0 0 1 1 0 1 1 A dominates B B dominates A
Wired-AND 0 0 0 0 0 0 1 1 AS A AS A
Wired-OR 0 0 1 1 1 1 1 1 D D
A dominates B 0 0 0 0 1 1 1 1 BS BD BS BD
B dominates A 0 0 1 1 0 0 1 1 A dominant-AND A dominant-OR B
A dominant-AND B 0 0 0 0 1 0 1 1 AS B A AS A
B dominant-AND A 0 0 0 1 0 0 1 1 D D
A dominant-OR B 0 0 0 1 1 1 1 1 BS BD BS BD
B dominant-OR A 0 0 1 1 1 0 1 1 B dominant-AND B dominant-OR A
144 A
Delay Faults and Crosstalk
• Path-delay fault model considers cumulative
propagation delay through CUT
– 2 test vectors create transition along path
– Faulty circuit has excessive delay
• Delays and glitches can be caused by crosstalk
between interconnect
– due to inductance and capacitive coupling
0 0 x1
0 1 x2 3
t=0 t=7 y
2
v2 v1 t=2
2
3
1 1 x3
145
Pattern Sensitivity and Coupling Faults
• Common in high density RAMs
• Pattern sensitivity fault
– Contents of memory cell is affected by
contents of neighboring cells
• Coupling fault
– Transition in contents of one memory cell
causes change in contents of another cell
146
Pattern Sensitivity and Coupling Faults
• Common in memory cells of high density RAMs
• Pattern sensitivity fault
– Contents of cell affected by contents of neighboring cells
• Coupling fault
– Transition in one cell causes change in another cell
• Detected with specific memory test algorithms
– Background Data Sequence (BDS) used for word-oriented
memories
148
Levels of Abstraction
• High levels have few implementation details
needed for effective test generation
– Fault models based on gate & physical levels
• Example: two circuits for same specification
– Ckt B test vectors do not detect 4 faults in Ckt A
a SA1
f(a,b,c)=m(1,7)+d(3) = abc + abc + Xabc b
c
ab SA1 f
c 0 0 1 1 f = abc + abc
00 11 1X 0 SA1 Circuit A
Circuit A Test Vectors
1 1 {111,110,101,011,010,00
SA1
ab 0} a
c 0 0 1 1
11 1X 0 f = ab + bc b Circuit B
00
Circuit B Test Vectors f
1 1
{111,101,010,000}
149 c
Overview of VLSI Test Technology
• Automatic Test Equipment (ATE) consists of
– Computer – for central control and flexible test
& measurement for different products
– Pin electronics & fixtures – to apply test
patterns to pins & sample responses
– Test program – controls timing of test patterns
& compares response to known good
responses
150
Overview of VLSI Test Technology
• Automatic Test Pattern Generation (ATPG)
– Algorithms generating sequence of test vectors for a
given circuit based on specific fault models
• Fault simulation
– Emulates fault models in CUT and applies test
vectors to determine fault coverage
– Simulation time (significant due to large number of
faults to emulate) can be reduced by
• Parallel, deductive, and concurrent fault simulation
151
Overview of VLSI Test Technology
• Design for Testability (DFT)
– Generally incorporated in design
– Goal: improve controllability and/or
observability of internal nodes of a chip or
PCB
• Three basic approaches
– Ad-hoc techniques
– Scan design
• Boundary Scan
– Built-In Self-Test (BIST)
152
Design of Testability
• Ad-hoc DFT techniques
– Add internal test points (usually multiplexers) for
• Controllability
• Observability
– Added on a case-by-case basis
• Primarily targets “hard to test” portions of chip
Chap1.
Fault Equivalence
Chap1.
Equivalence Fault Collapsing
Chap1.
Equivalence
in a Wire
A B
* Fault equivalence:
A sao <---> B sao
A sa1 <---> B sa1
Chap1.
Fault Equivalence
s-a-1
x
Chap1.
Chap1.
Chap1.
Chap1.
Chap1.
Chap1.
Chap1.
Fault Dominance
Chap1.
Fault Dominance
Chap1.
Fault Dominance
D
x
A
C x
B
x
E
• Detect A sa1:
zt z f t CD CE D CE D CD 1
C 0, D 1
• Detect C sa1:
zt z f t CD CE D E 1
C 0, D 1 or C 0, E 1
C sa1 --> A sa1
• Similarly C sa1 --> B sa1
C sa0 --> A sa0
C sa0 --> B sa0
Chap1.
Equivalence & Dominance
in a Single-Gate
A B C A B C
A B C sa1 sa1 sa1sa0 sa0 sa0
A
C 00 0 1
B 01 0 1 1
10 0 1 1
11 1 0 0 0
Chap1.
Fault Collapsing
Chap1.
Prime Fault
Chap1.
Why Fault Collapsing?
* Memory & CPU-Time saving
===> To ease the burden for test generation
and fault simulation in testing
# of # of # of
total faultsequivalent faultsprime faults
1 60% 40%
Chap1.
Fault Collapsing for
a Combinational Circuit
Chap1.
Checkpoint Theorem
Chap1.
Fault Collapsing
– 10 checkpoint faults
– a s-a-0 <-> d s-a-0 , c s-a-0 <-> e s-a-0
b s-a-0 -> d -> 0 , b s-a-1 -> d -> 1
– 6 tests are enough
Chap1.
Problem
1.1 If the yield of good dice is 90%, and we want a defect level not to exceed 0.1%,
what level of testing in terms of fault coverage must be achieved?
1.2 Given the market entry time verse revenue curves as shown in the figure, fill in
the following formula
1a. Lost Revenue = Total Expected Revenue * [ ];
The answer should be in term of d and w.
d is the delay entry, 2w is the product life.
The two market growth rates are the same.
1b. Given a product with total expected revenue $100M, product life is 20 months,
What is the revenue loss due to the one month late to the market?
$ Revenue
Revenue
M
Curve for ark
On Time h et
wt De
Market ro cli
Entry etG ne
ark
M
Product Life = 2w
Chap1.
1.3 For state transition fault model, explain why there are M(N-1) faults for a
M-transition N-state machine.
Similarly explain why there are NM-1 multiple state transition faults.
1.4 For PLA, there are missing crosspoints and extra crosspoints faults in both
AND-plane and OR-plane.
Can missing crosspoints be modeled as equivalent stuck-at faults? Why?
Can extra crosspoints be modeled as equivalent stuck-at faults? Why?
Chap1.
1.5 For the PLA design shown in Figure 1, construct the Karnaugh maps for Y1,Y2
and Y3 for each of the following situation.
(a) The original PLA;
(b) A shrinkage fault caused by an extra connection between bit line b2 and
product line P4;
(c) An appearance fault caused by an extra connection between P3 and Y1;
(d) A growth fault caused by the missing connection between bit line b4 and P3;
(e) A disappearance fault caused by the missing connection between P1 and Y3;
AND Plane OR Plane
b1 b2 b3 b4 b5 b6
P1=X1X2
P2=X2X3
P3=X2X3
P4=X2X3
Y3=P1+P4
Y2=P3+P4
X1 X2 X3 Y1=P1+P2
Figure 1. A PLA example
Chap1.
1.6 Prove that for combinational circuits faults dominance is a transitive relation,
i.e. if f dominates g and g dominates h, then f dominates h.
a f j
b
g
m
c
h
d i
e k
Chap1.
1.8 In the circuit if any of the following tests detect the fault x1 s-a-0 ?
a. (0,1,1,1)
b. (1,0,1,1)
c. (1,1,0,1)
d. (1,0,1,0)
x1
z
x2
x3
x4
Chap1.
Sensitization
• A test t that detects a fault f
Activates f (or generate a fault effect) by creating
different v and vf values at the site of the fault
Propagates the error to a primary output w by making
all the lines along at least one path between the fault
site and w have different v and vf values
• A line whose value in the test changes in the
presence of the fault f is said to be sensitized to
the fault f by the test
• A path composed of sensitized lines is called a
sensitized path
s-a-0
b 0 x
z
0
0
???
c
1
• G1 output stuck-at-0 fault is undetectable
Undetectable faults do not change the function of
circuit
The related circuit can be deleted to simplify the
circuit
VLSI Testing Fault model.236 NCKUEE-KJLEE
Undetectable Fault
• The presence of an undetectable fault f may
prevent the detection of another fault g, even
when there exists a test which detects the fault g.
• Example:
A detectable fault a s-a-0 becomes undetectable under
the presence of a undetectable fault c s-a-1.
• Fault equivalence
• Fault dominance
• Checkpoint theory
B
x
E
# of # of # of
total faultsequivalent faultsprime faults
1 60% 40%
10 checkpoint faults
a s-a-0 d s-a-0 , c s-a-0 e s-a-0
b s-a-0 d s-a-0 , b s-a-1 d s-a-1
6 faults are enough