SCHOOL OF ELECTRONICS ENGINEERING

M. Tech (Embedded Systems)

Electronic Hardware System Design

(ECE5053)
(LAB Report)

SUBMITTED BY
Shikha Shrivastava 17MES0018
Sujata Bhuyan 17MES0024
Sujatha D 17MES0027
 Content
Sl. No Title Page No
1. Evaluation 3
TASK 1 MODELLING OF COMBINATION LOGIC 4
2.
CIRCUITS- ALU
 Evaluation

Internal Assessment (60 Marks)

Task 1 Modelling of Combination Logic 40
Circuits-ALU
Task 2 Modelling of Sequential Logic 40
Circuits- FSM
Task 3 Designing Printed Circuit Board 20
100
Scaled down to 60 marks 60
Final Assessment Test (40 Marks)
1. Conducted for 50
2. Scaled down to 40 marks 40
Total Marks 100

Evaluation Methods of each Task

1. Report Writing 5
2. Output Verification 5
3. Understanding the Concept – Viva 5
4. Submitting the Report On time 5
Total Marks 20
TASK 1- MODELLING OF COMBINATION LOGIC
CIRCUITS- ALU

4x1 MUX
1.VHDL Code:

2. RTL Schematic:
3. Simulation Results:

Input: a=1,b=1,c=0,d=0,s=01
Output: y=1

4. Constraint file:
Switches:
LEDs:

5. Hardware result

Input: a=1, b=0, c=1, d=1, s=11

Output: y=1