Design of Control Power Supply for

High Power Converters with

Wide Input Variation

A Project Report
Submitted in Partial Fulfilment of
Requirement for the Degree of
Master of Engineering
in
Electrical Engineering

By
Akshay Kumrawat

Department of Electrical Engineering

Indian Institute of Science
Bangalore - 560 012
India

June 2012
Acknowledgements

I am thankful to Dr. Vinod John for giving me the opportunity to work in Power Electronics
Group on interesting topic. His invaluable, timely suggestions and encouragement have been
extremely helpful throughout the course of the project. I also want to thank him for giving
me chances in activity apart from academic and his calm nature in that period. His course
on Topics in Power Electronics and Distributed Generation and working with him, gave me
a new dimensions of thinking.
I sincerely thank Prof. G. Narayanan for his excellent teaching on Power Electronics and
his lab courses offered, which helped a lot in my work.
I express my humble gratitude to Prof. V. Ramnarayanan for his book Course Material
on Switched Mode Power Conversion, which helped me to built my fundamentals.
I thank Prof. M. K. Gunashekaran and G. V. Mahesh of CEDT for their excellent courses
on Electromagnetic Compatibility and Electronics Systems Packaging, respectively.
I would like to thank Manoj Modi, who motivated me to become a part of IISc during
my graduation.
I thank Silvi madam for her kind help in collecting and purchasing material for my
work. I thank Mr. D. M. Channegowda, Mr. H. N. Purushottam for providing excellent
administrative help. I thank Mr. Ravi, Mr. Ramchandranan and other members of workshop
for helping me for my project.
I would like to thank Abhijit K. for the useful academic discussions I have had with him
and Pavan for introducing me to the world of LATEX. I also thank students of PEG group
for their help. I am grateful to Arjun, Chinmay, Nimesh C. for making my life pleasant at
IISc.
I thank Amit K. for sharing his knowledge of DSPIC. I also extent my thank to Krishna
Kumar for his support during entire period. I thank all M.E. friends of mine for helping me

i
ii Acknowledgements

in one way or the other. I thank all the persons who have helped me in my whole life.
I thank God for giving me strength at all times. Finally, I would like to thank my parents
for their support in me. Their faith boosted my confidence.
Abstract

This project deals with building the hardware for control power supply, which will feed power
to sub-systems of High Power Converters (HPC), even under abnormal input conditions.
In this work, power supply is designed to operate over a wide range of input voltage
variation, maintaining power factor close to unity and low total harmonic distortion in input
current. Isolation is provided between power side and control side in control power supply.
Overall, the project work involves the building of the power supply hardware, the filters,
transformer, start up circuit along with on board power supply and design and implementa-
tion of closed loop control.

iii
Contents

Acknowledgements i

Abstract iii

List of Tables vii

List of Figures viii

Nomenclature x

1 Introduction 1
1.1 Outline of Project Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Organization of the Project Report . . . . . . . . . . . . . . . . . . . . . . . 3

2 Topologies Selection and Specification 4

2.1 Topology for Pre-Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Topology for Isolated DC-DC Converter . . . . . . . . . . . . . . . . . . . . 5

3 Hardware Design 7
3.1 Pre-Regulator Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.1 Power Devices Selection . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.2 Gate Drive Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.3 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.4 Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.5 Loss Calculation of Pre-Regulator . . . . . . . . . . . . . . . . . . . . 9
3.2 Isolated DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

iv
Contents v

3.2.1 Transformer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2.2 Output Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.3 Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.4 Gate Drive Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.5 Snubber Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 On Board Power Supply and Start-up Circuit . . . . . . . . . . . . . . . . . 14

4 Control Design 16
4.1 Pre-Regulator Control Design . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 DSFC Control Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Issues in Control Loop of Pre-Regulator . . . . . . . . . . . . . . . . . . . . 22
4.3.1 Low Voltage Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3.2 Cusp Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5 Experimental Results 24
5.1 Pre-Regulator System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 Isolated DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Experimental Result on Start up Circuit . . . . . . . . . . . . . . . . . . . . 30

6 Conclusions 32

A General Expression for Boost Diode Current in Pre-Regulator 33

B Circuit Board Schematics 35

B.1 Start-up Power Circuit Schematics . . . . . . . . . . . . . . . . . . . . . . . 35
B.2 Pre-Regulator Circuit Schematics . . . . . . . . . . . . . . . . . . . . . . . . 36
B.3 Isolated DC-DC Circuit Schematics . . . . . . . . . . . . . . . . . . . . . . . 38

C Bill of Materials 40

D Testing and Assembling Procedure 45

E Protection Inhibits by CPS 46

F Pictures of Hardware Set-up 47

F.1 Pre-Regulator Power Circuit - Version 1.0 . . . . . . . . . . . . . . . . . . . 47
vi Contents

F.2 DSFC Power Circuit - Version 1.0 . . . . . . . . . . . . . . . . . . . . . . . . 48

F.3 Control Circuit - Version 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
F.4 Complete Hardware Set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

References 51
List of Tables

3.1 Voltage and Current Rating of Selected Device for Pre-Regulator . . . . . . 8

3.2 Inductor Design for Pre-Regulator . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Loss Tabulation of Pre-Regulator . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 HF Transformer of DSFC Design Summary . . . . . . . . . . . . . . . . . . . 11
3.5 Inductor Design for DSFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6 Voltage and Current Rating of Selected Devices for DSFC . . . . . . . . . . 12
3.7 Loss Tabulation of Power Devices in DSFC . . . . . . . . . . . . . . . . . . . 12

vii
List of Figures

1.1 Typical Block Diagram of Converter in a Application . . . . . . . . . . . . . 2

1.2 Block Diagram of Auxiliary Power Supply . . . . . . . . . . . . . . . . . . . 3

2.1 Circuit Diagram of Pre-Regulator Stage . . . . . . . . . . . . . . . . . . . . . 4

2.2 Circuit Diagram of Double Switch Forward Converter . . . . . . . . . . . . . 6

3.1 Gate drive circuit, Snubber and On Board Power Supply in DSFC . . . . . . 13
3.2 Circuit Diagram of Start-up Power Circuit . . . . . . . . . . . . . . . . . . . 15

4.1 Average Current Mode Control based UPF rectifier . . . . . . . . . . . . . . 16

4.2 Current Loop Model of Average Current controlled UPF Rectifier . . . . . . 17
4.3 Voltage Loop Model of Average Current controlled UPF Rectifier . . . . . . 17
4.4 Bode Plot of G1 (s) and G1 (s)Hcom i (s) . . . . . . . . . . . . . . . . . . . . . 18
4.5 Bode Plot of G2 (s) and G2 (s)Hv (s) . . . . . . . . . . . . . . . . . . . . . . . 19
4.6 Close Loop Control Structure of DSFC . . . . . . . . . . . . . . . . . . . . . 20
4.7 Voltage loop of DSFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.8 Bode Plot of G3 (s) and G3 (s)Gv (s) . . . . . . . . . . . . . . . . . . . . . . . 21
4.9 Effect on input current by multiplier input . . . . . . . . . . . . . . . . . . . 22

5.1 Pre-Regulator Waveform at Low Line and Rated Power . . . . . . . . . . . . 24

5.2 Pre-Regulator Waveform at High Line and Low Power . . . . . . . . . . . . 25
5.3 Step Load Change from ∼ 250W to ∼ 100W in Pre Regulator . . . . . . . . 26
5.4 Step Load Change from ∼ 100W to ∼ 250W in Pre Regulator . . . . . . . . 26
5.5 Step Load Change from ∼ 100W to ∼ 150W in Pre Regulator . . . . . . . . 27
5.6 DSFC Waveform at Rated Power . . . . . . . . . . . . . . . . . . . . . . . . 27
5.7 DSFC Waveform at Low Power . . . . . . . . . . . . . . . . . . . . . . . . . 28

viii
List of Figures ix

5.8 Step Load Change from ∼ 50W to ∼ 100W in DSFC . . . . . . . . . . . . . 29

5.9 Step Load Change from ∼ 50W to ∼ 125W in DSFC . . . . . . . . . . . . . 29
5.10 Output Voltage and Inductor Current during Overload in DSFC . . . . . . . 30
5.11 Waveform During Starting of Pre Regulator and DSFC (Part 1) . . . . . . . 30
5.12 Waveform During Starting of Pre Regulator and DSFC (Part 2) . . . . . . . 31

B.1 Start up Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

B.2 Power Circuit of Pre-Regulator Circuit . . . . . . . . . . . . . . . . . . . . . 36
B.3 Control Circuit of Pre-Regulator Circuit . . . . . . . . . . . . . . . . . . . . 37
B.4 Power Circuit of Isolated DC-DC Converter . . . . . . . . . . . . . . . . . . 38
B.5 Control Circuit of Isolated DC-DC Converter . . . . . . . . . . . . . . . . . 39

F.1 Pre-Regulator Hardware Picture . . . . . . . . . . . . . . . . . . . . . . . . 47

F.2 DSFC Hardware Picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
F.3 Control Hardware Picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
F.4 Complete Hardware Set up Picture . . . . . . . . . . . . . . . . . . . . . . . 50
Nomenclature

Symbols : Definitions
HP C : High power converter
CP S : Control Power supply
Pin : Input power to auxiliary power supply
vin : Instantaneous 1φ input voltage
iin : Instantaneous 1φ input current
ωo : Fundamental line frequency in rad/sec
Vint : Voltage of pre-regulator DC bus
Pint : Pre-regulator output power
Lb : Pre-regulator inductor
Cint : Pre-regulator DC bus capacitor
T HD : Total harmonic distortion
ESR : Equivalent series resistance
Vo : Output of auxiliary power supply
Lo : Output filter inductor
Co : Output capacitor
im p : Magnetising current of transformer of isolated DC-DC converter refer to primary
Po : Isolated DC-DC converter output power
n : Turns ratio of isolated high frequency transformer
N1 : No. of turns in primary of isolated high frequency transformer
N2 : No. of turns in secondary of isolated high frequency transformer

x
Chapter 1

Introduction

High Power Converters (HPC) play key role in industrial growth, used in power conditioning,
drive application etc. To perform their task, HPC require robust sub-systems like gate drive
card, protection card, annunciation card etc. Those sub-systems need power at specified
voltage to perform their task. Unable to meet specification of sub-systems may result in
malfunctioning of sub-systems, which can cause undesirable operation on HPC and may
damage the costlier HPC. So, power to sub-system (CPS) plays critical role in operation of
HPC.
The require characteristics of a control power supply are:

• Reliable and inexpensive

• Tight line and load regulation

• Good dynamic performance

• Isolation

• Rejection of input disturbance in output

A typical converter application block diagram is shown in Fig. 1.1, in which high power
converter processes the input to perform require application with the help of sub-systems.
Power required for sub-systems are drawn from control power supply, derived from the input.

1
2 Chapter 1. Introduction

Sub-Systems
Control Card
Gate Drive card

Control Sensing Card

Protection Card

Power
Supply

Input Load

Converter
Figure 1.1: Typical Block Diagram of Converter in a Application

1.1 Outline of Project Tasks

The project involves -

• Design of Pre-Regulator Stage - In designing power supply, input is AC, while output
is DC. So, there is need of rectification. Also, this stage provides a constant output
voltage for a wide range of input voltage with unity power factor operation.

• Design of Dc-Dc Isolated Power Converter - For providing isolation between power
circuit and control circuit and for achieving faster voltage loop dynamics, it requires
another converter stage. This involves the choice of converter to achieve desire opera-
tion and its control circuit design.

• Testing of system for desire features.

The region inside dashed line in Fig. 1.2 shows the configuration of the power supply to
be designed. The ME report[12] specifies the control power requirement of one high power
converter to be ∼ 80W . Providing the margin of 20%, we will require ∼ 100W for one
converter. So, for operation of two converters, operating in parallel or back to back, control
power requirement will be ∼ 200W . 50W is included to charge the energy storage system for
1.2. Organization of the Project Report 3

providing back-up. So, design is done for supplying 250W of power at 24V . The variation
in vin is taken from 90V ac to 270V ac.
+15V -15V GND

Vin Vint Vo Control cards

Power supply
24V
+
250W Energy Storage
90Vac-270Vac
Pre-Regulator Isolated DC- Charging
Stage DC converter

+5V +12V -12V

Figure 1.2: Block Diagram of Auxiliary Power Supply

1.2 Organization of the Project Report

In chapter 2, the topologies for pre-regulator and isolated DC-DC converter are selected and
the specification are given for corresponding stages.
Chapter 3 discusses the hardware design of pre-regulator and isolated DC-DC converter
in detail, which includes magnetics design, switches selection, capacitor sizing, gate driver
design, estimation of losses in each component, snubber design, start up circuit and on board
power supply design.
Chapter 4 includes the details of the control system design for pre-regulator and isolated
DC-DC converter along with various control issues.
In chapter 5, experimental results on pre-regulator and isolated DC-DC converter with
the pertinent waveforms are discussed. Conclusions are discussed in chapter 7.
The schematics of power and control board of pre-regulator and isolated DC-DC con-
verter, the pictures of the hardware, bill of materials, testing and assembling procedure,
general diode current expression of pre-regulator and protection inhibits by CPS are pro-
vided in Appendix.
Chapter 2

Topologies Selection and Specification

In this chapter, topologies for pre-regulator and isolated DC-DC converter are selected among
the available topologies and their specification in terms of power, voltage and switching
frequency are specified.

2.1 Topology for Pre-Regulator

D5

Lb Db
D1 D2
Vin C1 Sb
C Vint
fuse int

D3 D4

Diode Rectifier Boost Stage

Figure 2.1: Circuit Diagram of Pre-Regulator Stage

As available power is AC, but output require DC, so rectification required. For rectifica-
tion, 1φ diode bridge followed by capacitor filter can be used as output power requirement
is low. But, it will draw peaky non-sinusoid current with substantial harmonic content

4
2.2. Topology for Isolated DC-DC Converter 5

from supply result in poor power factor. This is a concern of power quality. According to
IEC − 555 and IEEE − 519, it specify maximum limits for the amount of current allowed
at each harmonics of the line frequency. So, boost stage followed by 1φ diode bridge is used
to meet the standards by ensuring the unity power factor operation of rectifier. Boost stage
is chosen for current shaping as it’s input current is continuous and hence, required less
filtering at the input. Fig. 2.1 is the circuit of the pre-regulator stage. By controlling the
duty cycle of switch Sb , inductor current can be shaped as rectified sine.
The function of diode D5 is to avoid voltage doubling at Cint due to Lb − Cint oscillations
at starting by bypassing the inductor at starting. Under normal operating condition with
|vin | < Vint , D5 is in reverse bias and does not affect the boost operation. The function of
capacitor C1 is to filter the switching current from inductor current.
Pre-regulator stage is designed for 300W input power as to include 250W output power
and 50W in losses of system assuming ηsystem ∼ 80%, switching frequency of switch Sb is
chosen to be 100kHz and vin range is taken from 90 − 270V ac. So, intermediate voltage Vint
is chosen as 400V DC as to keep Vint > |vin max (peak)|.

2.2 Topology for Isolated DC-DC Converter

For isolated DC-DC converter Double Switch Forward Converter(DSFC) is chosen. Fig. 2.2
is the circuit of the double switch forward converter. Both switches S1 and S2 gets same
PWM.
It exhibits following advantages:

• Simple transformer design

• Device voltage rating is the same as the DC bus voltage

• Simple dynamic model and easy closed loop control

• Clamp diodes recovers magnetising energy in the core.

• Output filter requirement is low

• Better utilization of winding copper

The limitation of the circuit is that two power switches are needed with the associated
drive circuits and unidirectional flux swing in the core which limits the maximum duty cycle
6 Chapter 2. Topologies Selection and Specification

to 50%. Unidirectional flux swing is not much concern to transformer size compare to other
topologies with bidirectional flux swing because at high frequencies in transformer design,
change in flux swing is dictated by core loss to limit the temperature rise of core. So, core
of DSFC is utilised as good as the other isolated topologies with bidirectional flux swing at
high operating frequencies.

Figure 2.2: Circuit Diagram of Double Switch Forward Converter

Double switch forward converter is designed for 250W output power at 24V as to in-
clude 200W control output power and 50W power for charging of energy storage, switching
frequency of switches S1 and S2 are chosen to be 120kHz.
Chapter 3

Hardware Design

This chapter deals with the hardware design of pre-regulator and isolated DC-DC converter
which includes magnetics design, switches selection, capacitors sizing, gate driver design,
estimation of losses in each component, snubber design, start up circuit and on board power
supply design.

3.1 Pre-Regulator Power Circuit

3.1.1 Power Devices Selection
Diodes of diode bridge require to have peak reverse voltage rating more than vin max (peak) ∼
iL max (peak)
400V and average forward current rating more than π
∼ 1.5A. For diode D5 Surge
current is a concern, not continuous current.
Boost diode, Db and boost switch, Sb require to have blocking voltage of more than Vint
and peak current rating more than iL max (peak). Also, boost diode should have low reverse
recovery time and reverse recovery charge and boost switch should have low switching times
to minimize the switching losses. Table 3.1 lists the selected devices for pre-regulator along
with their voltage and current rating.

3.1.2 Gate Drive Circuit

A simple gate resistance based drive is chosen for driving boost MOSFET. A gate resistance
of 15Ω during turn ON and gate resistance of 10Ω during turn OFF is chosen, which got
PWM from control IC of pre-regulator. A zener across gate-source of MOSFET is used to
clip gate voltage within limit.

7
8 Chapter 3. Hardware Design

Table 3.1: Voltage and Current Rating of Selected Device for Pre-Regulator
Device Selected Device Blocking Voltage Rating Current Rating
Rectifier Diodes SK3GL10 1000V 3Aav
Diode D5 SK3GL10 1000V 150Asurge
Boost diode MUR860 600V 8Aav
Boost switch IRF840 500V 8Acont

3.1.3 Inductor Selection

The current ripple, δiLb of inductor Lb is given as -

(Vint − |vin |) ∗ |vin |

δiLb = (3.1)
Lb ∗ fsw ∗ Vint

where, δiLb is peak-peak ripple in inductor current, Vint is output voltage of pre-
regulator stage, |vin | is absolute value of instantaneous input voltage, Lb is boost inductor
value, fsw is switching frequency of Sb .
Vint
δiLb max will occur at |vin | = 2
. Taking δiLb max = 20% of iLb max , inductor value can
2∗Pin max
be found using equ. (3.1). We have, iLb max = vin min (peak)
, where Pin max is maximum value
of average input power equal to Pint max by neglecting losses, gives iLb max = 4.7Amps. So,
by using equ. (3.1), we get Lb ' 1mH.
Inductor design was done based on area product approach[1] and design is tabulated in
Table 3.2.

Table 3.2: Inductor Design for Pre-Regulator

4.7
Specification iLb (peak) = 1.1 ∗ 4.7 = 5.2A, iLb (rms) = √
2
= 3.3A,
Lb = 1mH
Core Selected EE 42/21/20 (ferrite core)
No. of turns 107
Wire size 1 conductor of SW G 19
Air gap in core 3.5mm
Mean Length of Turn 95mm
Resistance of inductor, RLb (21.27 ∗ 10−6 ) ∗ 95 ∗ 107 = 0.22Ω
3.1. Pre-Regulator Power Circuit 9

3.1.4 Capacitor Selection

Capacitor, Cint value is chosen based on the second harmonic ripple voltage present in
capacitor[5], whose peak value is given as -
Pint
δVint = (3.2)
2ωo Cint ∗ Vint
where, ωo is the angular velocity of fundamental component of vin in rad/sec.
Take δVint = 1.5% ∗ Vint at Pint max , so by using equ. (3.2), we get the value of capacitor
Cint ' 220µF . Also, capacitor Cint must rated for > 400V and able to handle maximum
value of ripple current id 100Hz ∼ 0.53A, id f sw ∼ 1.46A and next stage ripple currents.
2-470µF 250V capacitors of NIPPON CHEMI-CON SMQ series with ESR120Hz = 0.42Ω,
are used in series and can carry 2.11A120Hz at 85o C fulfil the requirement.

3.1.5 Loss Calculation of Pre-Regulator

For loss calculation, ripple in inductor current is neglected. Losses are tabulated in Table 3.3
at maximum power Pin max ∼ 300W and minimum input voltage vin min ∼ 90Vac with
Vint = 400V [4].

Table 3.3: Loss Tabulation of Pre-Regulator

Device Parameters Losses
Diode Vf = .85V, rd = 30mΩ, iav = 1.5A, irms = 2.4A 4 ∗ (0.85 ∗ 1.5 + 0.03 ∗
Bridge 2.42 ) = 5.8W
Inductor RLb = .22Ω, irms = 3.3A 0.22 ∗ 3.32 = 2.4W
Boost Qrr = 195nC, V r = 400V, fsw = 100kHz (195n ∗ 400/2) ∗ 100k =
diode 3.9W
Vf = 1.5V, iav = 0.75A 1.5 ∗ 0.75 = 1.13W
Boost tr = 35ns, tf = 30ns, Ts = 10µs, Vb = (2/π) ∗ ((35 + 30)n ∗ 400 ∗
switch 400V, ipeak = 4.7A 4.7)/10µ = 7.8W
Rd on = 0.85Ω, irms = 2.8A 0.85 ∗ 2.82 = 6.8W
Cint ESR120Hz = 0.42 ∗ 2 = 0.84Ω, ESR<50kHz = 0.84∗0.532 +0.37∗1.462 =
0.37Ω, irms 100Hz = 0.53A, irms 100kHz = 1.46A 1W

A sensing resistance of 0.2Ω is used to sense inductor current, which causes loss of
i2L max (rms) ∗ Rsense1 = 3.32 ∗ 0.2 ∼ 2.2W .
10 Chapter 3. Hardware Design

So, total losses in pre-regulator is ∼ 30W at Pin = 300W and vin = 90V ac. At these
operating condition, we got efficiency ηpre ∼ 90%.

3.2 Isolated DC-DC Converter

3.2.1 Transformer Design

For Vo = 24V at Vint = 400V and d = 0.35, using Vo = Vint n

d gives n ' 6. Using Ac Aw =
2Vint dmax iS1 rms
√
∆Bkw Jfs
with Vint = 400V, IS1 rms ' 10.5
6
0.5 = 1.23A, ∆B = 0.25T, kw = 0.3, fs =
120kHz, dmax = 0.5 and J = 3.5A/mm2 , we got Ac Aw = 1.56cm4 .
Vint dmax
We selected ETD39 core with Ac = 1.25cm2 and Aw = 1.77cm2 [6]. With N1 = ∆Bfs Ac
,
we got N1 ' 54, which makes N2 = 9.
iS1
With aw1 = rms
J
, we got aw1 ' 0.41mm2 , similarly aw2 ' 2.47mm2 . We selected 1
conductor of SWG21 with aw = 0.52mm2 and R = 33.23Ω/km for primary and 4 conductors
of SWG21 in k for secondary.
Core material is N87 with µr ' 2000, also mean length of flux path, lm ' 92mm. So, we
µo µr Ac N12 Vint
got Lm p ' 9mH, which gives im p (max) = 0.19A using Lm p = lm
and im p = Lm p
dTs
respectively.
Also, mean length of turn, lw ' 69mm, which gives Rp = 33.23 ∗ 69e − 6 ∗ 54 = 0.12Ω,
similarly Rs = 5.2mΩ. So, Ptr culoss = (1.232 ∗ 0.12 + 7.422 ∗ 5.2e − 3) = 0.47W .
Core loss in transformer is given as [9]-

Pcoloss = Vc (cm3 ) k Bac(mT )a fs (kHz)b mW (3.3)

At 120kHz, for N87 ⇒ k = 3.34e − 6, a = 2.7, b = 1[9] and core volume of ETD39,
Vc = 11.5cm3 . For our application Bac = Bmax − Bav = 200 − 100 = 100mT . So, Ptr coloss =
1.2W , therefore Ptr total ' 1.7W . Rth of core is 23.7o C/W , so temperature rise of core above
ambient is 41o C.
Leakage inductance of primary for sandwiched secondary between half of the two pri-
µo N12 lw bw µo ∗542 ∗69e−3∗8.25e−3
mary by using MMF method [9] is given as, Lσ1 = 3p2 hw
= 3∗12 ∗28.4e−3
' 25µH.
N22
Therefore, Lσ2 = L
N12 σ1
' 0.7µH.
The summary of DSFC transformer given in Table 3.4 and design was based on area
product approach[1].
3.2. Isolated DC-DC Converter 11

Table 3.4: HF Transformer of DSFC Design Summary

Specification Vint = 400V , d = 0.35, B(d=0.35) = 0.2T , iS2 max (rms) = 10.5A,
fs = 120kHz
Core Selected ET D39 (ferrite core)
No. of turns N1 = 54, N2 = 09
Wire sizes N1 ⇒ 1 SW G 21 conductor, N2 ⇒ 4 SW G 21 conductors in k
Lm p 9mH
Resistance Rp = 0.12Ω, Rs = 5.2mΩ

3.2.2 Output Filters

We have -
(1 − d)Vo
δiLo (p − p) = (3.4)
Lo fs
For δiLo (p − p) = (15% of Iomax ) = 1.6A and d = 0.35, we got Lo ' 80µH, with
iLo peak = 10.5 ∗ (1 + .15/2) = 11.3A and iLo rms ' 10.5A.
Inductor design was done based on area product approach[1] and tabulated in Table 3.5.

Table 3.5: Inductor Design for DSFC

Specification iLo (peak) = 11.3A, iLo (rms) = 10.5A, Lb = 80µH
Core Selected EE 42/21/20 (ferrite core)
No. of turns 19
Wire size 1 conductor of SW G 14
Air gap in core 1.25mm
Mean Length of Turn 95mm
Resistance of inductor, RL0 5.31 ∗ 10−6 ∗ 95 ∗ 19 = 0.01Ω
Losses 1.1W

(1−d) Vo 0.7 24
For δvo = 1% of Vo = 0.24V , Co > 8Lo fs2 δvo
= 8∗40µ∗(120k)2 0.01∗24
' 15µF and ESRCo <
δvo 0.01∗24
δic
= 10.5∗0.3
' 77mΩ at 120kHz.
We chose, 4-330µF 50V capacitors of JAMICON TQ series, in k with 1 capacitor having
ESR(<10kHz) ' 0.257Ω and iripple@105o C 120Hz ' 480mArms .
0.257 (0.15∗10.5)2
So, Ploss Co = ESR ∗ i2c rms ' 4 12
' 14mW .
12 Chapter 3. Hardware Design

3.2.3 Power Devices

Primary switches S1 and S2 require to have blocking voltage of more than Vint and rms
current rating more than iS1 rms (max), clamp diodes DC1 and DC1 require to have blocking
voltage of more than Vint and rms current rating more than im rms (max). Secondary diodes
(rectifier + free-wheeling) should have low forward drop to minimize conduction loss and
Vint
require to have blocking voltage of more than n
and average current rating more than
[iLo (max) ∗ d] for D1 (rectifier diode) and [iLo (max) ∗ (1 − d)] for D2 (free-wheeling diode).
Table 3.6 lists the selected devices for DSFC along with their voltage and current rating
and Table 3.7 tabulated devices losses[4] at rated power(250W) and 400V input voltage.

Table 3.6: Voltage and Current Rating of Selected Devices for DSFC
Devices Selected Blocking Voltage Current
Device Rating Rating
Primary Switches S1,S2 IRF840 500V 8Aav
Clamp diodes DC1 ,DC2 MUR460 600V 4Aavg
Secondary diodes D1,D2 MBR20200CT 200V 10Aav

Table 3.7: Loss Tabulation of Power Devices in DSFC

Device Parameters Losses
MOSFET tr = 35ns, tf = 30ns, Ts = ((1/2)((35 + 30)n ∗ 400 ∗
IRF 840 8.3µs, Vb = 400V, imax = 1.8A 1.8)/8.3µ) ∗ 2 = 5.7W
Rd on = 0.85Ω, irms = 1.1A (0.85 ∗ 1.12 ) ∗ 2 = 2.1W
DIODE Vd = .7V, rd = 20mΩ, iav = 3.7A, 0.7 ∗ 3.7 + 0.02 ∗ 6.22 =
M BR20200CT irms = 6.2A 3.4W
(rectifier)
DIODE Vd = .7V, rd = 20mΩ, iav = 6.9A, 0.7 ∗ 6.9 + 0.02 ∗ 8.52 =
M BR20200CT irms = 8.5A 6.3W
(freewheeling)

A sensing resistance of 0.45Ω is used to sense primary switch current, which causes loss
of i2S1 (rms) ∗ Rsense2 = 1.52 ∗ 0.45 = 1.2W .
3.2. Isolated DC-DC Converter 13

Total loss in DSFC at rated power 250W and 400V input voltage = 1.7 + 1.1 + 0.014 +
5.7 + 2.1 + 3.4 + 6.3 + 1.2 ' 22W . Therefore, ηdsf c ' 92%.

3.2.4 Gate Drive Circuit

A transformer based gate drive circuit is used as high side drive is required. Due to operating
at high frequency and duty ratio is limited to 50%, drive transformer design is simple.
A forward converter with reset winding with two secondary is used as drive transformer,
which is driven by transistor Q1 . Rb q1 provides steady sate base current, while C1 and R1
is used to provide surge current during turn ON and OFF of Q1 . A gate resistance of 12Ω is
used during turn ON, while PNP based turn OFF circuit is used. A zener across gate-source
of MOSFET is used to clip gate voltage within limit. RCD Turn OFF snubber is used to
dV
limit dt
across switch during turn OFF.

R
sn_OFF1
C
sn_sec1

.
R
Rg_on Don G sn_sec1
S1 D
sn_OFF1

.
S1 C D1
Z1
Vcc sn_OFF1 L 2
Q2 N2
L D2
Rb_q2 Rg_off
S
S1 m1
N1
V

.
obps
Dobps
L C
C1 R1 m3 obps
N3
Q1 S2
PWM Rb_q1

Gnd

Figure 3.1: Gate drive circuit, Snubber and On Board Power Supply in DSFC

3.2.5 Snubber Design

RCD Turn OFF snubber of primary switch is optimise to reduce total losses in (switch +
snubber) at higher switch current[1]. Snubber diode, Dsn OF F is selected M U R160 with
voltage rating of 600V and current rating of 1A. Snubber capacitor selected as Csn OF F =
iS1 (max)∗tf
2∗Vint
, where tf is the fall time of the device. We got-
14 Chapter 3. Hardware Design

Csn OF F = 100pF
ton (min)
The resistance Rsn OF F to discharge Csn OF F is selected based on Rsn OF F ' 5∗Csn OF F
.
Taking ton (min) = 100ns. We got-
Rsn OF F = 400Ω
To avoid oscillation between secondary leakage inductance and secondary diode capacitor
during switching, RC snubber is used. Csn sec is selected 10 times higher than diode capacitor
and Rsn sec is selected
r to critical rdamped series LCR circuit. So, Csn sec = 10∗25pF = 250pF
  
Lσ2 0.7µ
and Rsn sec = 12 Csn sec
= 12 250p
' 33Ω are selected.

3.3 On Board Power Supply and Start-up Circuit

For supplying power to control IC of pre-regulator, isolated DC-DC converter and relay, an
on board power supply is built, which uses auxiliary secondary to the transformer of isolated
converter connected in fly-back mode.
Maximum output voltage of on-board power supply under no-load is given as-

N3
Vobps = Vint (3.5)
N1

Keeping no-load Vobps = 25V , with Vint = 400V and N1 = 54, we got N3 = 3.4 ∼ 4,
which will result in no-load Vobps = 30V .
Dobps diode is selected M U R110 with voltage rating of 100V and current rating of 1A
and Cobps is selected as 22µF .
In Fig. 3.2, start-up power circuit is shown. In the absence of power from on-board power
supply at starting, voltage at Cap is build up by charging of Cap through high voltage Vint
with resistance Rst lmt to limit the current. MOSFET Sst is turned on initially by providing
biasing voltage through Rsb1 and Rsb2 . A zener Z1 across Cap is used to clip the voltage Vcon .
After on-board power supply is available, MOSFET Sst is turned off by turning on switch
Qsof f , which will make gate-source voltage across Sst negative. Qsof f is turned on by using
on-board power supply as biasing.
Relay which is used to limit the inrush current at starting, is powered by on-board power
supply. Resistance Rr is used to reduce voltage Vrelay to ∼ 12V from partially regulated
voltage Vobps . After start-up under normal operating condition, control voltage Vcon is also
maintained by on-board power supply by zener based regulated supply.
3.3. On Board Power Supply and Start-up Circuit 15

+Vint

Rsb1 Rst_lmt

V
relay

S_st
R_r
D1 Rz1
V Rb_soff Vcon
obps
Rsb2 V
obps
Q_soff C
Rbe_soff obps
Cap Z1
-Vint

Figure 3.2: Circuit Diagram of Start-up Power Circuit

Control IC and gate drive circuit requires ∼ 70mA. Also, turn on voltage of IC is 16V
from off condition, while 10V is IC turn off voltage.
2Pcon tstarting
So, capacitor Cap is chosen based on Cap = (Vi2 −Vf2 )
, where Pcon is the control IC power,
tstarting is the time from system starting upto on-board power supply become active, Vi is
turn on voltage of IC from off condition and Vf is IC turn off voltage. For tstarting = 20ms,
2∗(0.07∗16)∗0.02
we have Cap = (162 −102 )
∼ 300µF . So, Cap is chosen 420µF . Rst lmt is selected 4.7kΩ,
which will require around ∼ 0.35sec for Vcon to rise from 0V to 16V during starting at low
line voltage.
Rsb1 is selected 1.5M Ω. For VRsb2 ∼ 3.5V at Vint ∼ 120V (low line), we require Rsb1 ∼
42kΩ. At high voltage VRsb2 ∼ 14V .
Rbe of f is selected 10kΩ. For VRbe of f ∼ 0.6V at Vobps ∼ 10V , we require Rb of f ∼ 180kΩ.
Switch Sst is selected as MOSFET IRF 820 having voltage rating 500V and continuous
current rating 2.5A, while switch Qsof f is selected as BJT 2n2222 having voltage rating 40V
and maximum current rating 800mA.
Chapter 4

Control Design

This chapter discusses the control design for pre-regulator and DSFC along with various
control issues.

4.1 Pre-Regulator Control Design

Figure 4.1: Average Current Mode Control based UPF rectifier

For UPF rectifier control, a dedicated IC UC3854AN from Texas Instruments has been
chosen, which works on average current mode control[3] as it’s inner current loop to control

16
4.1. Pre-Regulator Control Design 17

output voltage as outer loop. Fig. 4.1 shows the control structure of average current mode
control based UPF rectifier[1].
The rectified sinusoidal current reference is generated using a multiplier which has recti-
fied bridge voltage (x in Fig. 4.1) as it’s one of the input. The another input to the multiplier
is corresponds to output voltage error (y in Fig. 4.1). The third input is a feed forward term
(z in Fig. 4.1) which is proportional to RMS value of input voltage obtained by passing input
rectified voltage to the a low pass filter.
In the absence of feed forward term, any change in input voltage get reflected in the
current reference, making input current to change by the same ratio as to the input voltage,
which makes input power change by square to the change of input voltage. This makes power
imbalance between input and output, results in output voltage transients.
So, by dividing the current reference by square of RMS value of input voltage causes
input current to decrease by same ratio, results in unchanged input power, which generates
no output voltage transient because of the input voltage change. Due to time constant of
low pass filter associated to the feed forward term generation results in little transients in
output voltage because of the input voltage change.
The current loop is represented in Fig. 4.2 and voltage loop is represented in Fig. 4.3.

G1 (s)
iL_ref iL_error H iL
1 ds iL
com_i
Vosc ds
iL_fb
Figure 4.2: Current Loop Model of Average Current controlled UPF Rectifier

G2 (s)
vint_ref vint_error vvea vint vint
Hv
vint_fb vvea

Figure 4.3: Voltage Loop Model of Average Current controlled UPF Rectifier

where, Vosc is peak -peak value of PWM carrier and equal to 5.5V .
18 Chapter 4. Control Design

We have, control transfer function, inductor current to duty cycle for average mode
control as [1]-
" #
îL (s) Vint 2 + sCR
= (4.1)
dˆs (s) R(1 − Ds )2 1 + s LRe + s2 Le Co

Lb
where, Le = (1−Ds )2
.
On substituting different values in equ. (4.1), we have-
 
îL (s) 2 + 0.125s
= 0.75 (4.2)
dˆs (s) 1 + 1.876 ∗ 10−6 s + 0.235 ∗ 10−6 s2

Hcom i (s), current controller is chosen as Proportional Integral (PI) controller. Zero is
kept at √ 1 rad/s . Bandwidth can be achieved by changing the proportional gain of PI
Le Co
controller and kept near at 15kHz. A high frequency pole is added in Hcom i (s) to attenuate
the noise. Hcom i (s) is selected as -
s


1.4 1 + 2π340 1
Hcom i (s) = s s

(4.3)
2π340 1+ 2π100e3

100
G1
Magnitude (dB)

50
G1 H com_i
0

−50

−100
90 System: cur_oltf
Phase Margin (deg): 79.7
Phase (deg)

0 Delay Margin (sec): 1.39e−005

At frequency (Hz): 1.6e+004
Closed Loop Stable? Yes
−90

−180
−1 0 1 2 3 4 5 6 7
10 10 10 10 10 10 10 10 10
Frequency (Hz)

Figure 4.4: Bode Plot of G1 (s) and G1 (s)Hcom i (s)

Bode Plot of G1 (s) and G1 (s)Hcom i (s) is shown in fig. 4.4.

We have, [13]
v̂int (s) Kac Rmo R(1 − Ds )
= (4.4)
v̂vea (s) 2Vint Rs Kf2f 1 + s RC
2
o

1 1
On substituting different values in equ. (4.4), where Kac = Rac
= 1.5M Ω
, Rmo = 6.8kΩ,
4.2. DSFC Control Design 19

Vf f 1.5
Rs = 0.2Ω, Kf f = Vin (rms)
= 90
= 0.0167 and Vint = 400V , we have-

v̂int (s) 51
= (4.5)
v̂vea (s) 1 + 0.0625s
RCo
Hv (s), voltage controller is chosen as PI controller. Zero is kept at 2
rad/s. A pole is
added near the bandwidth of voltage controller. Bandwidth of voltage controller is kept near
at 25Hz as to attenuation 100Hz ripple voltage of Vint , so that total harmonic distortion
(THD) in input current can be minimized as 1% of 100Hz component to DC value in output
of voltage error amplifier produces 0.5% of 3rd harmonic to fundamental in input current iin .
Hv (s) is selected as -

s
0.282 1 + 2π2.72
Hv (s) = s s (4.6)
1 + 2π27.2 2π2.72

60
G2
40
G2 H v
Magnitude (dB)

20

−20

−40

−60
0

−45 System: vol_oltf

Phase (deg)

Phase Margin (deg): 45.7

−90 Delay Margin (sec): 0.00484
At frequency (Hz): 26.2
Closed Loop Stable? Yes
−135

−180
−1 0 1 2 3
10 10 10 10 10
Frequency (Hz)

Figure 4.5: Bode Plot of G2 (s) and G2 (s)Hv (s)

Bode Plot of G2 (s) and G2 (s)Hv (s) is shown in fig. 4.5.

4.2 DSFC Control Design

For controlling DSFC, IC UC3844 which uses peak current control as it’s inner loop to
control the output voltage in outer loop is used[10]. The peak current control exhibits faster
dynamic response and simple control implementation due to absence of inductor current as
20 Chapter 4. Control Design

a state in control loop, reducing second order plant to first order. Also, peak current control
inherits current limit in it’s control structure.
Also, The peak current control used in buck based converter ideally makes output voltage
independent of the input voltage variation[8]. In practical, input voltage variation has little
impact on output voltage in peak current control, which also can be avoided by proper choice
of compensating ramp.
The peak current control is sensitive to noise. So, current blanking circuit is used to
remove leading edge noise present in system during switching . Also slope compensation is
added, which improves noise immunity.
For transferring the output voltage information across isolation boundary, IC UC3901
from Unitrode based on amplitude modulation, along with a small toroid for electrical iso-
lation, is used[11]. For extracting information on other side, a peak detector circuit is used.
The close loop control structure for DSFC is given in Fig. 4.6, in which the output voltage
is regulated in outer loop by controlling peak current as inner loop.

Signal Transformer
High frequency Carrier High frequency

High frequency
Power Transformer

d Peak
Detector

Figure 4.6: Close Loop Control Structure of DSFC

Voltage loop is shown below:

Figure 4.7: Voltage loop of DSFC

4.2. DSFC Control Design 21

1
where, Co = 1320µF , Rs = 0.45Ω, Lo = 80µH, n = 6, RESR = 0.06425Ω, RL Co = 2π52
,
1 Rd 1
RESR Co = 2π1.9k
and Lo
= 2π17k
.

Gv (s) is seleced as:

s
700 2π50
+1
Gv (s) = s

s


s 2π1.9k
+1 2π40k
+1
which gives bandwidth of voltage loop 3.5kHz and phase margin of 68o . Bode Plot
of G3 (s) and G3 (s)Gv (s) is shown in fig. 4.8.
100
3
50
Magnitude (dB)

3
0

−50 System: volt_oltf

Gain Margin (dB): 24.5
At frequency (Hz): 2.6e+004
−100 Closed Loop Stable? Yes

−150
0
Phase (deg)

−90
System: volt_oltf
Phase Margin (deg): 68.2
−180 Delay Margin (sec): 5.4e−005
At frequency (Hz): 3.51e+003
Closed Loop Stable? Yes
−270
0 1 2 3 4 5 6
10 10 10 10 10 10 10
Frequency (Hz)

Figure 4.8: Bode Plot of G3 (s) and G3 (s)Gv (s)

This is implemented as:

UC3901:
s
300 2π50
+1
Gv1 (s) = s


s 2π1.9k
+1
UC3844:
2.3
Gv2 (s) = s


2π40k
+1
The signal toroid for transferring voltage error information across isolation boundary is
designed for the magnetising inductance of ∼ 500µH[11] with carrier frequency to be 500kHz
of U C3901, peak carrier voltage across transformer inputs to be 2V and bias current of
U C3901 drivers to be 2mA.
22 Chapter 4. Control Design

4.3 Issues in Control Loop of Pre-Regulator

4.3.1 Low Voltage Bandwidth
The current reference is generated using multiplying rectified voltage and other inputs (say,
y). The rectified voltage can be express as the multiplication of input voltage to the diode
bride modulation function, which is unit rectangular at the line frequency.

i in Vin* y iL Vin* d mod * y d mod sin( ) d

+1.2
+1.0
* mod
+0.8
+0.6
+0.4

Vin |Vin| Vin* d mod +0.2

−0.4 +0.6 +1.4 +2.2 +3.0 +3.8 +4.6 +5.4 +6.2

−0.2
−0.4

x Vin* d mod
−0.6
−0.8
−1.0

x*y
i ref Vin* d mod * y
y

Figure 4.9: Effect on input current by multiplier input

From Fig. 4.9, it can be seen that the inductor current follow the reference current due to
high bandwidth of current controller, which passes from diode bride acting as a demodulator
generates input current, which can be express as the multiplication of input voltage and the
voltage y.
So, 2ω component present in y apart from DC generates ω and 2ω frequency component
in input current. The magnitude of those component to fundamental component in input
current is equal half the the ratio of DC to 3ω component present in y. This result in increase
in total harmonic distortion of current and depending on the phase of 100Hz component
present in y with the fundamental 50Hz of input voltage causes decrement in displacement
power factor.
So, 100Hz component present in y causes increase in total harmonic distortion and
decrement in displacement power factor. So, the 100Hz present in output voltage should be
suppress by desire amount to achieve better power factor and low total harmonic distortion
in input current. Therefore, the voltage bandwidth should kept below 100Hz, so that it can
attenuate 100Hz component present in output voltage.
4.3. Issues in Control Loop of Pre-Regulator 23

4.3.2 Cusp Distortion

Near zero crossing, the required slope of input current is highest and given by ω ∗ Iin (peak),
where Iin (peak) is peak value of input current. If average slope generated by converter is
less than the required slope, then current will not able to follow the reference. This is more
pronounce at higher peak current. Cusp distortion is also affected by converter operating
frequency and the inductor value used.
Cusp distortion will occur when-
Required slope of current < Average slope produced by converter
This result in the condition for cusp distortion as-
|vin | < (2 Lb ω iL b (peak) + Vint (1 − dmax ))
Chapter 5

Experimental Results

This chapter presents the experimental results of the hardware of pre-regulator and DSFC.

5.1 Pre-Regulator System

The Fig. 5.1 is at Rload ∼ 550Ω and vin ∼ 95Vac , the THD in current measured using FLUKE
Power Analyser at these condition is ∼ 12% with unity power factor and η ∼ 90%, while
Fig. 5.2 is at Rload ∼ 1500Ω and vin ∼ 260Vac , the THD in current is ∼ 7.5% with unity
power factor and η ∼ 99%. We have, Vint ∼ 386V .
In Fig. 5.1 and Fig. 5.2, vin (Ch.1), iin (Ch.2), Vint (Ch.3) and Iint (Ch.4). Math shows
the input power.

i in
Vint

I int vin

Pin

Figure 5.1: Pre-Regulator Waveform at Low Line and Rated Power

24
5.1. Pre-Regulator System 25

I int

Vint vin
i in

Pin

Figure 5.2: Pre-Regulator Waveform at High Line and Low Power

As grid voltage has a THD of ∼ 3%, which directly contributing in the THD of current.
Also, at low grid voltage cusp distortion increases the THD in the current and remaining
THD in current is contributed by control loop. Also, as we are going at higher grid condition,
efficiency of system improves due to decrease in conduction and switching losses of system
as for current decreases for same power level.
Fig 5.3, shows the unloading of pre-regulator from ∼ 250W to ∼ 100W with vin ∼ 90V ac.
It can be noted that in around one cycle (20ms) our control loop gets back to the steady
4 4
state, which is close to the designed settling time of system, tset = Bandwidth
= 2π27
∼ 24ms.
For Fig 5.3, Fig 5.4 and Fig 5.5, Vint (Ch.1) iin (Ch.2) and Io (Ch.4).
In Fig 5.3, step load is change from ∼ 100W to ∼ 250W , here the time taken to settle is
more. The reason behind that we are close to the rated power level of system, which deceases
the amount of surplus power to act on loading. Again, in Fig 5.3, step load is change from
∼ 100W to ∼ 150W , we got settling time close to the designed one.
Loading/unloading of pre-regulator is done using enabling/disabling the PWM of DSFC
as a change load along with constant load at Cint .
26 Chapter 5. Experimental Results

V int

i in

Io

Figure 5.3: Step Load Change from ∼ 250W to ∼ 100W in Pre Regulator

V int

Figure 5.4: Step Load Change from ∼ 100W to ∼ 250W in Pre Regulator
5.2. Isolated DC-DC Converter 27

V int

Io

Figure 5.5: Step Load Change from ∼ 100W to ∼ 150W in Pre Regulator

5.2 Isolated DC-DC Converter

The Fig. 5.6 is at Po ∼ 250W and Vint ∼ 350Vdc with Pint ∼ 280W , at these condition η ∼
88%, while Fig. 5.7 is at Po ∼ 55W and Vint ∼ 400Vdc with Pint ∼ 60W , at these condition
η ∼ 91%. We have, Vo ∼ 24.7V . For Fig 5.6 and Fig 5.7, Vint (Ch.1), Vo (Ch.3) and iLo (Ch.4).

Vint

Vo

i L_o

Figure 5.6: DSFC Waveform at Rated Power

28 Chapter 5. Experimental Results

Vint

Vo

i L_o

Figure 5.7: DSFC Waveform at Low Power

Fig 5.8, shows the loading of DSFC from ∼ 50W to ∼ 100W . It can be noted that due to
the inductance associated with incoming resistor load, output current rises slowly and due
to the large bandwidth of DSFC voltage loop, output voltage has very-very small transients.
For Fig 5.8 and Fig 5.9, Vo (Ch.3), and Io (Ch.4). For Fig 5.8 iin (Ch.2), while for Fig 5.9
iLo (Ch.2).
Fig 5.9, shows the loading of DSFC from ∼ 50W to ∼ 125W . In that, it can be observe
that the high bandwidth effect of voltage can be seen in the output inductor current as
current reference is generated through voltage loop and iLo responded to load change very
quickly.
Fig 5.10, shows the current limiting capability of DSFC during overload. It can be observe
in case of overload, DSFC has maximum current limit, which causes output voltage to drop.
5.2. Isolated DC-DC Converter 29

Vo

i in
Io

Figure 5.8: Step Load Change from ∼ 50W to ∼ 100W in DSFC

Vo

Io

I L_o

Figure 5.9: Step Load Change from ∼ 50W to ∼ 125W in DSFC

30 Chapter 5. Experimental Results

I L_o

Vo

Figure 5.10: Output Voltage and Inductor Current during Overload in DSFC

5.3 Experimental Result on Start up Circuit

Fig. 5.11 and Fig. 5.12 are taken at vin ∼ 90Vac with ∼ 50W output load. For Fig 5.11 and
Fig 5.12, iin (Ch.2), Vo (Ch.3), and Vcon (Ch.4).

i in

a V con b c

Vo

Figure 5.11: Waveform During Starting of Pre Regulator and DSFC (Part 1)
5.3. Experimental Result on Start up Circuit 31

Vo

Vcon

a b c d

Figure 5.12: Waveform During Starting of Pre Regulator and DSFC (Part 2)

In Fig. 5.11 and Fig. 5.12, at point

a , input voltage is applied, inrush current flows in
the circuit to charge the Vint upto peak value of vin . Inrush current limited by resistance.
Vcon starts building by charging through Rst lmt from Vint , which in starting is at vin (peak).
At point
b , Vcon reaches to ∼ 16V , at which pre regulator control IC starts and time taken
to charge from 0V to 16V is around 350ms, which is same as calculated one. These delay
will be maximum at low line input condition. At point
c , Vcon reaches to ∼ 16.5V , at
which isolated DC-DC converter control starts. After point
c , Vcon starts decreasing due to
supplying power to control IC’s.
It can be noted that output voltage charges upto ∼ 20V after starting of DSFC control.
The reason behind that the soft start feature involve in pre regulator control IC and Vint
reaches upto ∼ 300V and soft start nature of Vint can be seen in the output voltage between
point
c and point
d.
In Fig 5.12, after point
d under normal operating condition, Vcon is being supplied
through on board power supply.
Chapter 6

Conclusions

The project was aimed at developing the hardware and close loop control for control power
supply with wide input variation. The motivation for this was to have a reliable, compact,
efficient and economical hardware for the control power supply used in supplying power to
sub-systems of high power converters.

The hardware built for the project consists of:

• Circuit boards consisting of power circuits, and control circuits of pre-regulator and
isolated DC-DC converter

• The magnetic components - inductors and transformer

• Start up circuit and on-board power supply

The efficiency of pre-regulator and DSFC found close to the calculated one. The near
unity power factor operation of control power supply over the wide input variation has been
verified. The circuit protection of system has been tested. Bandwidth of pre-regulator and
DSFC found to be close to the designed one. An offline efficient start up circuit along with
on-board power supply built and tested

32
Appendix A

General Expression for Boost Diode

Current in Pre-Regulator

By neglecting losses, we can calculate diode Db DC and 100Hz current components as -

Pint iL (peak) ∗ M
id DC = = (A.1)
Vint 2
Pint
id 100Hz (rms) = √ (A.2)
Vint ∗ 2

|vin (peak)|
where, M = Vint
.
The change in inductor current over a Ts will be small as fsw >> fo . So, by applying
volt-sec balance over Ts across inductor with < δiL >Ts ∼ 0 as fo << fs , results in -

ds = 1 − M ∗ sin(2πfo ∗ kT s) (A.3)

where, ds is the duty cycle of switch Sb , fo is the fundamental line frequency of vin
1
and Ts = fsw
.
Current at switching frequency in diode Db can be calculated as -
  12
N
{i2L (kTs ) [dd (kTs ) − dd (kTs )2 ]} 
P

 k=0
id f sw (rms) =  (A.4)

N

 

fsw
where, dd = (1 − ds ) and N = 2∗fo
.

33
34 Appendix A. General Expression for Boost Diode Current in Pre-Regulator

To 1
As Ts << 2
, where To = fo
, equ. A.4 can be re-written as-
  21
Zπ
1
i2L dd − d2d dθ
 
id f sw (rms) = 
π
0
   12
4 3M
= iL (peak) M − (A.5)
3π 8
 B.1
Appendix B
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�
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�
�
� �������

35
���� ����

�
� ����
������
�

�����
���� �

�
����� � �������� ����� �������
Circuit Board Schematics

������ � ���������������

Figure B.1: Start up Power Circuit

�������
Start-up Power Circuit Schematics
 36

B.2
sb_pwm
Vint+ 1 J_1
PWM_SB- 1 2
2
PWM_SB+ V_IN
Dr5

V_RS1+ 1 Vs_pre
2
Rcurr_lmt2 V_RS1- Lb1 Lb2
1 2 Vint

1
2
1
2
1

1
2
1
2
NPT cm1 cmdm1 dm1 DB+
TP_L 1 2 V_IN Rs2
V_sb Cs2
1 1 2 Vint+

1
2
DB_L

1
2
Rcurr_lmt1

1
2
fuse 2 1 2 1
1 2 1
relay 1

1
2
Rb1

1
2

1
2
1
2
L 3 1
Cint1

5 int_out
Cint2

2 4 Db 1
2 Dr1 Dr3 2 1
1 3 Cy1 Vg_sb MUR860_0 1
1 2

1
2
Sb 2
1 3
Cp2 Rs1 3
N Ds1
Cp1 Roff Don
1 Cx

1
2
Cint3

2 V_relay 1
2 2 Cp3
1 Cy2 PWM_SB+ 1
Cint4

1 2
1
MOV Dr4 Dr2 Ron Cs1
Doff
z3
Rb2

TP_N PWM_SB- 2
1 Vint-

2
1
2
1
2
1
1
2

1 Rs1_p
DB_N 1

2
1
2
1
2
1
DB-
GND REF_CON
1 Rs2_p
Pre-Regulator Circuit Schematics

2 cm2 cmdm2 dm2

2
1
1
V_RS1- V_RS1+ Title : Pre-Regulator Power Circut

Figure B.2: Power Circuit of Pre-Regulator Circuit

1

TP_GND
Author : Akshay Kumrawat
Appendix B. Circuit Board Schematics
 J_1
sb_pwm TP13
Vint+ 1
PWM_SB- 1 2
1
2 V_IN
V_RS1+
PWM_SB+ 1 TP5 V_RS1-
V_RS1- TP11 1
1 2
V_RS1+
V_spre
PWM_SB- 1 vcc_3854
1 TP1
2
15V_pre
TP3
1 TP6
Rpk2 1
TP10

5
Rpk1 Vint+

15V_pre
B.2. Pre-Regulator Circuit Schematics

Rmo Rci
Ccp PWM_SB- Rvfv
PWM_SB+ C1
GND1
Rcz Ccz Dg1 Rvf1
+
1 2
C2 Cv1
DC Rvf3 TP2

Cpk uc3854 1
Ct_1 GND1 Rvf2
1 16
2 15
Rvf4 Cv2
3 14 Css1
R5 R6 R7 4 13
5 12 Rt_1
6 11
Rff1 7 10 en_pre Rvf TP12
8 9
V_IN R1 R3 TP4 TP7 Cvp C Cvz Rvf5
Cff2 Rff2 Cref1 1

Figure B.3: Control Circuit of Pre-Regulator Circuit

Cff1 1 1 GND1
R2 R4
TP15
TP14
1
1
PWM_SB-
1 stdn_3854
en_pre Title : Pre-Regulator Control Circuit
2
15V_pre
3
R10 2
37

R19 1
TP8 Rshdn Author : Akshay Kumrawat
Qstdn
1
TP9 1
 38
Vg_s1 1 pwm_s1

B.3
Ron1
1 Vint-

1
g_s1 1 Don1

7
Rfilt
2 Dm_r
Roff1 Q1 V_15V

7
z1 3 Rb_q1 1
1 Gnd_24V0 V_o
2 10 Cpwm_iso
s_s1 2
10 iso_pwm
9

2
9 1
Don2 Ron2 3 2
3 1
5

1
Vg_s2 1
5 3 Vo_
1 4 6 Q4 2

8
g_s2 Roff2 2 46 PWM_ISO+
S1_D z2 NPN1 Rb
3 Rb_q2 pulse_tr
Fuse2 +Vdc AP3-_

8
Q2 1
s_s2 PWM_ISO-

2
1 2 AP_3
1 AP3+_

1
2
1 Vint-
Vint+ 2 pwm_s2 AP2-_ 1
R_s1 S1 g_s1 V_sec 2 AP_2
AP2+_
HFTF

D_s1
1
1 1 26
Dc1 1 1 26
2 27 AP1-_ 1
2 27 AP_1
s_s1 3 28 2
3 28
C_s1 4 29
4 29
2 5 30 AP1+_
1 5 30 Lo1 Lo2
6 31 Rs3 Lo3 Lo4
1 S1_s 6 31
7 32

1
2
1
2
7 32 1 Vo_

1
2
1
2
Ci1 8 33 V_RS3-
8 33
2 1 S2_D 9 34 Cs3 1 Vs_iso

1
2
1
2
9 34 Dsec
10 35

1
2
1
2
10 35 1 V_RS3+ 2
11 36 2 1 Vo 1
11 36 2 op1+
2 12 37 2
12 37
Vint- 13 38 1
Dc2 S2 13 38
g_s2 14 39 PWM_ISO-
R_s2 ap1 14 39 Cs4 Ci3 Ci5 Co1 Ci10
15 40 Co3 Ci8

D_s2
ap1- 15 40 1 1 1
16 41 1 1 1 1 1 1 1
1 16 41 2 2 op2+ PWM_ISO+
2
1 ap2 17 42 V_rect 2
17 42 Rs4 3
18 43 Ci2
ap2- 18 43
C_s2 19 44 V_15V
s_s2 19 44 2 2 2 2 2 2 PWM_iso
ap3 20 45 1
Rs_i4 2 20 45 Ci9 1
Vint- ap3- Ci4 Ci6 Ci7 Co2 Co4 Ci11 2 op1-
2
-Vdc Rs_o5
Rs_i1
Isolated DC-DC Circuit Schematics

1
1 V_RS5-
1
S2_s 1 1 op2- 1 Vs_iLo
2
2 2

Figure B.4: Power Circuit of Isolated DC-DC Converter

Rs_o6 V_RS5+
V_RS3- V_RS3+ GND_24V
Gnd_24V0

AP1+ V_RS5- V_RS5+

AP1 AP2+ AP2 AP3+
1 AP3
AP1+_ Dap1 1 1 1
AP2+_ Dap2 AP3+_ 1 Dap3 1 Title : Isolated DC-DC Power Circuit
ap1 ap2 ap3
Cap4 Cap1 Cap5 Cap2 Cap6 Cap3
Appendix B. Circuit Board Schematics

ap1- ap2- ap3- Author : Akshay Kumrawat

AP2-_ AP3-_ AP3-
AP1-_
1
1 1
AP1- AP2-
 gnd_3901
gnd_3845 Vo_24v 1 V_o
V_RS3+ 2
V_3901 R18
ref_3845 R25 R23 Vo_24v
rt_2 3
Qramp TP-32 RLED1
ct_2 2 R24 1 TP_26
1 R20
1
R27

3
3 D1 C6 + C11
C10
2 PWM_iso+ J2 1 R28 LED1
1 C12
gnd_3845 R8 gnd_3901 R21
TP-31

1
Qblank R26
R9
Dg2 TP_16 1 Ct_3 V_3901 TP-34

2
uc3845
PWM_iso+ 1 TP_24 R16 st 1
TP_23 TP_17
5 4 1 14 Cp2 st

2
gnd_3845
B.3. Isolated DC-DC Circuit Schematics

15V_iso 6 3 Cp1 1 1 1 T1 2 13 vo_status

7 2 3 12
8 1 D2 gnd_3901
R14 4 11 Cz2 Rz2
R17 C13 1
C4 5 10 TP-33
st 2
6 9
2

Rz1

+
ref_3845 Cz1 R11 7 8 TP_36 1
Cref2 3 1 TP_28
C5
2 R15 C8 UC3901 J1 R22
1 TP_20 shtdwn_iso 1
1 Rsh_iso TP_19 1
gnd_3845

Qshdn1
gnd_3845 TP-35 Rt_3 Cref3
1 TP_25 1
1

C7
C9
gnd_3845 PWM_SB- gnd_3901
gnd_3845 PWM_iso
15V_iso 15V_pre gnd_3901
gnd_3845
1
gnd_3845 2 ref_3845 Title: Isolated DC-DC ControlCircut
1 vcc_3845
PWM_ISO+ R12
2 1 TP_22 gnd_3845 R13
15V_iso gnd_3845 1 1
1 TP_27

Figure B.5: Control Circuit of Isolated DC-DC Converter

1 Vs_iso 2 shdn_iso
shtdwn_iso TP_18 Author : AkshayKumrawat
1 V_RS3+ 2
TP_21
39
Appendix C

Bill of Materials

Control Circuit Bill Of Materials

Item Quantity Reference Part
1 1 Ccp 22p
2 1 Ccz 330p
3 5 Css1,Cref1,Cff1,Cref2,Cref3 0.1u
4 1 Cff2 0.47u
5 1 Cpk 27p
6 1 Cp1 47p
7 1 Cp2 390p
8 2 Ct 1,ct 2 1n
9 1 Ct 3 680p
10 1 Cvp 22n
11 5 C4,C9,C10,DC,Cvz 0.22u
12 1 Cz1 inf
13 1 Cz2 0.33u
14 2 C5,C1 47u
15 1 C6 270p
16 1 C7 120p
17 1 C8 4.7n

40
 41

Control Circuit Bill Of Materials

Item Quantity Reference Part
18 1 C11 10u
19 2 Dg1,Dg2 1n5819
20 2 D2,D1 1n4148
21 1 J1 RM-4Pin
22 2 J1,Rpk2 5.6k
23 11 J2,vcc 3845,vcc 3854,stdn 3854, RM-2Pin
vo status,shdn iso,sb pwm,
Vs iso,V spre,V o,PWM iso
24 1 LED1 LED
25 4 Qshdn1,Qstdn,Qramp,Qblank 2n2222
26 10 RLED1,rt 2,Rvf5,R15,R16,R17,R19, 6.8k
R22,Rmo,Rci
27 2 R21,Rcz 47k
28 1 Rff1 100k
29 2 R24,Rff2 22k
30 1 Rpk1 33k
31 2 Rsh iso,R25 220k
32 5 Rvf1,Rvf2,R5,R6,Rshdn 470k
33 1 Rt 1 12k
34 1 Rt 3 4.7k
35 1 Rvf 270k
36 1 Rvfv 180k
37 2 Rvf4,Rvf3 820k
38 1 Rz1 68k
39 1 Rz2 39k
40 4 R1,R2,R3,R4 1M
42 Appendix C. Bill of Materials

Control Circuit Bill Of Materials

Item Quantity Reference Part
41 1 R7 620k
42 4 R8,R9,R11,R23 1k
43 1 R10 18k
44 1 R12 0
45 1 R14 10k
46 1 R18 47
47 1 R20 56k
48 1 R26 2.2k
49 1 R27 2.7k
50 34 TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8, TP
TP9,TP10,TP11,TP12,TP13,TP14,
TP15,TP 16,TP 17,TP 18,TP 19,
TP 20,TP 21,TP 22,TP 23,TP 24,
TP 25,TP 26,TP 27,TP 28,TP-31,
TP-32,TP-33,TP-34,TP-35,TP 36
51 1 T1 Toroid
52 1 UC3901 14Pin Base
53 1 U1 08Pin Base
54 1 uc3854 16Pin Base
 43

Pre-Regulator
Power Circuit Bill Of Materials
Item Quantity Reference Part
1 2 Cint2,Cint1 470uF250V
2 3 Cp1,Cp2,Cp3 0.1uF630V
3 11 Vint,Vg sb,V sb,TP N,TP L, TP
TP GND,REF CON,DB N,DB L,
DB-,DB+
4 1 Db MUR860
5 2 Doff,Don IN5819
6 5 Dr1,Dr2,Dr3,Dr4,Dr5 SK3GL10
7 1 Ds1 MUR160 0
8 2 Fuse1 Fuse
9 6 Lb1,cm2,Lb2,N,L,GND CONN 2
10 1 J1 RM4
11 1 MOV MOV
12 1 NPT NPT
13 2 Rb1,Rb2 100k
14 3 Rcurr lmt1,Rcurr lmt2,Roff 10
15 1 Ron 15
16 2 Rs1 p,Rs2 p 0.39
17 1 Sb IRF840
18 2 V relay,Vs pre,sb pwm RM2
19 5 dm1,cmdm1,cm1,dm2,cmdm2 CONN 2
20 1 int out PM3
21 1 relay Relay
22 1 z3 18VZener
44 Appendix C. Bill of Materials

DSFC
Power Circuit Bill Of Materials
Item Quantity Reference Part
1 18 pwm s1,Vg s1,S1 s,S1 D,pwm s2,Vg s2, TP
S2 s,S2 D,AP2-,AP2+,AP2,GND 24V
iso pwm,Vo,V sec,V rect,-Vdc,+Vdc
2 6 AP 1,AP 2,AP 3,Vs iso,Vs iLo,V o RM2
3 2 C s1,C s2 100p
4 2 Cap2,Cpwm iso 0.47u
5 1 Cap4 22u
6 1 Ci1 0.1uF630V
7 6 Ci2,Ci3,Ci4,Ci5,Ci10,Ci11 1u
8 4 Co1,Co2,Co3,Co4 330u
9 2 z2,z1 18VZener
10 2 Cs4,Cs3 470p
11 3 D s1,Dap2,D s2 MUR160
12 2 Dc1,Dc2 MUR460
13 3 Don1,Don2,Dm r IN5819
14 1 Dsec MBR20020CT
15 1 Fuse2 Fuse
16 1 HFTF HFTF
17 8 op1-,op1+,Lo1,op2-,op2+,Lo2,Lo3,Lo4 CONN 2
18 1 PWM iso RM3
19 2 Q2,Q1 2n2906
20 1 Q4 2n2222
21 2 R s1,R s2 400
22 3 Rb q1,Rb q2,Rb 1k
23 3 Rs o5,Rs o6,Rfilt 0
24 2 Roff1,Roff2 2.7k
25 2 Ron1,Ron2 12
26 1 Rs i1 0.5
27 1 Rs i4 3.3
28 2 Rs4,Rs3 100
29 2 S2,S1 IRF840
30 1 pulse tr PulseTr
Appendix D

Testing and Assembling Procedure

• Assemble all components

• Built magnetic components, i.e. inductor and transformers

• Solder gate dive circuit of DSFC and test the pulses on secondary

• Solder DSFC remaining power circuit

• Solder DSFC control part

• At low voltage, short load and check the current limiting capability

• Put load, go for higher voltages

• Close the voltage loop of DSFC

• Check the close loop operation of DSFC

• Solder pre-regulator power circuit

• Check diode bridge operation

• Put low load (< 100Ω) at pre-regulator and check the current loop of pre-regulator by
slowly increasing the input voltage
Keep check of Vint < 400V

• Close the voltage loop of pre-regulator

• Check the close loop operation of pre-regulator

45
Appendix E

Protection Inhibits by CPS

• Metal oxide varistor (MOV) is placed at input terminal, which protect system from
input over-voltage by clipping voltage at ∼ 275V ac

• Relay based inrush current limiting is provided

• Peak current limiting protection of pre-regulator switch implemented in control IC

• Peak current limiting protection of isolated converter implemented in control IC

• In case of not providing the output voltage feedback, due to buck configuration used
in DSFC output voltage, under CCM operation of converter, output voltage is ∼ 33V
at 400V Vint and d = 0.5

46
Appendix F

Pictures of Hardware Set-up

F.1 Pre-Regulator Power Circuit - Version 1.0

Figure F.1: Pre-Regulator Hardware Picture

47
48 Appendix F. Pictures of Hardware Set-up

F.2 DSFC Power Circuit - Version 1.0

Figure F.2: DSFC Hardware Picture

F.3. Control Circuit - Version 1.0 49

F.3 Control Circuit - Version 1.0

Figure F.3: Control Hardware Picture

50 Appendix F. Pictures of Hardware Set-up

F.4 Complete Hardware Set up

Figure F.4: Complete Hardware Set up Picture

References

[1] V. Ramanarayanan, “Course Material on Switched Mode Power Conversion”, Depart-

ment of Electrical Engineering, Indian Institute of Science, Bangalore

[2] Daiva Prakash, “Design of 1400W Telecom Power Supply with Wide Range Input AC
Voltage”, MSc Thesis, Department of Electrical Engineering, Indian Institute of Science,
Bangalore, 2007.

[3] Data sheet and application notes of UC3854.

[4] G. Narayanan, “Class notes of Power Electronics”, Department of Electrical Engineering,

Indian Institute of Science, Bangalore, 2010.

[5] Vinod John, “Class notes of Topics in Power Electronics and Distributed Generation”,
Department of Electrical Engineering, Indian Institute of Science, Bangalore, 2011.

[6] Website “http://www.epcos.com”.

[7] Jasvinder Singh Khoral, “Power Factor correction of Switching Power Supplies with
UC3854”, ME report, Department of Electrical Engineering, Indian Institute of Science,
June 1994.

[8] R. W. Erickson, Dragan Maksimovic, “Chapter 12 Current Programmed Control” of

“Fundamentals of Power Electronics”, Second Edition, Springer International Edition,
2010.

[9] Mohan, Undeland, Riobbins, “Chapter 30 Design of Magnetic Components” of “Power

Electronics Converters, Application and Design”, Third Edition, Wiley Student Edition,
2009.

51
52 References

[10] Data sheet and application notes of UC3844.

[11] Data sheet and application notes of UC3901.

[12] Anand Vivek Ravi, “Control Power Supply Architecture For Ride Through in Power
Converters using Ultra-capacitors”, ME report, Department of Electrical Engineering,
Indian Institute of Science, Bangalore, 2010.

[13] Emilio Figueres, Jose-Manuel Benavent, Gabriel Garcerá, Marcos Pascual “Robust Con-
trol of Power-factor Correction Rectifiers With Fast Dynamic Responce” IEEE Transac-
tions on Industrial Electronics, vol. 52, No.1, February 2005.