library IEEE;

use ieee.std_logic_1164.all;

entity two_to_four_decoder is
port (in_vec: in std_logic_vector(1 downto 0);
out_vec: out std_logic_vector(3 downto 0));
end two_to_four_decoder;
architecture two_to_four_decoder_arch of two_to_four_decoder is
begin
process(in_vec)
begin
out_vec(0) <= (not(in_vec(0))) and (not(in_vec(1)));
out_vec(1) <= (not(in_vec(0))) and in_vec(1);
out_vec(2) <= in_vec(0) and (not(in_vec(1)));
out_vec(3) <= in_vec(0) and in_vec(1);
end process;
end two_to_four_decoder_arch;