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Approach:
◦ Analyze 4 resistor bias networks to set DC operating points for each stage of the amplifier.
◦ Select starting point by setting a key parameter to a desired value, and solving for unknowns using that parameter.
◦ Maximize gain for each stage while minimizing power dissipation.
◦ Simulate each stage and verify that the results match the by-hand calculations (shown on next slide).
◦ Decouple and bypass the DC bias from the AC input signal, and unify all 3 stages. Verify the final result to the project specifications.
Figure 1. Mathcad calculations for biasing each stage of the overall TIA amplifier.
Finalized 3-Stage Amplifier Circuit
The completed 3-stage amplifier design is
shown on the right:
◦ The input current source is located between
Stage 1 and Stage 2.
◦ The output load is located to the right of
Stage 3.
While the total gain does not meet the specified 1 MΩ, it
comes substantially close. These limitations on gain most
likely arise from impedance mismatching, clipping, and
limitations on power consumption.
When the bypass capacitors are removed, the overall Figure 3. AC analysis showing the gain provided by each stage, as
midband gain for the TIA is: well as the total amplifier gain. Stage 1 gain is shown in blue. Stage 2
◦ No Bypass Capacitor Gain: 84.54 dB = 16.87 kΩ gain is shown in purple. Stage 3 gain is shown green. The total
transimpedance gain is shown in red.
Input and Load Impedance
The input impedance for stage 1 of this amplifier is The load impedance for the output of this amplifier is
calculated using: calculated using:
𝟏 𝑹𝑳𝑶𝑨𝑫 = 𝑹𝑳 ||𝑹𝑺 ||𝒓𝒐
𝑹𝒊𝒏 = 𝑹𝑺 ||
𝒈𝒎
The input impedance to the common gate stage is simply Taking RL = 50 Ω the load impedance seen at the output is
the parallel combination of the source biasing resistor with the parallel combination of the connected load, the source
the small signal input impedance of the transistor. biasing resistor, and the small signal output impedance of
the transistor.
By biasing the first stage the way it is, a large (relative) value
for gm was achieved, thus allowing it to be the defining By biasing the third stage the way it is, a very large (relative)
factor for the input impedance. value for gm was achieved, thus allowing it to be the
defining factor for the load impedance.
The input impedance of the TIA meets the specified criteria
for design of ≤ 100 Ω. The load impedance of the TIA permits a large current gain
in order to drive the specified 50 Ω load.
Bandwidth Analysis
The specification for this design regarding bandwidth was
that the TIA must act as a low-pass filter for frequencies less
than 10 MHz.
In order to decrease the rise/fall time, the decoupling capacitor at the output must be decreased, to decrease the time constant. However, the tradeoff with this
lies with the causation of a smaller bandwidth.
Figure 7. Transient analysis showing the output Figure 8. Transient analysis showing the output
response to a step wave and its rise time. response to a step wave and its fall time.
Distortion
One of the specifications for this design is to have as low of
total harmonic distortion as possible.