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International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) – TCET, Mumbai, India

Design of 32 bit (MIPS) RISC PROCESSOR Using FPGA

D B Bhoyar

Department of Electronic Engg Yeshwantrao Chavan College Of

Engg. Nagpur, India

+91-9923448822

dinesh_bhoyar@rediffmail.com

R M Kubde

Department of Electronic Engg Yeshwantrao Chavan College Of

Engg. Nagpur, India

+91-9823935309

rupa_kubde@yahoo.co.in

R S KHEDIKAR

Department of Electronic Engg Yeshwantrao Chavan College Of

Engg. Nagpur, India

+91-9767031658

rakhikhedikar@yahoo.co.in

ABSTRACT

The proposed work is aimed at designing general purpose 32 bit RISC(MIPS) processor. The system is design using VHDL language and this source code can be use as IP (Intellectual

Property) core which can be targeted to any FPGA for several applications. Emphasis is given on simple working solution with minimum possible area. RISC processor has to be implemented

on FPGA (Field Programmable Gate Array)

instructions. Simulation of entire processor is done to verify the functionality. The source code can also be verified for synthesis purpose. Objective of this project is designing 32-bit RISC(MIPS) processor. The RISC design ideally suited to participate in a powerful trend in the embedded processor market – the "system-on-a-chip”. This paper describes current work utilizing rapid prototyping approach to simulate, synthesize, and implement prototype digital system and computer architectures using PCs with student versions of commercial VHDL based CAD tools and a low cost board with

a large CPLD or FPGA. VGA video output generated directly

by the CPLD chip is used to display graphics or textual data

eliminating the need for a logic analyzer.

It uses different

Categories and Subject Descriptors

B [Hardware]:B.5.1 Design, B.5.2 Design aids

General Terms

Design, simulation

Keywords

System-on –a – chip, CPLD chip, prototype digital system, VGA video output

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ICWET’10, February 26–27, 2010, Mumbai, Maharashtra, India.

Copyright 2010 ACM 978-1-60558-812-4…$10.00.

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INTRODUCTION

Microprocessors and Microcontrollers have traditionally been designed around two philosophies: Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC). The CISC concept is an approach to the instruction set architecture (ISA) design that emphasizes doing more with each instruction using a wide variety of addressing modes, variable number of operands in various locations in its instruction set. As a result Instruction is of widely varying lengths and execution time is more. Thus demanding a very complex control unit, which occupies a large real state on chip. On the other hand, RISC processor works on reduced number of instructions, fixed instruction length, more general purpose registers, load – store architecture and simplified addressing modes which makes individual instruction execute faster, achieve a net gain in performance and an overall simpler design with less silicon consumption as compared to CISC. This gives the RISC architecture more room to add on-chip peripheral, interrupt controller and programmable timer. The above feature makes RISC design ideally suited to participate in powerful trend in the embedded processor market – “system-on –a – chip”.

Computer organization and design is a common engineering course where students learn concepts of modern computer architecture. Students often learn computer design by implementing individual sections of a computer microprocessor using a simulation-only approach that limits a students experience to software design. This project targets the computer architecture courses and presents an FPGA (Field Programmable Gate Array) implementation of a MIPS RISC (Reduced Instruction Set Computer) Processor via VHDL (Very high speed integrated circuit Hardware Description Language) design. The goal of this project is to enhance the simulator based approach by integrating some hardware design to help the computer architecture students gain a hands-on experience in hardware-software integration and achieve a better understanding of both the MIPS single-cycle and pipelined processors.

Instruction Formats

Looking at the MIPS processor core instruction table you can see that we have assigned different formats for certain instructions. This is because different instructions use different operands and hence different formats needed to be constructed for them. The following section describes three formats that are

International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) – TCET, Mumbai, India

used.

Field

6

5

5

5

5

6

size

bits

bits

bits

bits

bits

bits

Register Format (R-type) The most common style of instruction is the R-type. The R- type instruction has two read registers and one write register.

(31 to 26) (25 to 21) (20 to16) (15 to11) (10 to 6)

(5 to 0)

R-

           

Forma

Opc

ode

Rs

Rt

Rd

shift

Function

t

All of the instructions have a 6-bit opcode, which is used to determine what type of instruction is to be executed. Each of the register specifications in all of the instructions is 5-bits wide. The first two 5-bit register specifications are the two read registers and the last 5-bit register specification is the destination register, that the instruction will use. The last 6-bits in the instruction are used as function bits. This function bits specify what the actual instruction that will be performed.

Immediate Format (I-type) (31 to 26)(25 to 21) (20 to 16)

(15 to 0)

I-

Format

s

R

t

R

Address/Immediate

value

Opcode

The I-type is similar to the R-type except the second read register and the 5 function bits are replaced by a 16-bit immediate value. Each I-type opcode can have only one instruction because it has no function bits like the R-type. Branch Type Format (J- type)

(31 to 26)

(25 to 0)

J-

Format

Opcode

Branch target address

The J-type format consists of a 6-bit opcode and remaining bit indicates branching address.

Working of Block Diagram

RISC processor consists of Instruction fetch unit, decoder unit, control unit, execution unit, and data memory unit. As shown below in figure 8 of block diagram the fetching unit comprises of Program counter, two adders and instruction memory. PC is 8-bit register, which contains the address of memory location of instruction memory where opcode is present. Instruction opcode is of 32 bit hence to fetch next instruction in normal operation PC will be incremented by 4 in adder 1. When branching instructions are used the corresponding branching address is generated in adder 2 using sign extended and shift left 2 blocks. The mux decides whether the address transferred to PC is a branching address or address of next instruction. A 32-bit instruction from instruction memory is splited into two groups .Instruction opcode and data, instruction opcode (31- 26) is fed to control unit, which generates different control signals as defined by the opcode. The remaining data is given to decoder on which the operation is performed. Last 6 bits of instruction code is function opcode (5- 0), which along with the two bit ALUOp (1-0) signal is fed to ALU control block. The ALU control block generates the control signals, which defines the operation performed by ALU

937

such as ADD, SUB, AND etc.

Mnemonic

Format

Opcode

Function

Instruction

field

field

ADD

R

0

32

Add

ADDI

I

8

--

Add

immediate

ADDU

R

0

33

Add

unsigned

SUB

R

0

34

Subtract

SUBU

R

0

35

Subtract

unsigned

AND

R

0

36

Bitwise

AND

OR

R

0

37

Shift

left

logical

SEL

R

0

0

Bitwise

OR

SRL

R

0

2

Shift

right

logical

SLT

R

0

42

Set if less than

LUI

I

15

--

Load

upper

immediate

LW

I

35

--

Load word

SW

I

43

--

Store

word

BEQ

I

4

--

Branch

on

equal

BNE

I

5

--

Branch on not equal

J

J

2

--

Jump

JAL

J

3

--

Jump &link

(used to

call )

       

Jump

JR

R

0

8

register

(used

to return)

The execution unit generates the ALU result which is then applied to data memory which selects the memory location in which the result is to be stored when memory write signal is high or memory location from which data is being loaded into register when memory to register and memory read signals are high.

Table 1.MIPS PROCESSOR CORE INSTRUCTIONS:

VGA Video from a CPLD or FPGA:-

In the past, the limited I/O features and debugging information available on CPLD and FPGA demo boards has been a problem on complex designs. To support this new laboratory development work, a VHDL based VGA video output feature was developed using hardware inside the CPLD or FPGA. Only five signals or pins are required, two Sync signals and three RGB color signals. A simple resistor and diode circuit is used to convert TTL to the analog RGB signals. This circuit and a VGA connector is already installed on the Altera UP1 board.

Figure 1.VGA Video from a CPLD or FPGA

RESULTS:

Simulation Results:-

International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) – TCET, Mumbai, India

Trends in Technology (ICWET 2010) – TCET, Mumbai, India 5. Simulation result of Data Memory stage
Trends in Technology (ICWET 2010) – TCET, Mumbai, India 5. Simulation result of Data Memory stage

5. Simulation result of Data Memory stage

Mumbai, India 5. Simulation result of Data Memory stage Figure Figure 6.Simulation of CPU/Output waveform Figure

Figure

India 5. Simulation result of Data Memory stage Figure Figure 6.Simulation of CPU/Output waveform Figure 7.

Figure 6.Simulation of CPU/Output waveform

stage Figure Figure 6.Simulation of CPU/Output waveform Figure 7. MIPS with Video Output generated by UP1Board

Figure 7. MIPS with Video Output generated by UP1Board

CONCLUSION

Result of the design tends to the following conclusion Design described in HDL can be easily targeted to different Technology and also can be easily reconfigure for different application requirement. Also with the help

Figure 2. Simulation Result of Fetch unit

Also with the help Figure 2. Simulation Result of Fetch unit Figure 3. Simulation Result of

Figure 3. Simulation Result of Decode unit

Simulation Result of Fetch unit Figure 3. Simulation Result of Decode unit Figure 4. Simulation Result

Figure 4. Simulation Result of Execute unit

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International Conference and Workshop on Emerging Trends in Technology (ICWET 2010) – TCET, Mumbai, India

of new design methodology and EDA tools the design time can be considerably reduced. Over all performance of the system can be improved with the help of best of the best algorithm available with these EDA tools.

0 P C + 4 Add MUX Add 1 Add Register 4 Destination Result Shift
0
P C + 4
Add
MUX
Add
1
Add
Register
4
Destination
Result
Shift
left 2
Branch
Memory Read
Instruction
ALU Opcode
(31-26)
Control
Memory write
Unit
Memory to Register
Register Write
ALUScr
Register
write
Clock
Reset
Instruction
(25-21) Rs
Read
Instruction
Read
register 1
Instruction
(20-16) Rt
data 1
Zero
Read
memory
ALU
Memory
register 2
Memory to
write
ALU
Register
Instruction
Address
0
Read
Read
Write
Read
Result
(31-0)
Instruction
1
P C
MUX
data
address
1
register
data 2
(15-11) Rd
Data
MUX
MUX
Memory
Write
0
data
Write
Memory
data
Read
Instruction
(15-0)
16
Sign
8
extend
ALU
ALU
Opcode
Control
Function Opcode (5-0)
(1-0)
Clock
Reset
Control bus
Data bus
Address bus

Figure 8. Block Diagram

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REFERENCES

[1]

“Rapid Prototyping of digital Systems, a tutorial approach” By – James O. Hamblen and Micheal D.

Furman.

[2]

“VHDL programming”, by Dougles Perry, Tata

 

[3]

Mcgraw- Hill Publication www.Altera.com

[4]

www.cs.wisc.edu

[5]

www.retromicro.com

[6]

www.users.ece.gatech.edu

[7]

A VHDL synthesis Primer, second edition by J

[8]

Bhasker. Fundamentals of Digital logic with VHDL Design by Stephen Brown and Zvonko Vranesic.

[9]

MIPS32

4K

Processor

Core

Software

User’s

Manual