Вы находитесь на странице: 1из 42

Chapter 8 – Introduction (8/7/06) Page 8.0-1.

CHAPTER 8 – COMPARATORS
INTRODUCTION
Chapter Outline
8.1 Characterization of Comparators
8.2 Two-Stage, Open-Loop Comparators
8.3 Other Open-Loop Comparators
8.4 Improving the Performance of Open-Loop Comparators
8.5 Discrete-Time Comparators
8.6 High-Speed Comparators
8.7 Summary

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 1 (8/7/06) Page 8.1-1.

SECTION 8.1 – CHARACTERIZATION OF COMPARATORS


What is a Comparator?
The comparator is a circuit that compares one analog signal with another analog signal or
a reference voltage and outputs a binary signal based on the comparison.
The comparator is basically a 1-bit analog-to-digital converter:

Reference Analog Comparator


1-Bit ADC
Voltage Input 1
1-Bit 1-Bit
Quantizer Encoder
Analog 1-Bit 1-Bit 1-Bit
Analog
Input Quantizer Encoder Digital
Input 2
Output
060808-01

Comparator symbol:
vP +
vO
vN -
Fig. 8.1-1

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 1 (8/7/06) Page 8.1-2.

Noninverting and Inverting Comparators


The comparator output is binary with the two-level outputs defined as,
VOH = the high output of the comparator
VOL = the low level output of the comparator
Voltage transfer function of a Noninverting and Inverting Comparator:
vo vo
VOH VOH

vP-vN vP-vN

VOL VOL
Noninverting Comparator Inverting Comparator
Fig. 8.1-2A

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 1 (8/7/06) Page 8.1-3.

STATIC CHARACTERIZATION
Static Characteristics
• Gain
• Output high and low states
• Input resolution
• Offset
• Noise

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 1 (8/7/06) Page 8.1-4.

Infinite Gain Comparator


Voltage transfer function curve:
vo
VOH

vP-vN

VOL Fig. 8.1-2

Model:
vP
+ +
vP-vN f0(vP-vN) vO
- -
vN
Comparator
VOH for (vP-vN) > 0
f0(vP-vN) =
VOL for (vP-vN) < 0 Fig. 8.1-3

VOH-VOL
Gain = Av = lim V where V is the input voltage change
V0

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 1 (8/7/06) Page 8.1-5.

Finite Gain Comparator


Voltage transfer curve:
vo
VOH
VIL
vP-vN
VIH
VOL
Fig. 8.1-4

where for a noninverting comparator,


VIH = smallest input voltage at which the output voltage is VOH
VIL = largest input voltage at which the output voltage is VOL
Model:
vP
+ +
f1(vP-vN) vO
VOH  VOL
vP-vN The voltage gain is Av = VIH  VIL
- -
vN
Comparator
VOH for (vP-vN) > VIH
f1(vP-vN) = Av(vP-vN) for VIL< (vP-vN)<VIH
VOL for (vP-vN) < VIL Fig. 8.1-5

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 1 (8/7/06) Page 8.1-6.

Input Offset Voltage of a Comparator


Voltage transfer curve:
vo
VOS VOH
VIL
vP-vN
VIH
VOL Fig. 8.1-6

VOH+VOL
VOS = the input voltage necessary to make the output equal 2 when vP = vN.
Model:
vP
+vP' +
±VOSv '-v ' f1(vP'-vN') vO
P N
-v ' -
vN N
Comparator Fig. 8.1-7
Other aspects of the model:
ICMR = input common mode voltage range (all transistors remain in saturation)
Rin = input differential resistance
Ricm = common mode input resistance

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 1 (8/7/06) Page 8.1-7.

;;
Comparator Noise
Noise of a comparator is modeled as if the comparator were biased in the transition
region.
vo
VOH
Rms Noise
vP-vN

VOL
Transition Uncertainty Fig. 8.1-8

Noise leads to an uncertainty in the transition region causing jitter or phase noise.

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 1 (8/7/06) Page 8.1-8.

Input Common Mode Range


Because the input is analog and normally differential, the input common mode range of
the comparator is also important.
Input common mode range (ICMR):
ICMR = the voltage range over which the input common-mode signal can vary
without influence the differential performance
As we have seen before, the ICMR is defined by the common-mode voltage range over
which all MOSFETs remain in the saturation region.

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 1 (8/7/06) Page 8.1-9.

DYNAMIC CHARACTERIZATION
Propagation Delay Time
Rising propagation delay time:
vo
VOH
V +V
vo = OH OL
t 2
VOL
vi = vP-vN
VIH
V +V
tp vi = IH IL
2
t
VIL
Fig. 8.1-9

Propagation delay time =


Rising propagation delay time + Falling propagation delay time
2

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 1 (8/7/06) Page 8.1-10.

Linear Frequency Response – Dominant Single-Pole


Model:
Av(0) Av(0)
Av(s) = s = sc+1
c + 1
where
Av(0) = dc voltage gain of the comparator
1
c = c = -3dB frequency of the comparator or the magnitude of the pole
Step Response:
vo(t) = Av(0) [1 - e-t/c]Vin
where
Vin = the magnitude of the step input.
Maximum slope of the step response:
dvo(t) Av(0)
-t/
dt = c e cVin
The maximum slope occurs at t = 0 giving,
dvo(t) | Av(0)
dt t=0 = c Vin
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 1 (8/7/06) Page 8.1-11.

Dynamic Characteristics - Propagation Time Delay


The rising propagation time delay for a single-pole comparator is:
VOH-VOL  1 
2 = Av(0) [1 - e-tp/c]Vin  tp = c ln  V -V
OH OL


1 - 2Av(0)Vin 
Define the minimum input voltage to the comparator as,
VOH -VOL  1 
Vin(min) = Av(0)  tp = c ln  Vin(min)
 
1- 2Vin 
Define k as the ratio, Vin, to the minimum input voltage, Vin(min),
Vin 
 2k 

k = Vin(min)  tp = c ln 2k-1


Thus, if k = 1, tp = 0.693c.
Illustration: vout
Vin > Vin(min)
VOH
Obviously, the more overdrive vin + vout VOH+VOL
applied to the input, the smaller - Vin = Vin(min)
2
VOL
the propagation delay time. 0 t t (max) t
0 p p Fig. 8.1-10
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 1 (8/7/06) Page 8.1-12.

Dynamic Characteristics - Slew Rate of a Comparator


If the rate of rise or fall of a comparator becomes large, the dynamics may be limited by
the slew rate.
Slew rate comes from the relationship,
dv
i = C dt
where i is the current through a capacitor and v is the voltage across it.
If the current becomes limited, then the voltage rate becomes limited.
Therefore for a comparator that is slew rate limited we have,
V VOH- VOL
tp = T = SR = 2·SR
where
SR = slew rate of the comparator.
If SR < |maximum slope|, then the comparator is slewing.

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 1 (8/7/06) Page 8.1-13.

Example 8.1-1 - Propagation Delay Time of a Comparator


Find the propagation delay time of an open loop comparator that has a dominant pole
at 103 radians/sec, a dc gain of 104, a slew rate of 1V/μs, and a binary output voltage
swing of 1V. Assume the applied input voltage is 10mV.
Solution
The input resolution for this comparator is 1V/104 or 0.1mV. Therefore, the 10mV
input is 100 times larger than vin(min) giving a k of 100. Therefore, we get

1  2·100  200
 
tp = 103 ln2·100-1 = 10-3 ln199 = 5.01μs

For slew rate considerations, we get


104
Maximum slope = 10-3 ·10mV = 105 V/sec. = 0.1V/μs.

Therefore, the propagation delay time for this case is limited by the linear response and is
5.01μs.

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 2 (8/7/06) Page 8.2-1.

SECTION 8.2 –OPEN-LOOP COMPARATORS


SINGLE-POLE COMPARATORS
Dominant Pole Comparators
Any of the self-compensated op amps provide a straight-forward implementation of an
open loop comparator without any modification.
The previous section give the relationships for:
1.) The static characteristics
• Gain
• Input offset
• Noise
2.) The dynamic characteristics
• Linear frequency response
• Slew rate response

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-2.

Single-Stage Dominant Pole Comparator


VDD
M3 M4

VPBias2
MC3 MC4 vo

CL
MC1 MC2
vp M1 M2 v
VBias n

-
+ M5
VNBias1
-
060808-02

• Gain  gm2rds2
• Slew rate = I5/CL
• Dominant pole = -1/(RoutCL) = -1/(gmrds2CL)
• VBias is replaced as shown in Chapter 6
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 2 (8/7/06) Page 8.2-3.

Folded-Cascode Comparator
VDD
VPB1

M4 M5

VPB2

vOUT
vP M6 M7
M1 M2 VNB2
M8 M9 CL
vN
M3
VNB1 I3 M11
M10

060808-03

• Gain  gm2rds2
• Slew rate = I3/CL
• Dominant pole = -1/(RoutCL)  -1/(gmrds2CL)
• Slightly improved ICMR

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-4.

Enhanced-Gain, Folded-Cascode Comparator


VDD

M10 M11
VPB1 M3
vP -A

M8 M9
vOUT
vN M1 M2
M6 M7 CL
-A -A

VNB1 M4
M5

060808-04

• Gain  gm1Rout
• Rout  [Ards7gm7(rds1||rds5)]|| (Ards9gm9rds11)
• Slew rate = I3/CL
• Dominant pole = -1/(RoutCL)
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 2 (8/7/06) Page 8.2-5.

TWO-POLE COMPARATORS
Two-Stage Comparator
The two-stage op amp without compensation is an excellent implementation of a
high-gain, open-loop comparator.
VDD

M3 M4
M6
vn vout
M1 M2
vp CL
+ M7
VNB1 M5
-
060808-05

• Much faster linear response – the two poles of the comparator are typically much larger
than the dominant pole of the self-compensated type of comparator.
• Be careful not to close the loop because the amplifier is uncompensated.
I7 I6-I7
• Slew rate: SR- = CII and SR+ = CII
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-6.

Performance of the Two-Stage, Open-Loop Comparator


We know the performance should be similar to the uncompensated two-stage op amp.
Emphasis on comparator performance:
• Maximum output voltage
 8I7 

VOH = VDD - (VDD-VG6(min)-|VTP|)1 - 1 -  (V -V (min)-|V |)2 


6 DD G6 TP
• Minimum output voltage
VOL = VSS
• Small-signal voltage gain

gm1   gm6 
Av(0) = gds2+gds4  gds6+gds7 

• Poles
Input: Output:
-(gds2+gds4) -(gds6+gds7)
p1 = CI p2 = CII
• Frequency response
Av(0)
Av(s) =  s  s




p1 - 1
p2 - 1


CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 2 (8/7/06) Page 8.2-7.

Example 8.2-1 - Performance of a Two-Stage Comparator


Evaluate VOH, VOL, Av(0), Vin(min), p1, p2, for the two-stage comparator in Fig. 8.2-1.
Assume that this comparator is the circuit of Ex. 6.3-1 with no compensation capacitor,
Cc, and the minimum value of VG6 = 0V. Also, assume that CI = 0.2pF and CII = 5pF.
Solution
Using the above relations, we find that
8·234x10-6  
VOH = 2.5 - (2.5-0-0.7) 1 -1 - 50x10-6·38(2.5-0-0.7)2  = 2.2V
The value of VOL is -2.5V. The gain was evaluated in Ex. 6.3-1 as Av(0) = 7696.
Therefore, the input resolution is
VOH-VOL 4.7V
Vin(min) = Av(0) = 7696 = 0.611mV
Next, we find the poles of the comparator, p1 and p2. From Ex. 6.3-1 we find that
gds2 + gds4 15x10-6(0.04+0.05)
p1 = - CI = - 0.2x10-12 = -6.75x106 (1.074MHz)
and
gds6 + gds7 95x10-6(0.04+0.05)
p2 = - CII = - = -1.71x106 (0.272MHz)
5x10-12
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-8.

Linear Step Response of the Two-Stage Comparator


The step response of a circuit with two real poles (p1  p2) is,

 p2etp1 p1etp2
vout(t) = Av(0)Vin1 + p1-p2 - p1-p2 
Normalizing gives,
vout(t) m 1 p2
vout’(tn ) = Av(0)Vin = 1 - m-1e-tn + m-1e-mtn where m = p1  1 and tn = -tp1
If p1 = p2 (m =1), then vout’(tn) = 1 - etp1 + tp1etp1 = 1 - e-tn - tne-tn
1
m=4
Normalized Output Voltage

0.8
m=2 m = 1 m = 0.5
m = 0.25
0.6

0.4
p2
m= p
1
0.2

0
0 2 4 6 8 10
Normalized Time (tn = -tp1 ) Fig. 8.2-2

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 2 (8/7/06) Page 8.2-9.

Linear Step Response of the Two-Stage Comparator - Continued


The above results are valid as long as the slope of the linear response does not exceed the
slew rate.
• Slope at t = 0 is zero
• Maximum slope occurs at (m 1)
ln(m)
tn(max) = m-1
and is
dvout’(tn(max)) m  
-ln(m) 

ln(m) 
dtn = exp

m-1  m-1 - exp


-m
 m-1 
• For the two-stage comparator using NMOS input transistors, the slew rate is
I7
SR- = CII
I6-I7 0.56(VDD-VG6(min)-|VTP|)2 - I7
SR+ = CII = CII

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-10.

Example 8.2-2 - Step Response of Ex. 8.2-1


Find the maximum slope of Ex. 8.2-1 and the time it occurs if the magnitude of the
input step is vin(min). If the dc bias current in M7 is 100μA, at what value of load
capacitance, CL would the transient response become slew limited? If the magnitude of
the input step is 100vin(min), what is the new value of CL at which slewing would occur?
Solution
The poles of the comparator were given in Ex. 8.2-1 as p1 = -6.75x106 rads/sec. and
p2 = -1.71x106 rads/sec. This gives a value of m = 0.253. From the previous
expressions, the maximum slope occurs at tn(max) = 1.84 secs. Dividing by |p1| gives
t(max) = 0.272μs. The slope of the transient response at this time is found as
dvout’(tn(max))
dtn = -0.338[exp(-1.84) - exp(-0.253·1.84)] = 0.159 V/sec
dvout’(t(max))
Multiplying the above by |p1| gives dt = 1.072V/μs
If the slew rate is less than 1.072V/μs, the transient response will experience slewing.
Therefore, if CL  100μA/1.072V/μs or 93.3pF, the comparator will slew.
If the input is 100vin(min), then we must unnormalize the output slope as follows.
dvout’(t( max)) vin dvout’(t( max))
dt = vin(min) dt = 100·1.072V/μs = 107.2V/μs
Therefore, the comparator will now slew with a load capacitance of 0.933pF.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 2 (8/7/06) Page 8.2-11.

Propagation Delay Time (Non-Slew)


To find tp, we want to set 0.5(VOH-VOL) equal to vout(tn). However, vout(tn) given as
 m 1 

vout(tn) = Av(0)Vin 1 - m-1e + m-1e 
-tn -mtn

can’t be easily solved so approximate the step response as a power series to get
    
m
tn2 1
m2tn2 mtn2Av(0)Vin
vout(tn)  Av(0)Vin1 - m-11-tn+ 2 + ··· + m-11-mtn+ 2 +···  



2
Therefore, set vout(tn) = 0.5(VOH-VOL)
VOH-VOL mtpn2Av(0)Vin
2  2
or
VOH-VOL Vin(min) 1
tpn  mAv(0)Vin = mVin = mk
This approximation is particularly good for large values of k.

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-12.

Example 8.2-3 - Propagation Delay Time of a Two-Pole Comparator (Non-Slew)


Find the propagation time delay of Ex. 8.2-1 if Vin = 10mV, 100mV and 1V.
Solution
From Ex. 8.2-1 we know
1
that Vin(min) = 0.611mV and m m=4
= 0.253. For Vin = 10mV, k =
Normalized Output Voltage

0.8
16.366 which gives tpn  0.491. m=2 m = 1 m = 0.5
m = 0.25
The propagation time delay is 0.6
equal to 0.491/6.75x106 or
72.9nS. This corresponds well 0.4
with Fig. 8.2-2 where the m= p
p2
1
normalized propagation time 0.2
delay is the time at which the
amplitude is 1/2k or 0.031 2k 1 = 0.031
0
which corresponds to tpn of 0
0.52
2 4 6 8 10
Normalized Time (tn = tp1 = t/τ1)
approximately 0.5. Similarly, tp = 0.52 = 77ns
6.75x106 Fig. 8.2-2A
for Vin = 100mV and 1V we get
a propagation time delay of 23ns and 7.3ns, respectively.

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 2 (8/7/06) Page 8.2-13.

Initial Operating States for the Two-Stage, Open-Loop Comparator


What are the initial operating states for VDD
the two-stage, open-loop comparator?
i3 i4
M3 v
M4 o1
M6
i1 i2 CI
vout
vG1 M1 M2 vG2
1.) Assume vG2 = VREF and vG1>VREF CII
with i1 < ISS and i2>0. ISS
+ M7
Initially, i4 > i2 and vo1 increases, VBias M5
M4 becomes active and i4 decreases -
VSS Fig. 8.2-3
until i3 = i4. vo1 is in the range of,
VDD - VSD4(sat) < vo1 < VDD, vG1 > VREF, i1 < ISS and i2 > 0
and the value of vout is
vout  VSS vG1 > VREF, i1 < ISS and i2 > 0
2.) Assume vG2 = VREF and vG1 >>VREF, therefore i1 = ISS and i2 = 0 which gives
vo1 = VDD and vout = VSS

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-14.

Initial Operating States - Continued


3.) Assume vG2 = VREF and vG1 < VREF with i1>0 and i2<ISS.
Initially, i4 < i2 and vo1 decreases. When vo1  VREF - VTN, M2 becomes active and
i2 decreases. When i1 = i2 = ISS/2 the circuit stabilizes and vo1 is in the range of,
VREF - VGS2 < vo1 < VREF - VGS2 + VDS2(sat)
or
VS2 < vo1 < VS2 + VDS2(sat), vG1 < VG2, i1 > 0 and i2 < ISS
For the above conditions,
 7ISS 
vout = VDD - (VDD-vo1-|VTP|)1 - 1-
56(VDD -vo1-|VTP|)2 
4.) Assume vG2 = VREF and vG1 << VREF, therefore i2 = ISS and i1 = 0.
Same as in 3.) but now as vo1 approaches vS2 with ISS/2 flowing, the value of vGS2
becomes larger and M5 becomes active and ISS decreases. In the limit, ISS  0,vDS2  0
and vDS5  0 resulting in
vo1  VSS and vout = VDD - (VDD-VSS-
 7ISS 

|VTP|)1 - 1-
56(VDD-VSS-|VTP|)2 

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 2 (8/7/06) Page 8.2-15.

Initial Operating States - Continued


5.) Assume vG1 = VREF and vG2>VREF with i2 < ISS and i1>0.
Initially, i4 < i2 and vo1 falls, M2 becomes active and i2 decreases until i1 = i2 = ISS/2.
Therefore,
VREF - VGS2(ISS/2) < vo1 < VREF - VGS2(ISS/2) +VDS2(sat)
or
VS2(ISS/2) < vo1 < VS2(ISS/2) + VDS2(sat), vG2 > VREF, i1 > 0 and i2 < ISS
and the value of vout is
 7ISS 
vout = VDD - (VDD-vo1-|VTP|)1 - 1- 
56(VDD -vo1-|VTP|)2 
6.) Assume that vG1 = VREF and vG2 >> VREF. When the source voltage of M1 or M2
causes M5 to be active, then ISS decreases and
 7ISS 
vo1  VSS and vout = VDD - (VDD-VSS-|VTP|)1 -  1- 
56(VDD -VSS-|VTP|)2 
7.) Assume vG1 = VREF and vG2 < VREF and i1 <ISS and i2 > 0. Consequently, i4>i2
which causes vo1 to increase. When M4 becomes active i4 decreases until i2 = i4 at
which vo1 stabilizes at (M6 will be off under these conditions and vout  VSS).
VDD - VSD4(sat) < vo1 < VDD, vG2 < VREF, i1 < ISS and i2 > 0
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-16.

Initial Operating States - Continued


8.) Finally if vG2 <<VREF, then i1 = ISS and i2 =0 and
vo1  VDD and vout  VSS.
Summary of the Initial Operating States of the Two-Stage, Open-Loop Comparator using
a N-channel, Source-coupled Input Pair:

Conditions Initial State of vo1 Initial State of vout


vG1>VG2, i1<ISS and i2>0 VDD-VSD4(sat) < vo1 < VDD VSS
vG1>>VG2, i1=ISS and i2=0 VDD VSS
vG1<VG2, i1>0 and i2<ISS vo1=VG2-VGS2,act(ISS/2), VSS if M5 Eq. (19), Sec. 5.1 for PMOS
act.
vG1<<VG2, i1>0 and i2<ISS VSS Eq. (19), Sec. 5.1 for PMOS
vG2>VG1, i1>0 and i2<ISS VS2(ISS/2)<vo1<VS2(ISS/2)+VDS2(sat) Eq. (19), Sec. 5.1 for PMOS
vG2>>VG1, i1>0 and i2<ISS VG1-VGS1(ISS/2) , VSS if M5 active Eq. (19), Sec. 5.1 for PMOS
vG2<VG1, i1<ISS and i2>0 VDD-VSD4(sat) < vo1 < VDD VSS
vG2<<VG1, i1=ISS and i2=0 VDD VSS

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 2 (8/7/06) Page 8.2-17.

Trip Point of an Inverter VDD


In order to determine the propagation delay time, it is
necessary to know when the second stage of the two-stage + M6
vin i6
comparator begins to “turn on”. - vout
Second stage: i7
M7
Trip point: VBias
Assume that M6 and M7 are saturated. (We know that the
VSS Fig. 8.2-4
steepest slope occurs for this condition.)
Equate i6 to i7 and solve for vin which becomes the trip point.
KN(W7/L7)
 vin = VTRP = VDD - |VTP| - KP(W6/L6) (VBias- VSS -VTN)
Example:
If W7/L7 = W6/L6, VDD = 2.5V, VSS = -2.5V, and VBias = 0V the trip point for the
circuit above is
VTRP = 2.5 - 0.7 - 110/50 (0 +2.5 -0.7) = -0.870V

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-18.

Propagation Delay Time of a Slewing, Two-Stage, Open-Loop Comparator


Previously we calculated the propagation delay time for a nonslewing comparator.
If the comparator slews, then the propagation delay time is found from
dvi  vi
ii = Ci dti = Ci ti
where
Ci is the capacitance to ground at the output of the i-th stage
The propagation delay time of the i-th stage is,
Vi
ti = ti = Ci Ii
The propagation delay time is found by summing the delays of each stage.
tp = t1 + t2 + t3 + ···

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 2 (8/7/06) Page 8.2-19.

Example 8.2-5 - Propagation Time Delay of a Two-Stage, Open-Loop Comparator


For the two-stage comparator shown VDD = 2.5V
assume that CI = 0.2pF and CII = 5pF. 4.5μm
M3 M4
4.5μm
M6
38μm
Also, assume that vG1 = 0V and that vG2 1μm 1μm
vo1
1μm
vout
has the waveform shown. If the input
vG1 M1 3μm M2 CI =
voltage is large enough to cause slew to 30μA 3μm 0.2pF CII =
dominate, find the propagation time delay 1μm 1μm 5pF
vG2
of the rising and falling output of the 234μA
comparator and give the propagation time 4.5μm 30μA
35μm
delay of the comparator. 1μm 4.5μm 1μm
M8 M5 1μm M7
vG2
VSS = -2.5V Fig. 8.2-5A
2.5V

0V t(μs)
0 0.2 0.4 0.6
-2.5V Fig. 8.2-5

Solution
1.) Total delay = sum of the first and second stage delays, t1 and t2
2.) First, consider the change of vG2 from -2.5V to 2.5V at 0.2μs.
The last row of Table 8.2-1 gives vo1 = +2.5V and vout = -2.5V
3.) tf1, requires CI, Vo1, and I5. CI = 0.2pF, I5 = 30μA and V1 can be calculated by
finding the trip point of the output stage.
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-20.

Example 8.2-5 - Continued


4.) The trip point of the output stage by setting the current of M6 when saturated equal to
234μA.
6 234·2
2 (VSG6-|VTP|)2 = 234μA  VSG6 = 0.7 + 50·38 = 1.196V
Therefore, the trip point of the second stage is VTRP2 = 2.5 - 1.196 = 1.304V
Therefore, V1 = 2.5V - 1.304V = VSG6 = 1.196V. Thus the falling propagation time
delay of the first stage is
1.196V
 
tfo1 = 0.2pF  30μA  = 8 ns
5.) The rising propagation time delay of the second stage requires CII, Vout, and I6. CII
is given as 5pF, Vout = 2.5V (assuming the trip point of the circuit connected to the
output of the comparator is 0V), and I6 can be found as follows:
VG6(guess)  0.5[VG6(I6=234μA) + VG6(min)]
2·15
VG6(min) = VG1 - VGS1(ISS/2) + VDS2  -VGS1(ISS/2) = -0.7 - 110·3 = -1.00V
VG6(guess)  0.5(1.304V-1.00V) = 0.152V
6 38·50
Therefore VSG6 = 2.348V and I6 = 2 (VSG6-|VTP|)2 = 2 (2.348 - 0.7)2 = 2,580μA

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 2 (8/7/06) Page 8.2-21.

Example 8.2-5 - Continued


6.) The rising propagation time delay for the output can expressed as

 2.5V 

trout = 5pF 2,580μA-234μA  = 5.3 ns
Thus the total propagation time delay of the rising output of the comparator is
approximately 13.3 ns and most of this delay is attributable to the first stage.
7.) Next consider the change of vG2 from 2.5V to -2.5V which occurs at 0.4μs. We shall
assume that vG2 has been at 2.5V long enough for the conditions of Table 8.2-1 to be
valid. Therefore, vo1  VSS = -2.5V and
vout  VDD. The propagation time delays for 3V vout
the first and second stages are calculated as 2V
1.304V-(-1.00V) VTRP6 = 1.304V
 
tro1 = 0.2pF  
30μA  = 15.4 ns
 1V
 2.5V 
  0V
tfout = 5pF 234μA = 53.42ns
vo1
8.) The total propagation time delay of the -1V
falling output is 68.82 ns. Taking the
Falling prop.
average of the rising and falling -2V Rising prop. delay time
propagation time delays gives a propagation -3V delay time
500ns
time delay for this two-stage, open-loop 200ns 300ns 400ns
Time
600ns
Fig. 8.2-6
comparator of about 41.06ns.
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-22.

Two-Stage Comparator with Increased Speed


Clamp the input stage with 1/gm loads to decrease the signal swing and avoid slew rate
limitation in the first stage.
VDD

M4 M6

M3 M8
vn vout
M1 M2
vp CL

M5
+ M9 M7 Metal
VBias
-
060808-06
Comments:
• Gain reduced  Larger input resolution
• Push-pull output  Higher slew rates

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 2 (8/7/06) Page 8.2-23.

Increasing the Gain of the Previous Comparator


Cascode output stage:
VDD

M4 M6

VNB2
M3 M7 M8

vn vout
M1 M2 M9
VNB2 M10 CL
vp

M5
+ M11 M12
VNB1
-
060808-07
Comments:
• Can also use the folded cascode architecture
• Cascode output stage results in a slow linear response (dominant pole is small)
• Poorer noise performance

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 2 (8/7/06) Page 8.2-24.

Comparators that Can Drive Large Capacitive Loads


VDD

M8 M10
M3 M4
M6
vn
M1 M2 vout
vp CL
+ M7 M9 M11
VNB1 M5
-
060808-08
Comments:
• Slew rate = 3V/μs into 50pF
• Linear rise/fall time = 100ns into 50pF
• Propagation delay time  1μs
• Loop gain  32,000 V/V
• The quiescent dc currents in the output stages are not well defined

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 2 (8/7/06) Page 8.2-25.

SUMMARY
• The two-stage, open-loop comparator has two poles which should as large as possible
• The transient response of a two-stage, open-loop comparator will be limited by either
the bandwidth or the slew rate
• It is important to know the initial states of a two-stage, open-loop comparator when
finding the propagation delay time
• If the comparator is gainbandwidth limited then the poles should be as large as possible
for minimum propagation delay time
• If the comparator is slew rate limited, then the current sinking and sourcing ability
should be as large as possible

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 3 (8/7/06) Page 8.3-1.

SECTION 8.3 – IMPROVING THE PERFORMANCE OF


COMPARATORS
Objective
The objective of this section is:
1.) Improve the performance of continuous-time, open-loop comparators
Outline
• Autozeroing techniques
• Comparators using hysteresis
• Summary

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 3 (8/7/06) Page 8.3-2.

AUTOZEROING
Principle of Autozeroing
Use the comparator as an op amp to sample the dc input offset voltage and cancel the
offset during operation.
Ideal Ideal Ideal
Comparator Comparator Comparator
vIN
- - - vOUT
+ + - +
VOS VOS CAZ VOS +VOS
+ VOS
-C
AZ

Model of Comparator. Autozero Cycle Comparison Cycle


Fig. 8.4-1

Comments:
• The comparator must be stable in the unity-gain mode (self-compensating comparators
are ideal, the two-stage comparator would require compensation to be switched in
during the autozero cycle.)
• Complete offset cancellation is limited by charge injection
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 3 (8/7/06) Page 8.3-3.

Differential Implementation of Autozeroed Comparators

φ1Ideal
vIN-
+ - vOUT = VOS
Comparator VOS
φ2 - +
- vOUT
φ1 VOS
vIN+ + Comparator during φ1 phase
φ2 VOS vIN- - vOUT
CAZ φ1 +
vIN+ + -
VOS VOS
Differential Autozeroed Comparator Comparator during φ2 phase
Fig. 8.4-2

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 3 (8/7/06) Page 8.3-4.

Single-Ended Autozeroed Comparators


Noninverting:
φ2 - φ1
φ1 CAZ vOUT
vIN +
φ2
φ1
Fig. 8.4-3
Inverting:
CAZ
vIN vOUT
φ2 - φ1
φ1 +
Fig. 8.4-4

Comment on autozeroing:
Need to be careful about noise that gets sampled onto the autozeroing capacitor and
is present on the comparison phase of the process.

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 3 (8/7/06) Page 8.3-5.

HYSTERESIS
Influence of Input Noise on the Comparator
Comparator without hysteresis:
Comparator vin
threshold
t

vout
VOH

t
VOL Fig. 8.4-6A
Comparator with hysteresis:
vin
VTRP+
t
VTRP-

vout
VOH

t
VOL
Fig. 8.4-6B
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 3 (8/7/06) Page 8.3-6.

Use of Hysteresis for Comparators in a Noisy Environment


Transfer curve of a comparator with hysteresis:
vOUT vOUT
VOH VOH

VTRP+ R1 (V -V )
R2 OH OL VTRP+
vIN 0 vIN
0
VTRP- VTRP-
VOL VOL

Counterclockwise Bistable Clockwise Bistable Fig. 8.4-5

Hysteresis is achieved by the use of positive feedback


• Externally
• Internally

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 3 (8/7/06) Page 8.3-7.

Noninverting Comparator using External Positive Feedback


Circuit: vOUT
VOH
R2
R1 (V -V ) R V
vIN R1 R2 OH OL - 1 OL
+ vOUT 0 R2
vIN
- 0
-R1VOH
R2
VOL
Fig. 8.4-7

Upper Trip Point:


Assume that vOUT = VOL, the upper trip point occurs when,
 R   R 
 1   2  R1
0 = R1+R2VOL + R1+R2VTRP+
    VTRP+ = - R2 VOL
Lower Trip Point:
Assume that vOUT = VOH, the lower trip point occurs when,
   
 R1   R2  R1
0 = R1+R2VOH + R1+R2VTRP-  VTRP- = - R2 VOH
Width of the bistable characteristic:
 
R1
Vin = VTRP -VTRP = R  VOH -VOL
+ -
2
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 3 (8/7/06) Page 8.3-8.

Inverting Comparator using External Positive Feedback


Circuit:
vOUT
VOH
vIN - vOUT R1 (V -V )
+ R1+R2 OH OL
0 vIN
0
R2 R1VOL R1VOH
R1 R1+R2
R1+R2 VOL

Fig. 8.4-8
Upper Trip Point:
R1  

vIN = VTRP+ = R1+R2VOH 


Lower Trip Point:


 R 
 1 
vIN = VTRP- = R1+R2VOL
Width of the bistable characteristic:
 R
 1  
+ -
Vin = VTRP -VTRP = R +R  VOH -VOL

1 2
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 3 (8/7/06) Page 8.3-9.

Horizontal Shifting of the CCW Bistable Characteristic


Circuit:
vOUT R1 (V -V )
VOH R2 OH OL
R2
R1 R1+R2
vIN
+ vOUT R2 VREF
0 vIN
- 0 R1|VOL|
VREF R1VOH R2
R2
VOL
Fig. 8.4-9
Upper Trip Point:
     
 R1   R2  R1+R2 R1
VREF = R1+R2VOL + R1+R2VTRP+  VTRP+ =  R2 VREF - R2 VOL

Lower Trip Point:


R1    R  
R1+R2
  2   R1
V  REF
= R1+R2VOH + R1+R2VTRP-
 

  VTRP- = R2 VREF - R2 VOH


R
 1 +R 2
Shifting Factor:
R2 VREF 


CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 3 (8/7/06) Page 8.3-10.

Horizontal Shifting of the CW Bistable Characteristic


Circuit:
vOUT R1 (V -V )
vIN - vOUT R1+R2 OH OL
+ VOH
R2
R2 R1+R2VREF
R1 0 vIN
0 R1VOH
VREF R1|VOL| R1+R2
R1+R2
VOL
Fig. 8.4-10
Upper Trip Point:

R1 


 R2 

vIN = VTRP+ = R1+R2VOH + R1+R2VREF


 

Lower Trip Point:



R1  
 R2 

vIN = VTRP- = R1+R2VOL + R1+R2VREF


 

Shifting Factor:
 R 
 2 
  V
R1+R2 REF

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 3 (8/7/06) Page 8.3-11.

Example 8.4-1 Design of an Inverting Comparator with Hysteresis


Use the inverting bistable to design a high-gain, open-loop comparator having an
upper trip point of 1V and a lower trip point of 0V if VOH = 2V and VOL = -2V.
Solution
Putting the values of this example into the above relationships gives

R1   R 
  2 
1 = R1+R2 2 + R1+R2VREF


 

and

R1   R 
  2 
0 = R1+R2 (-2) + R1+R2VREF


 

Solving these two equations gives 3R1 = R2 and VREF = (2/3)V.

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 3 (8/7/06) Page 8.3-12.

Hysteresis using Internal Positive Feedback


Simple comparator with internal positive feedback:
VDD

IBias M3 M6 M7 M4
vo1 vo2

vi1 M1 M2 vi2

M8 M5

Fig. 8.4-11
VSS

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 3 (8/7/06) Page 8.3-13.

Internal Positive Feedback - Upper Trip Point VDD


Assume that the gate of M1 is on ground and the
input to M2 is much smaller than zero. The
resulting circuit is: M3 M6 M7 M4
vo1 vo2
M1 on, M2 off  M3 on, M6 on (active), M4
and M7 off.
 vo2 is high. M2
M1
i1 = i3 i2 = i6
W6/L6
M6 would like to source the current i6 = W3/L3 i1 vin
M5
I5
As vin begins to increase towards the trip point, the
current flow through M2 increases. When i2 = i6, VSS
Fig. 8.4-12A

the upper trip point will occur.


W /L  W6/L6 i5
6 6
 i5 = i1+i2 = i3+i6 = i3+W /L
i3 = i3 1 + W /L   i1 = i3 = 1 + [(W /L )/(W /L )]

3 3 3 3 6 6 3 3
Also, i2 = i5 - i1 = i5 - i3
Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives
2i2 2i1
VTRP+ = vGS2 - vGS1 = 2 + V T2 - 1 - VT1

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 3 (8/7/06) Page 8.3-14.

Internal Positive Feedback - Lower Trip Point


VDD
Assume that the gate of M1 is on ground and the input
to M2 is much greater than zero. The resulting circuit
is: vo1 M3 M6 M7 M4
vo2
M2 on, M1 off  M4 and M7 on, M3 and M6 off.
 vo1 is high. vi1 vi1
M1 M2
W7/L7 i1 = i7 i2 = i4
M7 would like to source the current i7 = W4/L4 i2 vin
As vin begins to decrease towards the trip point, the I5
M5
current flow through M1 increases. When i1 = i7, the Fig. 8.4-12B
VSS
lower trip point will occur.
  W7/L7
W7/L7 i5
 i5 = i1+i2 = i7+i4 = W /L
i4 +i4 = i4 1 + W /L   i2 = i4 = 1 + [(W /L )/(W /L )]

4 4 4 4 7 7 4 4
Also, i1 = i5 - i2 = i5 - i4
Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives
2i2 2i1
VTRP- = vGS2 - vGS1 = 2 + VT2 - 1 - VT1

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 3 (8/7/06) Page 8.3-15.

Example 8.4-2 - Calculation of Trip Voltages for a Comparator with Hysteresis


Consider the circuit shown. Using the VDD
transistor device parameters given in Table
3.1-2 calculate the positive and negative IBias M3 M6 M7 M4
threshold points if the device lengths are all 1 vo1 vo2
μm and the widths are given as: W1 = W2 = W6
= W7 = 10 μm and W3 = W4 = 2 μm. The gate vi1 vi2
M1 M2
of M1 is tied to ground and the input is the
gate of M2. The current, i5 = 20 μA
Solution M8 M5
To calculate the positive trip point, Fig. 8.4-11
VSS
assume that the input has been negative and is
heading positive.
(W/L)6 i5 20 μA
i6 = (W/L)3 i3 = (5/1)(i3)  i3 = 1 + [(W/L)6/(W/L)3] = i1 = 1 + 5 = 3.33 μA
2i   2·3.33 
1
1/2
1/2
i2 = i5  i1 = 20  3.33 = 16.67 μA  vGS1 =  1
 +VT1 = (5)110
 +0.7 = 0.81V
2i  2·16.67
2
1/2
1/2
vGS2 =  2
 + VT2 =  (5)110
 + 0.7 = 0.946V
 VTRP+  vGS2vGS1 = 0.9460.810 = 0.136V
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 3 (8/7/06) Page 8.3-16.

Example 8.4-2 - Continued


Determining the negative trip point, similar analysis yields
i4 = 3.33 μA
i1 = 16.67 μA
vGS2 = 0.81V
vGS1 = 0.946V
VTRP-  vGS2  vGS1 = 0.81  0.946 = 0.136V
PSPICE simulation results of this circuit are shown below.
2.6

2.4
2.2
2
vo2
1.8
(volts)
1.6

1.4
1.2
1
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
vin (volts) Fig. 8.4-13
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 3 (8/7/06) Page 8.3-17.

Complete Comparator with Internal Hysteresis


VDD

IBias M3 M6 M7 M4

M9 M8

vi1 vi2
M1 M2 vout

M10 M11
M8 M5

VSS Fig. 8.4-14

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 3 (8/7/06) Page 8.3-18.

Schmitt Trigger
The Schmitt trigger is a circuit that has better defined switching points.
Consider the following circuit:
VDD How does this circuit work?
Assume the input voltage, vin, is low and the output
M5
voltage, vout , is high.
M3, M4 and M5 are on and M1, M2 and M6 are off.
M4 When vin is increased from zero, M2 starts to turn on causing
vin M3 vout M3 to start turning off. Positive feedback causes M2 to turn
M6
on further and eventually both M1 and M2 are on and the
M2 output is at zero.
The upper switching point, VTRP+ is found as follows:
M1 When vin is low, the voltage at the source of M2 (M3) is
vS2 = VDD-VTN3
Fig. 8.4-15
VTRP+ = vin when M2 turns on given as VTRP+ = VTN2 + vS2
VTRP+ occurs when the input voltage causes the currents in M3 and M1 to be equal.

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 3 (8/7/06) Page 8.3-19.

Schmitt Trigger – Continued


Thus, iD1 = 1( VTRP+ - VTN1)2 = 3( VDD - vS2- VTN3) 2 = iD3
which can be written as, assuming that VTN2 = VTN3,
VTN1 + 3/1 VDD
1( VTRP+ - VTN1) 2 = 3( VDD – VTRP+)2  VTRP+ =
1 + 3/1
The switching point, VTRP- is found in a similar manner and is:
5/6 (VDD - VTP5)
5( VDD - VTRP- - VTP5)2 = 6( VTRP-)2  VTRP- =
1 + 5/6
The bistable characteristic is, vout
VDD

0 vin
0 VTRP- VTRP+ VDD
Fig. 8.4-16

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 4 (8/7/06) Page 8.4-1.

SECTION 8.4 – DISCRETE-TIME COMPARATORS (LATCHES)


SIMPLE LATCHES
Regenerative Comparators
Regenerative comparators use positive feedback to accomplish the comparison of two
signals. Latches have a faster switching speed that the previous bistable comparators.
NMOS and PMOS latch:
VDD VDD

I1 I2 M1 M2
vo1 vo2 vo1 vo2

M1 M2 I1 I2

NMOS latch PMOS latch


Fig. 8.5-3

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 4 (8/7/06) Page 8.4-2.

Operating Modes of the Latch


The latch has two modes of operation – enable or latch and Enable (enable_bar) or
Latch (latch_bar).
1.) During the Enable_bar, the latch is turned off (currents are removed) and the
unknown inputs are applied to it. The parasitic capacitance at the latch nodes hold the
unknown voltage.
2.) During Enable, the latch is turned on, and the positive feedback acts on the applied
inputs and causes one side of the latch to go high and the other side to go low.
Enable_bar:
VDD VDD

I1 I2 M1 M2
Enable Enable Enable Enable
Vo1ʼ Vo2ʼ Vo1ʼ Vo2ʼ

M1 M2 I1 I2

NMOS latch PMOS latch 060808-09

The inputs are initially applied to the outputs of the latch.


Vo1’ = initial input applied to vo1
Vo2’ = initial input applied to vo2
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 4 (8/7/06) Page 8.4-3.

Step Response of a Latch (Enable)


Circuit: VDD VDD

Ri and Ci are the I1 I2


+ + +
resistance and capacitance vo2 C1 C2
vo1 Vo2 Vo1 Vo2
seen to ground from the Vo1' Vo2'
M1 M2 gm1Vo2 R1 s gm2Vo1 R2 s
i-th transistor. - - -
Nodal equations: Fig. 8.5-4
 Vo1’

gm1Vo2+G1Vo1+sC1Vo1- s  = gm1Vo2+G1Vo1+sC1V o1-C1Vo1’ = 0


 Vo2’

gm2Vo1+G2Vo2+sC2Vo2- s  = gm2Vo1+G2Vo2+sC2V o2-C2Vo2’ = 0


Solving for Vo1 and Vo2 gives,


R1C1 gm1R1 1 gm1R1
Vo1 = sR1C1+1 Vo1’ - sR1C1+1 Vo2 = s1+1 Vo1’ - s1+1 Vo2
R2C2 gm2R2 2 gm2R2
Vo2 = sR2C2+1 Vo2’ - sR2C2+1 Vo1 = s2+1 Vo2’ - s2+1 Vo1
Defining the output, Vo, and input, Vi, as
Vo = Vo2-Vo1 and Vi = Vo2’-Vo1’
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 4 (8/7/06) Page 8.4-4.

Step Response of the Latch - Continued


Solving for Vo gives,
 g mR
Vo = Vo2-Vo1 = s+1 Vi + s+1 Vo
or
 Vi
 Vi 1-gmR ’ Vi
Vo = s+(1-gmR) = s = s’+1
1-gmR + 1
where

’ = 1-gmR
Taking the inverse Laplace transform gives
vo(t) = Vi e-t/’ = Vi e-t(1-gmR) /  egmRt/Vi, if gmR >>1.
Define the latch time constant as
 C 0.67WLCox WL3
L = |’|  gmR = gm = 2K’(W/L)I = 0.67Cox 2K’I
if C  Cgs.
 Vout(t) = et/L Vi
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 4 (8/7/06) Page 8.4-5.

Step Response of a Latch - Continued


Normalize the output voltage by (VOH-VOL) to get
Vout(t) Vi
= e t/L
VOH-VOL VOH-VOL
which is plotted as,
1
0.5
0.4 0.3
0.8 0.2
0.1 ΔVi
VOH-VOL
0.05
0.6
ΔVout 0.03
VOH-VOL 0.01
0.4
0.005
0.2

0
0 1 2 3 4 5
t
τL Fig. 8.5-5
V 
 OH- VOL
The propagation delay time is tp = L ln  2Vi 
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 4 (8/7/06) Page 8.4-6.

Example 8.5-1 - Time Domain Characteristics of a Latch.


Find the propagation time delay for the NMOS if the W/L of the latch transistors is
5μm/0.5μm and the latch dc current is 10μA when Vi = 0.1(VOH-VOL) and Vi =
0.01(VOH-VOL).
Solution
The transconductance of the latch transistors is
gm = 2·120·10·10 = 155μS
The output conductance is 0.6μS which gives gmR of 93V/V. Since gmR is greater than
1, we can use the above results. Therefore the latch time constant is found as
WL3 (5·0.5)x10-24
L = 0.67Cox 2K’I = 0.67(60.6x10 ) 2·120x10-6·10x10-6 = 0.131ns
-4

Since the propagation time delay is the time when the output is 0.5(VOH-VOL), then
using the above results or Fig. 8.5-5 we find for Vi = 0.01(VOH-VOL) that tp = 3.91L =
0.512ns and for Vi = 0.1(VOH-VOL) that tp = 1.61L = 0.211ns.

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 4 (8/7/06) Page 8.4-7.

Comparator using a Latch with a Built-In Threshold†


How does it operate? VDD
1.) Devices in shaded region operate in the φ1 M7 M8 φ1
triode region. Latch M9 M10 Latch
/Reset /Reset
2.) When the latch/reset goes high, the upper
φ1 M5 M6 φ1
cross-coupled inverter-latch regenerates. The
drain currents of M5 and M6 are steered to M3 vout+ vout- M4
R1 R2
obtain a final state determined by the mismatch M2
M1 M2 M1
between the R1 and R2 resistances. vin+ vin-
 W W2 
1  1  VREF- VREF+
+ -
R1 = KN  L (vin - VT) + L (VREF - VT) 
 
Fig. 8.5-6
and
 W W2 
1  1 
R2 = KN  L (vin- - VT) + L (VREF+ - VT) 


3.) The input voltage which causes R1 = R2 is vin(threshold) = (W2/W1)VREF


W2/W1 = 1/4 generates a threshold of ±0.25VREF.
Performance  20Ms/s & 200μW


T.B. Cho and P.R. Gray, “A 10b, 20Msamples/s, 35mW pipeline A/D Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March
1995.
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 4 (8/7/06) Page 8.4-8.

Simple, Low Power Latched Comparator†


VDD
φ1 M7 M8 φ1
M9 M10

φ1 M5 M6 φ1
vout+ vout-
M3 M4

vin+ M1 M2 vin-

Fig. 8.5-7
Dissipated 50μW when clocked at 2MHz.


A. Coban, “1.5V, 1mW, 98-dB Delta-Sigma ADC”, Ph.D. dissertation, School of ECE, Georgia Tech, Atlanta, GA 30332-0250.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 4 (8/7/06) Page 8.4-9.

CMOS Latch
Circuit:
VDD
φLatch
M6

M8 M3 M4 +
VREF vout
vin vout-
M7
M1 M2

φLatch
M5

Fig. 8.5-8

;;
;;
;;
;;
Input offset voltage distribution:
L = 1.2μm
of Samples

20
Number

;;
;;;
;;;
σ = 5.65 (0.6μm Process)
10
0 -15 -10 -5 0 15
5 10
Input offset voltage (mV) Fig. 8.5-9
Power dissipation/sampling rate = 4.3μW/Ms/s
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 4 (8/7/06) Page 8.4-10.

CMOS Latch with Different Inputs and Outputs


VDD
Latch_bar
M5 M6
Latch
Inputs

M1 M2
Latch
M7 Outputs

M3 M4

060808-10

When Latch_bar is high, M5, M6 and M7 are off and the latch is disabled and the outputs
are shorted together.
When Latch_bar is low, the input voltages stored at the sources of M1 and M2 will cause
one of the latch outputs to be high and the other to be low.
The source of M1 and M2 that is higher will have a larger source-gate voltage
resulting in a larger transconductance and more gain than the other transistor.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 4 (8/7/06) Page 8.4-11.

Metastability
Metastability is the condition where the latch cannot make a decision in the time
allocated. Normally due to the fact that the input is small (within the input resolution
range).
Metastability can be improved (reduced) by increasing the gain of the comparator by
preceding it with an amplifier to keep the signal input to the latch as large as possible
under all conditions. The preamplifier also reduced the input offset voltage.
VDD
Latch_bar

Latch
Inputs

Comparator
Inputs Latch
Outputs

VNB1

Preamplifier Latch 060808-11

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 4 (8/7/06) Page 8.4-12.

SUMMARY
• Discrete-time comparators must work with clocks
• Switched capacitor comparators use op amps to transfer charge and autozero
• Regenerative comparators (latches) use positive feedback
• The propagation delay of the regenerative comparator is slow at the beginning and
speeds up rapidly as time increases
• The highest speed comparators will use a combination of open-loop comparators and
latches

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 5 (8/7/06) Page 8.5-1.

SECTION 8.5 – HIGH-SPEED COMPARATORS


Objective
The objective of this presentation is to show how to achieve high-speed comparators
Outline
• Limitations of high-speed comparators
• Amplifier-latch comparators
• Summary

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 5 (8/7/06) Page 8.5-2.

Speed Limitations of Comparators


The speed of a comparator is limited by either:
• Linear response – response time is inversely proportional to the magnitude of poles
jω Gain vout Propagation
Increase for Time Delay
speed σ VOH
Increase
bandwidth ω
060810-01 VOL t

• Slew rate – delay is proportional to capacitance and inversely proportional to


current sinking or sourcing capability
VDD
Propagation
ISource vout
Time Delay
VOH
+ dvout = I
ISink CL vout dt CL
− VOL t
060810-02

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 5 (8/7/06) Page 8.5-3.

Maximizing Speed for Slew Rate Limitation


The key is to make the sourcing/sinking current large and the capacitance small.
Best possible sinking/sourcing circuit in CMOS is:
VDD
M2
ISource
vIN vOUT
M1 ISink
CL
060810-03

Assuming a W/L ratio of 10 for M1 and 40 for M2, if the input can swing to VDD (=2.5V)
and ground, the sourcing and sinking currents are:
Kp'W 25·40
ISourcing = 2L (VDD – |VTP|)2 = 2 (2.5V-0.5)2 μA = 2.0 mA
Kn'W 120·10
ISinking = 2L (VDD – VTN)2 = 2 (2.5V-0.5)2 μA = 2.4 mA
If larger currents are required, cascaded stages can be used to optimize the delay versus
the current output.
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 5 (8/7/06) Page 8.5-4.

Self-Biased Differential Amplifier†


Not as good as the push-pull inverter but interesting.
VDD
VDD
VBias M6 Extremely
M6 large sourcing
M3 M4 current
M3 M4
vout
vin+ vin- vin+ vin-

M1 M2
M1 M2
M5
VBias M5
VSS Fig. 8.3-4
VSS
Advantage:
Large sink or source current with out a large quiescent current.
Disadvantage:
Poor common mode range (vin+ slower than vin-)


M. Bazes, “Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, Feb.
1991, pp. 165-168.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 5 (8/7/06) Page 8.5-5.

A Study in Exponentials
The step response of an amplifier with a gain of Ao and a dominant pole at A is,
vout(t) = Ao[1 – exp(-At)] Vin
vout
Slow rising
AoVin

Fast rising
0 t
060810-04

The latch response to a step input of Vin is,


t  

vout(t) = Vin exp tL  vout


Fast rising
2.72Vin
Slow rising

0 t
τL 060810-05

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 5 (8/7/06) Page 8.5-6.

A High-Speed Comparator Architecture


Cascade an amplifier with a latch to take advantage of the exponential characteristics of
the previous slide.
Preamplifier

+ + +
Vin Ao Vo1 Latch Vout
− − −
060810-06

In order to keep the bandwidth of the amplifier large, the gain will be small. To achieve
Preamplifier 1 Preamplifier 2 Preamplifier n
+ + + + + +
Vin Ao1/n Vo1 Ao1/n Vo2 Von-1 Ao1/n Von Latch Vout
− − − − − −

Gain = Ao 060810-08

Therefore, the question is how many stages of the amplifier and what is the gain of each
stage for optimum results?

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 5 (8/7/06) Page 8.5-7.

Ex. 8.5-1 – Optimizing the Propagation Time Delay


A comparator consists of an amplifier cascaded with a latch as shown below. The
amplifier has a voltage gain of 10V/V and f-3dB = 100MHz and the latch has a time
constant of 1ns. The maximum and minimum voltage swings of the amplifier and latch
are VOH and VOL. When should the latch be enabled after the application of a step input to
the amplifier of 0.05(VOH-VOL) to get minimum overall propagation time delay? What is
the value of the minimum propagation time delay?
vin = 0.05(VOH-VOL) voa
Amplifier vout
Latch
Av(0)=10V/V
τL=10ns
t=0 f-3dB=100MHz vil
Comparator
Enable S01E3P1
Solution
The solution is based on the figure shown.
Amplifier
We note that, VOH
voa(t) = 10[1-e--3dBt]0.05(VOH-VOL). Latch
x(VOH-VOL)
If we define the input voltage to the latch as,
t2
vil = x·(VOH-VOL) VOL t
t1 S01E3S1
then we can solve for t1 and t2 as follows:
CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 5 (8/7/06) Page 8.5-8.

Example 8.5-1 - Continued


x·(VOH-VOL) = 10[1-e--3dBt1]0.05(VOH-VOL)  x = 0.5[1-e--3dBt1]
This gives,
1  
 1 
t1 = -3dB ln 1-2x
From the propagation time delay of the latch we get,

VOH-VOL  
 1
t2 = L ln 2vil  = L ln 2x


 

1  1  1 dtp
   
 tp = t1 + t2 = -3dB ln 1-2x + L ln 2x  dx = 0 gives
2L-3dB 0.4
2x = 2+2L-3dB = 2+0.4 = 0.3859 (x = 0.1930)
10ns  1 

t1 = 2 ln 1-0.3859 = 1.592ns·0.4875 = 0.7762 ns
1  

and t2 = 1ns ln 0.3859= 0.9522ns



 tp = t1 + t2 = 0.776 ns + 0.952 ns = 1.728 ns


CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 5 (8/7/06) Page 8.5-9.

Minimizing the Propagation Delay Time in Comparators


Facts:
• The input signal is equal to Vin(min) for worst case
• Amplifiers have a step response with a negative argument in the exponential
• Latches have a step response with a positive argument in the exponential
Result:
Use a cascade of linear amplifier to quickly build up the signal level and apply this
amplified signal level to a latch for quick transition to the full binary output swing.
Illustration of a preamplifier and vout
latch cascade: VOH
Minimization of tp: Latch
Q. If the preamplifer consists of n
stages of gain A having a single- Preamplifier
pole response, what is the value of
n and A that gives minimum VX
propagation delay time? t1 t2
A. n = 6 and A = 2.62 but this is a V OL t
Fig. 8.6-2
very broad minimum and n is
usually 3 and A  6-7 to save area.

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 5 (8/7/06) Page 8.5-10.

Fully Differential, Three-Stage Amplifier and Latch Comparator


Circuit:
FB FB FB
Sample Cv1 FB Cv3 FB Cv5 FB
+ - + - + - +
+
vin Sample FB FB FB Latch vout
- -+ -+ -+
Reset Reset Reset Reset -
Cv2 Cv4 Cv6
060810-08 FB FB FB Clock
Comments:
• Autozero and reset phase followed by comparison phase
• In the autozero phase, switches labeled “Reset” and “FB” are closed.
• In the sample phase, switches labeled “Sample” and “ FB ” are closed.
• Can run as high as 200Msps

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 5 (8/7/06) Page 8.5-11.

Preamplifier and Latch Circuits


Gain: VDD
gm1 gm2 KN’(W1/L1) M3 M4
Av = - gm3 = - gm4 = - Kp’(W3/L3)
Dominant Pole: Q
FB Reset
gm3 gm4
|pdominant| = C = C Q
FB
where C is the capacitance seen from the M1
M5 M6
output nodes to ground. M2

If (W1/L1)/(W3/L3) = 100 and the Enable Latch


bias current is 100μA, then A = -3.85 Preamplifier Latch
and the bandwidth is 15.9MHz if C =
0.5pF. VBias
Comments: Fig. 8.6-4
• If a buffer is used to reduce the output
capacitance, one must take into account the loss of the buffer.
• The use of a preamplifier before the latch reduces the latch offset by the gain of the
preamplifier so that the offset is due to the preamplifier only.

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 5 (8/7/06) Page 8.5-12.

An Improved Preamplifier
Circuit:
VDD
VBiasP VBiasP
M3 M4
vout- M5 M6 vout+
Reset

M10 M12
FB M11 FB
M7 M8
VBias
vin+ vin-
M1 M2

VBiasN
M9
Fig. 8.6-5
Gain:
gm1 KN’(W1/L1)I1 KN’(W1/L1) I5
Av = - gm3 = - KP’(W3/L3)I3 = - KP’(W3/L3) 1+I3
If I5 = 24I3, the gain is increased by a factor of 5

CMOS Analog Circuit Design © P.E. Allen - 2006


Chapter 8 – Section 5 (8/7/06) Page 8.5-13.

Improved Frequency Response of the Amplifier


If the ratio of transconductance W/L is much larger than the load W/L, the frequency
response will suffer. Using the technique of the previous slide, we can keep the ratio of
the W/Ls to a more reasonable value. The result is higher frequency response.
Amplifier of Example 7.2-3:
VDD
VPB1 VPB1
I5 I3 I4 I6
Μ5 Μ3 V Μ4 Μ6
Μ1 − out + Μ2
+ I1 I2
Vin

VNB1 I7
Μ7
060711-01

Gain = 20dB
f-3dB = 551MHz

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 8 – Section 6 (8/7/06) Page 8.6-1.

CHAPTER 8 - SUMMARY
Types of Comparators Presented
• High-gain, open-loop
• Improved high-gain, open-loop, comparators
Hysteresis
Autozeroing
• Regenerative comparators
• High-speed comparators
Performance Characterization
• Propagation delay time
• Binary output swing
• Input resolution and/or gain
• Input offset voltage
• Power dissipation
Important Principles
• The speed of the comparator depends on the linear and slewing responses
• The dc input offset voltage depends on the matching and is reduced by autozeroing.
Charge injection is the limit of autozeroing
• The comparator gain should be large enough for a binary output when vin = Vin(min)
• High speed comparator use preamplifiers cascaded with a latch
CMOS Analog Circuit Design © P.E. Allen - 2006