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COURSE PLAN
ASSESSMENT PLAN:
1. In Semester Assessments - 50 %
2 Tests each of 15 marks
Written tests :
3 Group activity/Mini-Project
4
5
Portions for Sessional Test
Test no. Topics/Lessons
1 L0-L14
2 L15-L28
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Course Outcomes (COs)
CO2: Discuss the architectural features and digital circuit implementation using FPGAs and 1,2,5,6,7,8,9,10
CPLDs. 22
CO3: Discuss various testing methods and DFT methodologies employed in digital design. 1,2,5,6,7,8,9,10
04
CO4: Write and analyze the Verilog code for given design using behavioral, switch level, 1,2,5,6,7,8,9,10
04
data flow and structural modeling styles.
CO5: Write the Verilog code for system level building blocks. 1,2,3,4,5,6,7,8,9,10
09
CO6: 1,2,5,6,7,8,9,10
05
Course Plan
Course
L. No. Topics Outcome
Addressed
L0 Introduction to COs
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Course
L. No. Topics Outcome
Addressed
L 13 Implementation of combinational and sequential circuits using FPGAs: Shannon’s decomposition.
L16 D algorithm
L 17 Boolean difference
L18 PODEM
L19 ITG
L23 Introduction to HDL, VHDL versus Verilog, Verilog description of combinational circuits
L 24 Verilog modules
L 28 Delays in Verilog
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Course
L. No. Topics Outcome
Addressed
L 39 System level design of real-world examples using Verilog : LED displays, ALU
L40 System level design of real-world examples using Verilog : UART, GPIO
L41
L42
L43
L44
L45
L46
L47
L48
References:
1. M. J. S. Smith, Application Specific ICs, Pearson 1997.
2. Charles Roth, Lizy Kurian John, Byeong Kil Lee, Digital System Design Using Verilog, 1st Edition, 2016.
3. Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall Publishing, Second edition,
2010.
4. Stephen. Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, TMH, 2013.
5. Parag K. Lala, Fault tolerant and Fault testable hardware design, BS Publication, 1990.
6.
7.
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Submitted by:
Date:
Approved by:
(Signature of HOD)
Date:
*********
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