This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPWRD.2016.2580585, IEEE
Transactions on Power Delivery
Current Transformer Saturation Prevention using a
Controlled Voltage Source Compensator
Ehsan Hajipour, Student Member, IEEE, Mehdi Vakilian, Senior Member, IEEE, and
Majid Sanaye-Pasand, Senior Member, IEEE
Abstract—Current transformer (CT) saturation causes severe
distortion in the measured current waveform which may lead
to mal-operation of the protective devices. This paper proposes
a low-cost, power electronic device to prevent the CT from
saturation. The proposed compensator is inserted in series with
the relay in the CT secondary circuit and acts as a controlled volt-
age source (CVS). The proposed CVS generates a time varying
voltage to cancel the voltage developed across the CT burden;
therefore, the CT magnetic flux remains almost constant and
undistorted during the power system transients. It will be shown
that this device can precisely compensate fault current, inrush
current, and other probable transient currents despite of its
simplicity. The proposed device can be employed to compensate
the already in-service CTs connected to non-digital and digital
relays. Comprehensive computer simulations are carried out
to validate the effectiveness of the proposed compensator. The
performance of a sample compensator of this type is validated
through special high current laboratory experiments (carried out
over several hundred Amperes up to 1.6 kA) and the obtained
results illustrate the capability of the proposed compensator to
prevent CT saturation.
Index Terms—Current transformer (CT), CT compensation,
CT saturation, hardware-based compensator.
I. I NTRODUCTION
T HE accurate and proper performance of protection de-
vices is directly related to the correct replication of power
system high current waveform in the current transformer (CT)
secondary terminal [1]. Consequently, current waveform dis-
tortion due to CT saturation significantly threatens the reliable
operation of the relays [2], [3]. CT saturation compensation is
a safe and effective way to prevent the relays mal-operation.
This paper mainly focuses on the saturation compensation of
the already in-service CTs which may become undersized over
the years due to: i) the unanticipated changes in the power
system topology (i.e. transmission line construction) and thus,
increase in the power system short circuit capacity [4], ii)
implementation of auto-reclosing schemes in an existing power
network [5]. In these cases, replacement of the undersized CT
is an expensive and undesired solution, where the number of
changes during a substation refurbishment needs to be kept
minimum [6].
E. Hajipour and M. Vakilian are with the Center of Excellence in
Power System Management and Control, Department of Electrical Engi-
neering, Sharif University of Technology, Tehran 11365-11155, Iran (e-mail:
e hajipour@ee.sharif.edu; vakilian@sharif.edu).
M. Sanaye-Pasand is with the Electrical and Computer Engineering School,
College of Engineering, University of Tehran, Tehran 14395-515, Iran. He
is also with the Control and Intelligent Processing Center of Excellence,
Electrical and Computer Engineering School, University of Tehran, Tehran
14395-515, Iran (e-mail: msanaye@ut.ac.ir).
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In recent years, the new generation of digital relays is
sometimes equipped with a software-based CT saturation
detection/compensation unit [2]. This unit detects the inception
of a CT saturation incident and tries to prevent the relay
inappropriate operation by blocking its trigger command [7]
or by reproduction of the distorted samples of the CT output
current [8]. Various valuable algorithms have been presented in
the literature which focus on the detection of CT saturation [1],
[9], [10], and to digitally compensate the CT distorted output
[4], [8], [11], [12]. These algorithms can be implemented only
into the modern digital relays [13]. In addition, they might not
be able to accurately reproduce the input current in all different
scenarios.
A major part of the already in-service relays are elec-
tromechanical, static and initial digital type relays that do not
support digital inputs and modern communication protocols.
For example, a power system asset analysis implemented by
National Grid USA in New York State depicts that over 85%
of the relay population in their system are non-digital relays
[14]. These types of relays cannot be equipped with the afore-
mentioned software-based saturation compensation/detection
algorithms. In this case, hardware-based compensation of the
CT is a low-cost and effective solution that can be employed.
A hardware-based CT compensator is an analog circuit
inserted into the CT secondary circuit and prevents the CT
from saturation. This type of compensators does not break
the analog connection between the CT and the relay and
can be employed to compensate a CT which is connected
to either non-digital or digital relays. In [15]–[17], different
hardware-based algorithms have been proposed to estimate
and compensate the CT magnetizing current. These algorithms
are only applicable to measurement CTs. In [18], the dc
offset component of a CT’s secondary transient current is
eliminated by injection of a similar compensating current into
the CT secondary winding terminals. A major drawback of
this method is the dependence of its performance on accurate
estimation of the fault inception instant. Additionally, its
performance will be affected by presence of noise [13]. In
[5], the CT has been compensated during the dead time of an
auto-reclosing scheme. Through the dead time interval, the CT
primary winding is open-circuit and therefore, the proposed
hardware compensator of [5] could eliminate the CT residual
flux employing a bi-directional controlled switching. However,
when the fault current is flowing in the power system, the CT
primary current is not zero and consequently, the proposed
compensator in [5] is not applicable. In [13] and [19], a resistor
is dynamically inserted into the CT secondary circuit by a
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Rb Lb
i1 i2
+
vB
-
+
+
Magnetizing
vCVS
Branch
vCT
-
- where λ(t0 ) represents the CT magnetic flux at t0 .
Fig. 1. Schematic diagram of the proposed compensator.
power electronic switch, generating a flux to oppose the time-
varying flux associated with the decaying dc component of the
fault current. In this method, heat dissipation is a factor that
might hinder its application [1].
It should also be noted that: while, all of the aforementioned
hardware-based methods only focus on the CT compensation
under presence of a fault current, this paper opens a new
door to reproduce other saturated current waveforms, such as:
inrush current, harmonically polluted current [11], and evolv-
ing faults. This paper employs a low-voltage dc source, four
power-electronic switches, and a low-cost microprocessor to
prevent CT saturation. Using a simple switching strategy, the
proposed compensator applies a voltage (equal and opposite to
that of the CT burden) to the CT secondary circuit terminals.
Therefore, the voltage across the CT core is kept virtually
zero and thus, the CT magnetic flux remains almost constant
and undistorted. Theoretically, the proposed compensator can
inhibit CT saturation independent of the CT primary current
waveform. In addition, this paper introduces a simple formu-
lation to determine the appropriate parameters of the proposed
compensator. The results of a wide range of simulations which
are carried out on an accurate CT model has revealed the
efficiency and reliability of the proposed method. Furthermore,
the performance of the proposed method is verified against a
sample protective CT, through experimental results.
II. T HE P ROPOSED C OMPENSATION A LGORITHM
A. Theoretical Background of the Proposed Compensator
The schematic diagram of the proposed compensator struc-
ture is illustrated in Fig. 1. The proposed compensator is
connected in series with the CT burden, which consists of
the CT internal resistance and reactance, the lead equivalent
impedance, and the relay burden. Therefore, the voltage across
the CT magnetic core vCT can be obtained as follows:
vCT (t) = vB (t) + vCV S (t)
where vB and vCV S represent the voltage developed across the
CT burden and the compensator output voltage, respectively.
In this paper, the compensator output voltage vCV S is
controlled such that it satisfies the following integral equation:
Zt Zt
vCV S (τ )dτ = − vB (τ )dτ (2)
t0 t0
Therefore, the CT magnetic flux λ(t) can be computed using
(1) and (2) through the following relation:
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Transactions on Power Delivery
The Proposed Compensator Rt Rt
λ(t)−λ(t0 ) = vCT (τ )dτ = [vB (τ ) + vCV S (τ )] dτ →
VCVS t0 t0
CVS Unit
Rt Rt
µ-Processor
λ(t)−λ(t0 ) = vB (τ )dτ + vCV S (τ )dτ = 0 → λ(t) = λ(t0 ).
Analogue
Interface
t0 t0
(3)
i2 Process Unit Theoretically, (3) shows that in an ideal operation of the
proposed compensator, the CT magnetic flux remains constant
over time, independent of the magnitude and waveform of the
CT primary current and therefore, the CT will not saturate.
This observation is valid for any current waveform such
as symmetrical sinusoidal current, fault current including a
decaying dc component, inrush current and combination of
them.
To implement the aforementioned compensation algorithm,
firstly, the CT secondary current i2 (t) is sampled by a high
precision current sensor. Then, as shown in Fig. 1, vB (t) can
be calculated as follows:
di2 (t)
vB (t) = Rb i2 (t) + Lb (4)
dt
where Rb and Lb are the resistance and inductance of the CT
secondary circuit. These parameters can be measured using
the CVS unit as demonstrated in [20].
The proposed compensator estimates its required output
voltage vCV S (t) based on the estimated vB (t) and through
(2). Afterwards, the proper command is sent to the controlled
voltage source (CVS) unit and it applies vCV S (t) to the CT
secondary circuit terminals.
The following sections describe the proposed hardware of
the CVS unit and its switching strategy to realize the relation
in (2).
B. Hardware Implementation
Fig. 2 depicts hardware implementation of the pro-
posed compensator. This hardware consists of a dc voltage
source, four power electronic switches (including freewheeling
diodes), an instant-on switching solid-state relay (IO-SSR),
and a microprocessor which manages the switching sequence.
To minimize the adverse effect of the power plant noise on
the proper performance of the proposed compensator, it is
recommended to install this device adjacent to the relay in
the substation relay room.
Under normal operating condition of the power system,
the proposed compensator is bypassed by the IO-SSR. This
normally closed (NC) contactor will prevent occurrence of any
undesired open-circuit in the CT secondary circuit. After the
(1) detection of a transient inception, the microprocessor issues
a control command to open the IO-SSR. Simultaneously, the
compensator which has been already bypassed by the IO-SSR,
is inserted into the CT secondary circuit. The typical response
time of an IO-SSR is less than 1 ms [21], while a CT would
not become saturated at least for about 1/6 of cycle (3.3 ms
for a 50 Hz power system) after the fault inception [22].
In this paper, the instantaneous current algorithm [23] has
been employed for fast fault detection. In this method, a
transient inception is detected when 16 consecutive samples
of the CT secondary current i2 (t) exceed the CT nominal
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Transactions on Power Delivery

Controlled Voltage Source (CVS) Unit 50

40
1

vB(V)
30

IO-SSR
VDC 

vCVS
20 ΔTTd d
10 t2 t4
t1 t3
0
0 0.5 1 1.5 2 2.5
Gates

0
Control

vCVS (V)
Signal i2
μProcessor 2
Conditioning -V
-VDDC
1 2 5
Signal Processing Unit  on  on  on
0 0.5 1 1.5 2 2.5
Fig. 2. Hardware implementation of the proposed compensator. Time (ms)

Fig. 3. The basic concept of the switching control strategy.

secondary current (1 A or 5 A). Since this algorithm only
uses three processor operations (two COMPARE instructions, Fault Detector NOT
and one ADD instruction), it can be implemented by using FD AND
Switch on
a fast sampling rate (200 kHz employed in this paper). At 0 CVS unit
this sampling frequency, this detection algorithm leads to a vref

Compare
delay of 80 µs. It should be noted that during the operation of vCVS AND
Close
the compensator, the freewheeling diodes across the electronic IO-SSR
meas.
switches prevent the CT secondary current from being chopped vCVS
abruptly [24]. Unhealthy Status
In the proposed compensator, the microprocessor controls
Fig. 4. The proposed logic used to detect the compensator unhealthy status.
the CVS output voltage by turning the switches ON or OFF.
By proper control of these switches, the microprocessor is
able to generate arbitrary voltage pulses with desired width
paper, the current sensor sampling rate is 200 kHz, while the
and magnitude of [−VDC , 0, +VDC ].
compensator output pulses are generated with delay frequency
of fd = 1/∆Td = 25 kHz, as shown in Fig. 3.
C. Switching Control Algorithm As it can be seen in Fig. 3, there is a time delay of
Fig. 3 depicts the basic concept of the proposed switching ∆Td between vCV S (t) and vB (t). In this paper, ∆Td is set
control algorithm. This figure demonstrates a typical voltage to 40 µs. The effect of this time delay on the performance
developed across the CT burden vB and its corresponding of the proposed compensation method will be thoroughly
compensator output voltage vCV S . As shown in Fig. 3, in investigated in section III-B.
the proposed switching strategy, time is discretized through If the magnitude of VDC is not chosen properly, it is
i i
application of a set of constant steps of ∆Td . At the beginning possible to obtain δon > 1, through (5). In this case, δon
i
of each time step ti , a control command δon i
is sent from should be set to +1, or −1; depending on the sign of δon .
the microprocessor to the CVS. This command contains: 1) A formula is introduced in section III, in order to select the
polarity of the desired voltage sgn(δon i
)=[−1,0,+1] and 2) VDC parameter appropriately and to prevent obtaining a value
i
i
width of the required pulse |δon | in percentage of ∆Td . of δon > 1.
In the proposed switching control, the pulse width is de-
termined such that the integral of vCV S (t) over each step of D. Self-Checking Routine
∆Td equals to the integral of vB (t) over the past recent time
step. For example, in Fig. 3, the δon 5
is selected in a way that Since the proposed compensator is installed in series with
A1 equals A2 (A1 = A2 ). To achieve this, one may estimate the CT secondary circuit, it should be ensured that any
i+1
δon as follows: probable failure of its components would not affect the ap-
Rti Rti propriate performance of the protection system. Therefore,
i+1
VDC δon ∆Td = −Rb i2 (t)dτ − Lb di2 (τ ) it is recommended to equip the device with a self-check
" ti−1 ti−1 # scheme. The proposed logic to check the health status of the
i+1 −Rb
Rti Lb device is depicted in Fig. 4. F aultDetector unit, which was
→ δon = VDC ∆Td i2 (t)dτ + Rb (i2 (ti ) − i2 (ti−1 ))
ti−1 described earlier, determines the power system condition. If
(5) power system operates under normal condition, F D would be
The CT secondary current i2 (t) is sampled at a frequency zero, otherwise F D = 1.
of fs , 200 kHz in this paper. Therefore, the above integral Under normal operation of the power system (F D = 0),
would be substituted by a simple trapezoidal rule of integration the IO-SSR switch is closed and all of the CVS switches are
determination and summation. It should be noted that in this kept in OF F state. Therefore, the output voltage across the

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Transactions on Power Delivery

meas. meas. 1
CVS unit (vCV S ) would be zero (vCV S = vref = 0). If VXnew  5VXold
occurrence of any failure causes IO-SSR to open, then, an
open-circuit voltage would appear across the IO-SSR switch.
0.8
  0.65 VXnew  2VXold
The compensator monitors the CVS output voltage (vCV meas.
S ),
0.6   0.36


and if any non-zero voltage is observed, it switches the
0.4
CVS unit ON in order to short the CT secondary circuit.
Simultaneously, an alarm signal (Equipment Failure EF as 0.2
stated in IEC 60044-8 [25]) will be sent to the substation
control room. 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Under power system fault circumstance (F D = 1), the VXold VXnew
IO-SSR switch is opened and the CVS unit compensates
the voltage developed across the CT burden. If any failure Fig. 5. Appropriate value of α based on (8).
threatens the proper operation of the CVS unit (such as burning
of the switches), the measured output voltage of the CVS unit
meas.
(vCV S ) would not be equal to the reference voltage (vref = the primary system reactance and resistance up to the point of
vCV S ) selected by the processor. The processor monitors the desired power system fault.
CVS output voltage, and if a difference is found between this Assume that for an already in-service CT or for a newly
meas.
voltage and its reference (vCV S 6= vref = vCV S ), then the installed CT, it is required to increase the CT saturation voltage
processor issues a close command to the IO-SSR and the CVS from VXold to VXnew by using the proposed compensator.
unit is bypassed. Simultaneously, an alarm signal (Equipment Parameter α is defined as follows:
Failure) will be sent to the substation control room. VDC
α = √ new (7)
As it can be seen, the IO-SSR and the CVS unit backup 2VX
each other and therefore, considerably reduce the compensator It is shown in the appendix that the new saturation voltage
probability of threatening the proper operation of the protec- of the CT would be equal or greater than VXnew , if α satisfies
tion system under an unhealthy status. the following"constraint:
√ #
1 − α2 π −1 V old
III. S ELECTION OF T HE C OMPENSATOR PARAMETERS α − − sin α ≤ X (8)
α 2 VXnew
It is trivial that if the magnitude of dc voltage source Fig. 5 depicts the minimum value of α which satisfies the
VDC is selected equal or larger than the maximum magnitude equality condition of relation (8), while the ratio of VXold to
of vB (t), then, the proposed compensator can completely VXnew (the right hand side term in this relation) is varied. If
cancel the burden voltage at each time step and therefore, α is set to 1, then, the compensator completely cancels the
CT saturation will be certainly prevented. In this case, the effect of the voltage developed across the CT burden and
CT magnetic flux remains constant over time. However, it consequently, the CT magnetic flux remains constant over
is quite reasonable and practical to design the compensator time. While, If α < 1, then the magnetic flux λ(t) can vary
in such a way that the CT magnetic flux varies between over time, however it would not exceed the CT saturation
its two saturation limits (positive and negative), and not to flux and consequently, the CT will not saturate. In this case,
exceed these limits. In response, the magnitude of dc voltage the compensator supports the CT to feed its burden up to
source VDC could be decreased to reduce the compensator its nameplate rating without losing its accuracy. Refer to the
requirement. To do so, the standard procedure of CT sizing appendix for more detailed description.
based on the CT saturation voltage VX is employed in this The steps which should be followed for proper determina-
section [26]. tion of VDC are summarized as follows:
1) The real saturation voltage of the CT is obtained using
A. Appropriate Magnitude of DC Voltage Source its nameplate information or through some proper tests
For a CT, the saturation voltage VX is defined as that of and is represented by VXold ;
symmetrical voltage across the secondary winding of the CT 2) Based on the power system parameters, and the CT
for which the peak induction just exceeds the saturation flux burden, the required saturation voltage of the CT VXnew
density [26]. The CT saturation voltage is a key parameter (to avoid its saturation) is calculated through (6);
for the proper CT sizing. For example, (without using any 3) By solving the equality condition in relation (8), the
compensator) to avoid saturation of a CT due to a fault current minimum acceptable value of α is determined.
including a dc offset component and under a pure resistive 4) The appropriate value of VDC is calculated as follows:
√
burden, the CT saturation voltage should be higher than the VDC ≥ α (1 + ε) 2VXnew (9)
right hand side term of (6), as it is determined
 in [26]: where ε represents the error which is introduced into
X this computation process by inherent time delay of
VX > Is × Zs 1 + (6)
R the compensator, as will be discussed in the following
where Is is the primary current divided by the CT turns ratio, section.
and Zs is the total secondary burden of the CT. X and R are 5) According to IEC 60044-8 [25], the rated auxiliary dc

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Transactions on Power Delivery

Voltage (V) Current (A)

30 50
 f d  25 kHz 0
 = 5.03%
 (%)

20
%

   5.03% -50 (a)

10 500

0 0
5 10 15 20 25 30 35 40 45
ffdd (kHz)
(kHz) -500 (b)
2.0
Bsat

B (T)
Fig. 6. The compensation error ε contributed by the compensator time delay 0
(VXnew /V old = 4).
X
-2.0 (c)
40 45 50 55 60 65 70 75 80
Time (ms)
power supply voltage of an electronic current trans-
former (ECT) can be selected from the standard values Fig. 7. a) The CT secondary current without (solid line) and with (dash
of {24 V, 48 V, 60 V, 110 V, 220 V}. Therefore, the line) compensation, b) vB (dash line) and vCV S (solid line), c) the CT
magnetic flux density without (solid line) and with (dash line) the proposed
nearest larger value of these standard levels should be compensator.
chosen as VDC .

A. Steady State Analysis

B. Proper Value of ∆Td
As it can be seen in Fig. 3, a time delay equal to ∆Td exists
between the compensator output voltage vCV S and the voltage
across the CT burden vB . It is shown in the appendix that this
delay will result in an error of ε as follows:
V new
ε = 2 Xold sin (πf ∆Td ) (10)
VX
where f is the power system nominal frequency.
Fig. 6 depicts ε versus the delay frequency fd = 1/∆Td
where VXnew /VXold = 4. As it can be seen, through this
equation a delay frequency of 4 kHz results in an error of
about 31.4%. However, if the frequency is increased, its error
reduces rapidly to a value of about 5.03% in fd = 25 kHz. In
this paper, the delay frequency is set to 25 kHz (in a 50 Hz
power system) and therefore, ∆Td would be 40 µs. The error
introduced by this time delay is canceled through choosing a
proper value for VDC as in(9).
IV. S IMULATION R ESULTS
In this section, several simulations are presented to show
the effectiveness of the proposed compensator. An appropriate
CT model, including accurate representation of the magnetic
core hysteresis characteristic is developed using the Jiles-
Atherton theory [27]. The simulated CT is 300:1-8 VA and
its parameters have been provided in [4]. The CT saturation
voltage is VXold = 205 V. Assume that, in order to avoid CT
saturation it is required to increase the CT saturation voltage
to VXnew = 2VXold = 410 V. Realizing that the delay frequency
fd is set to 25 kHz, the error of ε would be 2.5%. In addition,
α is equal to 0.36 according to Fig. 5. Therefore, using (9), the
required voltage magnitude of the dc voltage source is 214.0
V, while it is assumed to be 220 V (a standard dc voltage
level for auxiliary dc power supply in the substations [25]).
The CT burden Zb is the CT nominal burden of 8 Ω (with
power factor of 0.8). The current sensor sampling frequency
fs is assumed to be 200 kHz.
In this section, performance of the proposed compensator is
investigated during steady state symmetrical ac current injec-
tion. The total CT secondary circuit impedance |RCT + Zb |
is 9.76 Ω. Therefore, an ac current with the magnitude of
i2 = 42.0 A generates VXnew = 410 V across the CT sec-
ondary terminal. Fig. 7 depicts the performance of the CT
with and without the proposed compensator. Fig. 7(a) shows
that without the compensation application, the CT becomes
deeply saturated, while the proposed compensator prevents CT
saturation. Fig. 7(b) depicts the voltage across the CT burden
vB and the compensator output voltage vCV S . As it can be
seen, vCV S is in phase with vB and in opposite polarity. Fig.
7(c) illustrates the corresponding magnetic flux density B. As
it can be seen, in the compensated CT, the maximum value of
B is about Bsat , which verifies the formulas presented in the
paper appendix, where the value of VDC is chosen in such a
way to limit the maximum of B to Bsat .
Fig. 8 depicts the CT input/output ratio curve between the
RMS of its primary current I10 and the RMS of its secondary
current I2 under different values of VDC . In an ideal operation
of the CT, this curve should follow a straight line of I2 =
I10 . As it can be seen in this figure, by variation of VDC ,
CT accuracy limit primary current Ial [25] can be arbitrary
tuned to avoid the core saturation. Without compensation, the
CT accuracy limit primary current is Ial old
= 25.5 A (indicates
a 5P20 CT based on IEC 60044-8 [25]). However, while the
VDC parameter is set to 220 V, the CT accuracy limit primary
current is increased to Ial new
≈ 2Ialold
= 48.8 A (represents a
5P40 CT based on IEC 60044-8 [25]). Therefore, one may
conclude that VXnew = 2VXold ; as it was requested in the first
stage.
B. Transient Currents Analysis
This section investigates the performance of the proposed
compensator during power system transient currents. A perma-
nent fault of 2.5 kA (rms) has a fully offset decaying dc com-
ponent, and a time constant of τ = 100 ms has been injected

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Transactions on Power Delivery

100
30 ideal

Current (A)
20 Uncomp.
80 67.1 A
10 Comp.

}
440 V
60 48.8 A 0
I2 (A)

VDC
35.2 A 220 V -10 (a)
40 25.5 A 110 V (b)
200

Voltage (V)
Uncomp.
20 0

0 -200
0 20 40 60 80 100
2 (c)
I1' (A)

B (T)
Fig. 8. CT input/output ratio curves when the VDC parameter varies. 1
Compensated
Uncompensated
0
20 ideal 50 100 150 200
Current (A)

Uncomp. Time (ms)

10 Comp.
Fig. 10. a) The CT secondary current in the presence of a 3.5 kA fault, b)
0 vB (t) (dash line) and vCV S (t) (solid line), c) the CT magnetic flux density.
(a)
200 (b)
Voltage (V)

phase displacement are less than 0.21%, and 3.6 minutes,

0
respectively.
Fig. 11(a) depicts a complex fictitious scenario to verify
-200
2 (c)
the independence of the proposed compensator from the CT
primary current waveform. In this imaginary case, an inrush
B (T)

1
0
50 100
Time (ms)
Fig. 9. a) The CT secondary current in the presence of a 2.5 kA fault, b)
vB (t) (dash line) and vCV S (t) (solid line), c) the CT magnetic flux density.
to the CT primary terminals, as shown in Fig. 9(a). Without
using the compensation scheme, the CT experiences a deep
saturation, while the compensator prevents this phenomenon.
Fig. 9(b) depicts the compensator output voltage vCV S and the
voltage across the CT burden vB . As it can be seen, in this
case, the maximum of vB is less than VDC = 220 V (similar to
a case of α = 1), therefore, as shown in Fig. 9(c), the proposed
compensator can properly maintain the magnetic flux density
B virtually zero. This observation verifies the effectiveness of
the proposed switching strategy. A typical full-cycle discrete
Fourier filter (DFT) has been employed to extract the CT
ratio error and the CT phase displacement. For the scenario
considered here, the maximum CT ratio error and phase error
are less than 0.04%, and 1.4 minutes, respectively.
Fig. 10(a) illustrates a similar fault with a magnitude of 3.5
kA. As it can be seen in Fig. 10(b), once α is selected less
than 1 (0.36 in this study), the compensator lets the CT to
supply its burden, without saturation, up to its nominal rating.
Therefore, the CT magnetic flux density deviates from zero;
however, it is shown in the appendix that the CT magnetic
flux would stay certainly below the CT saturation flux λsat .
Thus, the CT will not enter its saturation region. In this
scenario, the CT maximum ratio error, and the CT maximum
current waveform is appeared in the first two cycles of the CT
Uncompensated
primary current. Then, a permanent fault is happened. The du-
Compensated
ration of this initial fault assumed to be 2 cycles, followed by
150 200 an auto-reclosing dead time of 2 cycles. Afterward, the circuit
breakers are closed again and the second fault is experienced.
As it can be seen in Fig. 11(b), the proposed compensator
output voltage vCV S precisely follows the variation of vB .
Fig. 11(c) illustrates how the compensator properly prevents
the CT core from saturation, while without using the proposed
compensator, the CT experiences a deep saturation. In this
case, the CT maximum ratio error and its phase displacement
are less than 0.06%, and 5.2 minutes, respectively. This figure
depicts that the proposed compensation methodology works
properly while it is independent of the current waveshape
(inrush, fault, and combination of them). This promising
feature distinguishes the proposed compensator from others
available in the literature [13], [15]–[19].
V. E XPERIMENTAL R ESULTS
In order to show the reliability and effectiveness of the pro-
posed compensator, experimental test are also carried out. The
developed compensator consists of: i) a low-cost dsPIC33F
Microchip as the microprocessor, ii) a LA 25-NP LEM Hall
effect current sensor with high immunity to external infer-
ences, iii) four IRFP3710 IOR fast power MOSFET switches
and, iv) a Siemens V2306 miniature power PCB relay as the
normally closed (NC) IO-SSR contactor. In addition, an AC-
DC converter (220 Vac to 24 Vdc) has been employed as the
compensator dc voltage source.
A 300:1 10P5-1VA protective current transformer is chosen
to be compensated. The CT saturation voltage VXold is 4.82 V
and it is desired to increase this saturation voltage to VXnew =

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPWRD.2016.2580585, IEEE
Transactions on Power Delivery

50:1 I1
Ideal Regulating R Standard CT
20 Transformer
Current (A)
Transformer
Uncomp. Ammeter
10 Comp. Diode A
High Current

220 V
(transient test)
0 Loop I2 Burden

-10 (a)
Clamp Test CT
200 (b)
Voltage (V)

Current Sensor IO-SSR

0

dsPIC33FJ256
Analogue
Interface
-200
2 (c)
Switches Gates
B (T)

1 Comp. USB
Uncomp.
Process Unit CVS Unit
0
0 20 40 60 80 100 120 140 160 180
Time (ms) Fig. 12. Schematic diagram of the experimental test setup.

Fig. 11. a) The CT secondary current in an autoreclosing scheme, b) vB (t) TABLE I

(dash line) and vCV S (t) (solid line), c) the CT magnetic flux density. L ABORATORY- MEASURED RATIO ERRORS AND PHASE DISPLACEMENTS

Compensated (VDC = 20 V) Uncompensated

I1 (A) εr (%) 4ϕ (minutes) εr (%) 4ϕ (minutes)
4VXold = 19.28 V. The delay frequency is 25 kHz and based on 381 0.81 56.8 3.18 263.8
(10), ε is 5.03%. Through (8), for VXold /VXnew =0.25, α would 558 1.12 79.2 21.3 1283.4
be equal to 0.593. Therefore, VDC should be selected greater 771 0.60 63.4 36.8 1875.6
than 17.00 V as presented in (9); which is set to 20 V in the 912 0.57 32.6 49.7 2340.8
experiments. 1098 7.71 131.8 58.1 2628.2
Fig. 12 demonstrates schematic diagram of the implemented 1353 20.4 337.2 60.2 2806.6
test setup. A regulating transformer and a variable resistor 1398 22.9 354.0 63.1 2927.6
are employed to control the magnitude of the circuit current. 1569 29.7 476.8 74.1 3010.2
The illustrated diode would be inserted only in the transient
tests. A large 50:1 short-circuited power transformer is used
to generate high magnitude currents. A clamp-on ammeter the corresponding results for the uncompensated CT. Table I
and a typical commercial ammeter are used to monitor the reports the CT ratio error (εr ), and its phase displacement
RMS of CT primary and secondary currents during the steady- (4ϕ) ) when the CT is compensated (employing a VDC = 20
state experiments. In addition, a standard CT is inserted to the V) versus the uncompensated CT related parameters.
high current loop to record the primary current wave shape As it can be seen in Fig. 13, since the CT burden is 6 Ω and
during the transient analysis. A digital oscilloscope saves all the CT saturation voltage VXold is 4.82 V, the CT will begin to
the measured data to the in-site laptop. Based on IEC 60044-8 saturate in I2 of about 0.8 A (I1 = 240 A) without the proposed
[25], for a CT with 1 A secondary rated current and 1 VA rated compensator. It is worth mentioning that while the CT burden
power, the rated burden is 1 Ω. However, in this paper, in order is chosen significantly larger than its rated value (6 Ω instead
to investigate the performance of the proposed compensator of 1 Ω), the CT saturates even under its primary rated current
under high degree of the CT saturation, the under-test CT (I1 =300 A). However, with the proposed compensator, the ac
burden is selected to be 6 Ω (purely resistive). By increasing saturation of CT occurred at I1 equal to 1024 A and 1179 A
the CT burden, the required primary current to saturate the for VDC equal to 20 V and 28 V, respectively. For VDC = 40
CT has been proportionally decreased. The implemented test V, CT saturation would happen for a current more than the
circuit is capable of generating steady state sinusoidal currents maximum permissible current of the test setup (I1 = 1.6 kA).
up to 1.6 kA. The new obtained saturation voltages VXnew for VDC = [20 V,
24 V, 40 V] are equal to [4.267 VXold , 4.91 VXold , >6.25 VXold ].
The CT saturation voltage is successfully increased to 4VXold
A. Steady State Experiments by VDC equal to 20 V, as predicted through (9).
In these experiments, the injected primary current is sinu- The recorded CT secondary currents with and without the
soidal. The RMS value of CT primary and secondary currents proposed compensator are depicted in Fig. 14, when I1 is
are read using a clamp-on ammeter, and a regular ammeter, equal to 885 A. As it can be seen in Fig. 14(a), without
respectively, as shown in Fig. 12. The obtained input/output the compensator, CT becomes deeply saturated, while the
ratio curves are depicted in Fig. 13, when the dc voltage compensator prevents the CT core from saturation. Fig. 14(b)
source VDC is set to 20 V, 28 V and 40 V, respectively. represents the voltage across the CT burden vB and the
Please note that these voltage levels are not in compliance with compensator output voltage vCV S . As it can be seen, vCV S
IEC 60044-8 [25] and just have been selected to investigate is in phase with vB but with opposite polarity.
the compensator performance. In addition, Fig. 13 illustrates A 20 VDC voltage source can prevent the CT from satura-

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPWRD.2016.2580585, IEEE
Transactions on Power Delivery

6 20 V 28 V 40 V Uncompensated

5 1179 A
}
40 V 5

Current (A)
1024 A 28 V VDC
4 20 V 0
I2 (A)

3
-5
2 240 A
Uncomp. 10 20 30 40 50 60 70 80
1 Time (ms)
0
0 200 400 600 800 1000 1200 1400 1600 Fig. 15. Performance of the proposed compensator when VDC is selected
I1 (A) less than its proper value.

Fig. 13. Experimentally measured input/output ratio curves without and with 1) Regulating transformer
the proposed compensator when the CT burden is 6 Ω. 2) 50:1 single-phase power transformer
3) Under test and Standard CTs
4 (a) Ideal 4) The proposed compensator
Current (A)

2 Uncomp. 5) Digital oscilloscope

0 Comp. 6) A typical measured transient current
-2
-4
(b)
Voltage (V)

20

-20
0 20 40 60 80 100
0
Time (ms) Clamp
Under-Test CT
Fig. 14. a) The measured CT secondary current without (dash line) and with
(solid line) the proposed compensator, b) the recorded voltage across the CT
burden vB (t) (dash line) and the compensator output voltage vCV S (t) (solid
line).

old
tion up to 4Ial =1024 A. In Fig. 15, a 1360 A symmetrical ac
current is applied to the CT when the compensator dc voltage
source is set to 20, 28, and 40 V, respectively. As it can be
seen, 20 V and 28 V dc voltage sources cannot prevent CT
saturation. However, if it is compared with the uncompensated
CT, the depth of CT saturation is noticeably decreased. This
figure shows how the compensator prevents CT saturation up
to its boundaries, even with improper sizing of VDC .
B. Transient Experiments
In order to verify the performance of the proposed method
during a transient current injection, a diode is inserted into the
presented circuit in Fig. 12. Therefore, the CT primary current
would be a half-wave rectified waveform which is similar to
a typical inrush current. The regulating transformer is tuned
to obtain a primary current with maximum of 650 A. Fig.
16 depicts the test setup and a typical recorded signal. As
it can be seen, to achieve a higher current level, the high-
current capacity primary conductor has been wound in multi-
turns (four turns) around the CT under test.
Fig. 17(a) illustrates the measured currents at the secondary
terminals of both the standard and under-test CTs, without
the proposed compensation. As it can be seen, the under-test
CT experiences a very deep saturation. Fig. 17(b) depicts the
results of a same test when the under-test CT is compensated
with the proposed compensator. As it can be seen, the proposed
Standard CT
Fig. 16. Transient test setup and a typical recorded signal.
compensator prevents the CT deep saturation. However, the
effect of a very slight saturation can be seen on the CT
secondary current waveform which is due to overlooking the
inductance of the CT burden. Fig. 17(c) depicts the voltage
measured across the CT burden vB and the compensator
output voltage vCV S . Note that none of the known hardware-
based compensators can perform well in the presence of the
presented transient current. For example, since this current
does not have negative half-cycles, dynamically insertion of a
resistor [13], [19] could not help to suppress the CT saturation.
VI. C ONCLUSIONS
A hardware-based compensator using a controlled voltage
source has been introduced to prevent CT saturation. This
compensator cancels the voltage developed across the CT
burden and therefore, prevents the CT magnetic flux from
entering its saturation region. Some promising features of the
proposed compensation method are summarized as follows:

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPWRD.2016.2580585, IEEE
Transactions on Power Delivery

Current (A) 2 100 vB (t )

Voltage (V)
VDC
50
1
00
0 -50 vCT (t )  vB (t )  VDC
(a) VDC
-100
2
Current (A)

00  5 
10 
315 
220
1
2

 t (rad/s)
ωt rad
s  2

0
(b) Fig. A.1. The voltage across the CT terminal vCT (t) under ideal compen-
sation and steady-state ac current injection.
10
Voltage (V)

0 !
V
-10 θ = sin −1
√ DC (A.3)
(c) 2VXnew
-20
40 60 80 100 120 140 160 180 The CT magnetic flux associated with vCT can be eval-
Time (ms) uated by integration of (A.2). Here, the CT operates under
Fig. 17. a) The CT primary (solid line) and secondary (dash line) currents steady-state condition and due to voltage waveform symmetry
without the proposed compensator, b) CT primary (solid line) and secondary λ(2π) = λ(0). Therefore, the maximum CT magnetic flux
(dash line) currents with compensation, c) recorded vB (dash line) and vCV S λmax can be written as:
(solid line). VDC h π i
λmax = cot θ − + θ (A.4)
2πf 2
The ability to compensate current signal for both non-
• It is required to limit this magnetic flux to the CT saturation
digital and digital relays; flux λsat that can be calculated based on the real CT saturation
• The ability to compensate both in-service and newly voltage VXold through the following relation [26]:
installed CTs; V old
λsat = √ X (A.5)
• Eliminating the requirement for replacing the in-service 2πf
CTs with larger ones; Considering (A.4) with (A.5), one may conclude (A.6) in
• Preventing false operation of the protective relays due to order to avoid CT saturation:
π i √
CT saturation;
h
VDC cot θ − + θ ≤ 2VXold (A.6)
• Providing a simple theoretical control strategy with the 2
√ new
ability to compensate different possible current wave- Defining α = VDC /( 2VX ), (A.6) can be rewritten as
forms (fault current, inrush current, evolving fault, etc); follows: "√
• Low-cost hardware preserving a simple hardware struc-
#
1 − α2 π V old
ture, while having a set of appropriate design parameters. α − − sin−1 α ≤ X (A.7)
α 2 VXnew
The reliability and effectiveness of the proposed compen-
sator has been verified through a wide range of simulation 2) Selection of ∆Td : Assume that the compensator output
studies. The carried out experimental tests depicts the promis- voltage vCSV has a time delay equal to ∆Td corresponding
ing performance of the proposed device. to vB . In addition, vB has its maximum foreseen magnitude
as presented in
√(A.1). Here, the voltage across the CT is:
A PPENDIX vCT (t) = 2VXnew √ [sin (2πf t) − sin (2πf (t + ∆Td ))]
D ERIVATION OF T HE F ORMULAS FOR T HE PARAMETERS → vCT (t) = 2VXnew cos (2πf t) [2 sin (πf ∆Td )]
(A.8)
1) Magnitude of VDC : Assume that it is determined to Therefore, the CT magnetic flux can be calculated as:
increase the CT saturation voltage to VXnew . Therefore, the √ new
2VX sin (πf ∆Td )
maximum anticipated steady state voltage across the CT λεmax = (A.9)
πf
burden would be:
√ Considering λsat from (A.5), the error contributed by the
vB (t) = 2VXnew sin(2πf t) (A.1)
time delay ε can be calculated as follows:
Fig. A.1 depicts this voltage across the CT burden. Assume λε V new
ε = max = 2 Xold sin (πf ∆Td ) (A.10)
that the compensator dc voltage source is equal VDC . Ideally, λsat VX
the compensator output voltage vCSV can cancel vB while it is
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPWRD.2016.2580585, IEEE
Transactions on Power Delivery

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