32lv3550-Zb Chassis Ld01u

Internal Use Only
North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
LED LCD TV
SERVICE MANUAL
CHASSIS : LD01U
MODEL: 32LV3500/3551
MODEL: 32LV3500-ZA/32LV3551-ZD
MODEL: 32LV3550/355A/355C/355N/355U
MODEL: 32LV3550/355A/355C/355N/355U-ZB
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL62863056 (1102-REV00) Printed in Korea

CONTENTS
CONTENTS .............................................................................................. 2
PRODUCT SAFETY ................................................................................. 3
SPECIFICATION ....................................................................................... 6
ADJUSTMENT INSTRUCTION ................................................................ 9
BLOCK DIAGRAM...................................................................................15
EXPLODED VIEW .................................................................................. 16
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright ©2011 LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer, AC Volt-meter
always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical Good Earth Ground
shock. such as WATER PIPE,
To Instrument’s CONDUIT etc.
0.15 uF
Leakage Current Cold Check(Antenna Cold Check) exposed
With the instrument AC plug removed from AC source, connect an METALLIC PARTS
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC 1.5 Kohm/10W
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc. When 25A is impressed between Earth and 2nd Ground
If the exposed metallic part has a return path to the chassis, the for 1 second, Resistance must be less than 0.1 Ω
measured resistance should be between 1 MΩ and 5.2 MΩ.
*Base on Adjustment standard
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or
NOTE: If unforeseen circumstances create conflict between the exposure of the assembly.
following servicing precautions and any of the safety precautions on 3. Use only a grounded-tip soldering iron to solder or unsolder ES
page 3 of this publication, always follow the safety precautions. devices.
Remember: Safety First. 4. Use only an anti-static type solder removal device. Some solder
removal devices not classified as "anti-static" can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board 6. Do not remove a replacement ES device from its protective
module or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug or (Most replacement ES devices are packaged with leads
other electrical connection. electrically shorted together by conductive foam, aluminum foil
c. Connecting a test substitute in parallel with an electrolytic or comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective material
installation of electrolytic capacitors may result in an to the chassis or circuit assembly into which the device will be
explosion hazard. installed.
CAUTION: Be sure no power is applied to the chassis or circuit,
2. Test high voltage only by measuring it with an appropriate high and observe all other safety precautions.
voltage meter or other voltage measuring device (DVM, 8. Minimize bodily motions when handling unpackaged
FETVOM, etc) equipped with a suitable high voltage probe. replacement ES devices. (Otherwise harmless motion such as
Do not test high voltage by "drawing an arc". the brushing together of your clothes fabric or the lifting of your
3. Do not spray chemicals on or near this receiver or any of its foot from a carpeted floor can generate static electricity
assemblies. sufficient to damage an ES device.)
4. Unless specified otherwise in this service manual, clean
electrical contacts only by applying the following mixture to the General Soldering Guidelines
contacts with a pipe cleaner, cotton-tipped stick or comparable 1. Use a grounded-tip, low-wattage soldering iron and appropriate
non-abrasive applicator; 10 % (by volume) Acetone and 90 % tip size and shape that will maintain tip temperature within the
(by volume) isopropyl alcohol (90 % - 99 % strength) range or 500 °F to 600 °F.
CAUTION: This is a flammable mixture. 2. Use an appropriate gauge of RMA resin-core solder composed
Unless specified otherwise in this service manual, lubrication of of 60 parts tin/40 parts lead.
contacts in not required. 3. Keep the soldering iron tip clean and well tinned.
5. Do not defeat any plug/socket B+ voltage interlocks with which 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
receivers covered by this service manual might be equipped. bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
6. Do not apply AC power to this instrument and/or any of its Do not use freon-propelled spray-on cleaners.
electrical assemblies unless all solid-state device heat sinks are 5. Use the following unsoldering technique
correctly installed. a. Allow the soldering iron tip to reach normal temperature.
7. Always connect the test receiver ground lead to the receiver (500 °F to 600 °F)
chassis ground before connecting the test receiver positive b. Heat the component lead until the solder melts.
lead. c. Quickly draw the melted solder with an anti-static, suction-
Always remove the test receiver ground lead last. type solder removal device or with solder braid.
8. Use with this receiver only the test fixtures specified in this CAUTION: Work quickly to avoid overheating the circuit
service manual. board printed foil.
CAUTION: Do not connect the test fixture ground strap to any 6. Use the following soldering technique.
heat sink in this receiver. a. Allow the soldering iron tip to reach a normal temperature
(500 °F to 600 °F)
Electrostatically Sensitive (ES) Devices b. First, hold the soldering iron tip and solder the strand against
Some semiconductor (solid-state) devices can be damaged easily the component lead until the solder melts.
by static electricity. Such components commonly are called c. Quickly move the soldering iron tip to the junction of the
Electrostatically Sensitive (ES) Devices. Examples of typical ES component lead and the printed circuit foil, and hold it there
devices are integrated circuits and some field-effect transistors and only until the solder flows onto and around both the
semiconductor "chip" components. The following techniques component lead and the foil.
should be used to help reduce the incidence of component CAUTION: Work quickly to avoid overheating the circuit
damage caused by static by static electricity. board printed foil.
1. Immediately before handling any semiconductor component or d. Closely inspect the solder area and remove any excess or
semiconductor-equipped assembly, drain off any electrostatic splashed solder with a small wire-bristle brush.
charge on your body by touching a known earth ground.
Alternatively, obtain and wear a commercially available
discharging wrist strap device, which should be removed to
prevent potential shock reasons prior to applying power to the
unit under test.
IC Remove/Replacement Circuit Board Foil Repair
Some chassis circuit boards have slotted holes (oblong) through Excessive heat applied to the copper foil of any printed circuit
which the IC leads are inserted and then bent flat against the board will weaken the adhesive that bonds the foil to the circuit
circuit foil. When holes are the slotted type, the following technique board causing the foil to separate from or "lift-off" the board. The
should be used to remove and replace the IC. When working with following guidelines and procedures should be followed whenever
boards using the familiar round hole, use the standard technique this condition is encountered.
as outlined in paragraphs 5 and 6 above.
At IC Connections
Removal To repair a defective copper pattern at IC connections use the
1. Desolder and straighten each IC lead in one operation by gently following procedure to install a jumper wire on the copper pattern
prying up on the lead with the soldering iron tip as the solder side of the circuit board. (Use this technique only on IC
melts. connections).
2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing the 1. Carefully remove the damaged copper pattern with a sharp
IC. knife. (Remove only as much copper as absolutely necessary).
Replacement 2. carefully scratch away the solder resist and acrylic coating (if
1. Carefully insert the replacement IC in the circuit board. used) from the end of the remaining copper pattern.
2. Carefully bend each IC lead against the circuit foil pad and 3. Bend a small "U" in one end of a small gauge jumper wire and
solder it. carefully crimp it around the IC pin. Solder the IC connection.
3. Clean the soldered areas with a small wire-bristle brush. 4. Route the jumper wire along the path of the out-away copper
(It is not necessary to reapply acrylic coating to the areas). pattern and let it overlap the previously scraped end of the good
copper pattern. Solder the overlapped area and clip off any
"Small-Signal" Discrete Transistor excess jumper wire.
Removal/Replacement
1. Remove the defective transistor by clipping its leads as close as At Other Connections
possible to the component body. Use the following technique to repair the defective copper pattern
2. Bend into a "U" shape the end of each of three leads remaining at connections other than IC Pins. This technique involves the
on the circuit board. installation of a jumper wire on the component side of the circuit
3. Bend into a "U" shape the replacement transistor leads. board.
4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with 1. Remove the defective copper pattern with a sharp knife.
long nose pliers to insure metal to metal contact then solder Remove at least 1/4 inch of copper, to ensure that a hazardous
each connection. condition will not exist if the jumper wire opens.
2. Trace along the copper pattern from both sides of the pattern
Power Output, Transistor Device break and locate the nearest component that is directly
Removal/Replacement connected to the affected copper pattern.
1. Heat and remove all solder from around the transistor leads. 3. Connect insulated 20-gauge jumper wire from the lead of the
2. Remove the heat sink mounting screw (if so equipped). nearest component on one side of the pattern break to the lead
3. Carefully remove the transistor from the heat sink of the circuit of the nearest component on the other side.
board. Carefully crimp and solder the connections.
4. Insert new transistor in the circuit board. CAUTION: Be sure the insulated jumper wire is dressed so the
5. Solder each transistor lead, and clip off excess lead. it does not touch components or sharp edges.
6. Replace heat sink.
Diode Removal/Replacement
1. Remove defective diode by clipping its leads as close as
possible to diode body.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range 3. Test method

This specification is applied to the LCD/ LED LCD TV used 1) Performance: LGE TV test method followed
LD01U chassis. 2) Demanded other specification
- Safety: CE, IEC specification
2. Requirement for Test - EMC:CE, IEC
Each part is tested as below without special appointment.
1) Temperature
: 25 ºC ± 5 ºC (77 ºF ± 9 ºF), CST : 40 ºC ± 5 ºC
2) Relative Humidity : 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~ 50 / 60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.
4. Model General Specification

No. Item Specification Remarks
1 Market EU(PAL Market-36Countries) DTV-T/C & Analog
(Germany, Netherlands, Switzerland, Hungary, Austria, Slovenia, Sweden, Denmark,
Finland, Norway, Bulgaria
DTV-T & Analog
UK, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece, Czech, Croatia,Turkey,
Moroco, Ireland, Latvia, Estonia, Lithania, Poland, Portugal, Romania, Ukraine
Analog Only
Kazakhstan, Albania, Bosnia, Serbia, Slovakia
2 Broadcasting system 1) PAL-BG
2) PAL-DK
3) PAL-I/I’
4) SECAM L/L’
5) DVB-T/C/S (ID TV)
3 Receiving system Analog : Upper Heterodyne
Digital : COFDM, QAM
4 Scart Jack (1EA) PAL, SECAM Scart Jack is Full scart and support RF-OUT(analog & DTV)
5 Video Input RCA(1EA) PAL, SECAM, NTSC 4System : PAL, SECAM, NTSC, PAL60
6 Component Input(1EA) Y/Cb/Cr, Y/Pb/Pr
7 RGB Input RGB-PC Analog(D-SUB 15PIN)
8 HDMI Input (3EA) HDMI1-DTV (DVI) PC(HDMI version 1.3)
HDMI2-DTV Support HDCP
HDMI3-DTV
9 Audio Input (3EA) RGB/DVI Audio, Component, AV L/R Input
10 SDPIF out (1EA) SPDIF out
11 Earphone out (1EA) Antenna, AV1, AV2, AV3, Component,
RGB, HDMI1, HDMI2, HDMI3, HDMI4
12 USB (1EA) For SVC (download)
DivX
13 DVB DVB-T CI : UK, Finland, Denmark, Norway, Sweden, Russia, Spain, Ireland, Luxemburg, Belgium, Netherland
CI+ : France(Canal+), Italy(DGTVi)
DVB-C CI : Switzerland, Austria, Slovenia, Hungary, Bulgaria
CI+ : Switzerland(UPC,Cablecom), Netherland(Ziggo), Germany(KDG,CWB), Finland(labwise)
DVB-S CI+ : Germany(Astra HD+)
6. Component Video Input (Y, CB/PB, CR/PR)
Specification
No. Remark
Resolution H-freq(kHz) V-freq(Hz)
1. 720x480 15.73 60.00 SDTV,DVD 480i
2. 720x480 15.63 59.94 SDTV,DVD 480i
3. 720x480 31.47 59.94 480p
4. 720x480 31.50 60.00 480p
5. 720x576 15.625 50.00 SDTV,DVD 625 Line
6. 720x576 31.25 50.00 HDTV 576p
7. 1280x720 45.00 50.00 HDTV 720p
8. 1280x720 44.96 59.94 HDTV 720p
9. 1280x720 45.00 60.00 HDTV 720p
10. 1920x1080 31.25 50.00 HDTV 1080i
11. 1920x1080 33.75 60.00 HDTV 1080i
12. 1920x1080 33.72 59.94 HDTV 1080i
13. 1920x1080 56.250 50 HDTV 1080p
14. 1920x1080 67.5 60 HDTV 1080p
7. RGB (PC)
Specification
No. Proposed Remark
Resolution H-freq(kHz) V-freq(Hz) Pixel Clock(MHz)
1. 720*400 31.468 70.08 28.321 For only DOS mode
2. 640*480 31.469 59.94 25.17 VESA Input 848*480 60 Hz, 852*480 60 Hz
-> 640*480 60 Hz Display
3. 800*600 37.879 60.31 40.00 VESA
4. 1024*768 48.363 60.00 65.00 VESA(XGA)
5. 1280*768 47.78 59.87 79.5 WXGA
6. 1360*768 47.72 59.8 84.75 WXGA FHD Model
7. 1366*768 47.56 59.6 84.75 WXGA WXGA Model
8. 1200*1024 63.901 60.02 100.075 SXGA FHD model
9. 1280*720 45 60 74.25 720p DTV Standard
10. 1920*1080 67.5 60 148.5 WUXGA FHD model
8. HDMI Input
(1) DTV Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*480 31.469/31.5 59.94/60 27.00/27.03 SDTV 480P
2. 720*576 31.25 50 54 SDTV 576P
3. 1280*720 37.500 50 74.25 HDTV 720P
4. 1280*720 44.96/45 59.94/60 74.17/74.25 HDTV 720P
5. 1920*1080 33.72/33.75 59.94/60 74.17/74.25 HDTV 1080I
6. 1920*1080 28.125 50.00 74.25 HDTV 1080I
7. 1920*1080 26.97/27 23.97/24 74.17/74.25 HDTV 1080P
8. 1920*1080 33.716/33.75 29.976 /30.00 74.25 HDTV 1080P
9. 1920*1080 56.250 50 148.5 HDTV 1080P
10. 1920*1080 67.43/67.5 59.94/60 148.35/148.50 HDTV 1080P
(2) PC Mode
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
1. 720*400 31.468 70.08 28.321 HDCP
2. 640*480 31.469 59.94 25.17 VESA HDCP
3. 800*600 37.879 60.31 40.00 VESA HDCP
4. 1024*768 48.363 60.00 65.00 VESA(XGA) HDCP
5. 1280*768 47.78 59.87 79.5 WXGA HDCP
6. 1360*768 47.72 59.8 84.75 WXGA HDCP
7. 1280*720 45 60 74.25 HDCP
8. 1280*1024 63.981 60.02 108.875 SXGA HDCP/FHD model
9. 1920*1080 67.5 60 148.5 WUXGA HDCP/FHD model
ADJUSTMENT INSTRUCTION
1. Application Range (2) (3)
This specification sheet is applied to all of the LCD/ LED LCD
TV with LD01U chassis.
2. Designation
1) The adjustment is according to the order which is
designated and which must be followed, according to the Please Check the Speed :
To use speed between
plan which can be changed only on agreeing. from 200KHz to 400KHz
2) Power Adjustment: Free Voltage
3) Magnetic Field Condition: Nil.
5) Click “Auto” tab and set as below
4) Input signal Unit: Product Specification Standard
6) Click “Run”.
5) Reserve after operation: Above 5 Minutes (Heat Run)
7) After downloading, check “OK” message.
Temperature : at 25 ºC ± 5 ºC
Relative humidity : 65 % ± 10 % (4)
Input voltage : 220 V, 60 Hz
filexxx.bin
6) Adjustment equipments: Color Analyzer(CA-210 or CA-110), (5)
DDC Adjustment Jig equipment, Service remote control.
(7) .OK
7) Push The “IN STOP” key - For memory initialization.
Case1 : Software version up (6)
1. After downloading S/W by USB, TV set will reboot

automatically
2. Push “In-stop” key
3. Push “Power on” key * USB DOWNLOAD
4. Function inspection 1) Put the USB Stick to the USB socket
5. After function inspection, Push “In-stop” key. 2) Automatically detecting update file in USB Stick
Case2 : Function check at the assembly line - If your downloaded program version in USB Stick is Low,
1. When TV set is entering on the assembly line, Push it didn’t work. But your downloaded version is High, USB
“In-stop” key at first. data is automatically detecting
2. Push “Power on” key for turning it on. 3) Show the message “Copying files from memory”
-> If you push “Power on” key, TV set will recover
channel information by itself.
3. After function inspection, Push “In-stop” key.
3. Main PCB check process

* APC - After Manual-Insult, executing APC
* Boot file Download

1) Execute ISP program “Mstar ISP Utility” and then click
“Config” tab.
(1)
fi lexxx.bin
2) Set as below, and then click “Auto Detect” and check “OK”
message
If “Error” is displayed, Check connection between
computer, jig, and set.
3) Click “Read” tab, and then load download file (XXXX.bin)
by clicking “Read”
4) Click “Connect” tab. If “Can’t” is displayed, check
connection between computer, jig, and set.
4) Updating is staring. 3.1. ADC Process
(1) ADC
- Enter Service Mode by pushing “ADJ” key,
- Enter Internal ADC mode by pushing “G” key at “5. ADC
Calibration”
EZ ADJUT
0. Tool Option1 ADC Calibration
1. Tool Option2
2. Tool Option3
3. Tool Option4 ADC Comp 480i NG
4. Country Group
5. ADC Calibration ADC Comp 1080p NG
6. White Balance
7. Test Pattern ADC RGB NG
8. EDID D/L
9. Sub B/C
10. V-Com Start Reset
11. P-Gamma
<Caution> Using ‘power on’ button of the Adjustment R/C,

power on TV.
* ADC Calibration Protocol (RS232)
Adjust Sequence
• aa 00 00 [Enter Adjust Mode]
Item CMD1 CMD2 Data0
Adjust ‘Mode In’ A A 0 0 When transfer the ‘Mode In’,
Carry the command.
ADC Adjust A D 1 0 Automatically adjustment
(The use of a internal pattern)
• xb 00 40 [Component1 Input (480i)]

• ad 00 10 [Adjust 480i Comp1]
• xb 00 60 [RGB Input (1024*768)]
• ad 00 10 [Adjust 1024*768 RGB]
5) Uploading completed, The TV will restart automatically.
• aa 00 90 End Adjust mode
6) If your TV is turned on, check your updated version and
* Required equipment : Adjustment R/C.
Tool option.(explain the Tool option, next stage)
* If downloading version is more high than your TV have,
TV can lost all channel data. In this case, you have to 3.2. Function Check
channel recover. if all channel data is cleared, you didn’t * Check display and sound
have a DTV/ATV test on production line. - Check Input and Signal items. (cf. work instructions)
1) TV
* After downloading, have to adjust Tool Option again. 2) AV (SCART1/SCART2/CVBS)
1) Push "IN-START" key in service remote controller 3) COMPONENT (480i)
2) Select “Tool Option 1” and Push “OK” button. 4) RGB (PC : 1024 x 768 @ 60 Hz)
3) Punch in the number. (Each model has their number) 5) HDMI
6) PC Audio In
Module Tool option1 Tool option2 Tool option3 Tool option4 Tool optin5
* Display and Sound check is executed by Remote control.
AUO 18280 18986 55337 26904 352
CIM 18276 18986 55337 26904 352
4) Completed selecting Tool option.
Copyright ©2011 LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
4. Total Assembly line process • Auto adjustment Map(RS-232C)
RS-232C COMMAND
4.1. Adjustment Preparation [CMD ID DATA]
· W/B Equipment condition Wb 00 00 White Balance Start
CA210 Wb 00 ff White Balance End
: CCFL/EEFL -> CH9, Test signal: Inner pattern(80IRE) RS-232C COMMAND MIN CENTER MAX
LED -> CH14, Test signal: Inner pattern(80IRE)
· Above 5 minutes H/run in the inner pattern. (“power on” key [CMD ID DATA] (DEFAULT)
of adjust remote control) Cool Mid Warm Cool Mid Warm
Cool 13,000 K X=0.269(±0.002) R Gain jg Ja jd 00 172 192 192 192
Y=0.273(±0.002) <Test Signal> G Gain jh Jb je 00 172 192 192 192
Medium 9,300 K X=0.285(±0.002) Inner pattern B Gain ji Jc jf 00 192 192 172 192
Y=0.293(±0.002) (204 gray, 80 IRE) R Cut 64 64 64 128
Warm 6,500 K X=0.313(±0.002) G Cut 64 64 64 128
Y=0.329(±0.002) B Cut 64 64 64 128
· Edge LED W/B Table is process of time (Only LGD Module) ** Caution **
CA210: CH14, Test signal : Inner pattern(80IRE) Color Temperature : COOL, Medium, Warm.
Aging Time Cool Medium Warm
One of R Gain/G Gain/ B Gain should be kept on 0xC0, and
adjust other two lower than C0.
GP2R (Min.) X Y X Y X Y
(when R/G/B Gain are all C0, it is the FULL Dynamic Range
269 273 285 293 313 329 of Module)
1 0-2 279 288 295 308 319 338
2 3-5 278 286 294 306 318 336 * Manual W/B process using adjusts Remote control.
3 6-9 277 285 293 305 317 335 • After enter Service Mode by pushing “ADJ” key,
4 10-19 276 283 292 303 316 333 • Enter White Balance by pushing “ G ” key at “6. White
5 20-35 274 280 290 300 314 330
Balance”.
6 36-49 272 277 288 297 312 327 EZ ADJUST
0. Tool Option1
7 50-79 271 275 287 295 311 325 1. Tool Option2
8 80-149 270 274 286 294 310 324 2. Tool Option3 White Balance
3. Tool Option4
Color Temp. Cool
4. Country Group
9 Over 150 269 273 285 293 309 323 5. ADC Calibration R-Gain 172
6. White Balance G-Gain 172
7. Test Pattern B-Gain 192
8. EDID D/L R-Cut 64
* Connecting picture of the measuring instrument 9. Sub B/C G-Cut
B-Cut
64
10. V-Com 64
(On Automatic control) 11. P-Gamma Test-Pattern. ON
Reset To set
Inside PATTERN is used when W/B is controlled. Connect to
auto controller or push Adjustment R/C POWER ON ->
Enter the mode of White-Balance, the pattern will come out. * After you finished all adjustments, Press “In-start” key and
compare Tool option and Area option value with its BOM, if
it is correctly same then unplug the AC cable. If it is not
same, then correct it same with BOM and unplug AC cable.
Full White Pattern CA-210
For correct it to the model’s module from factory Jig model.
COLOR * Push the “IN STOP” key after completing the function
ANALYZER
TYPE: CA-210 inspection. And Mechanical Power Switch must be set
“ON”.
RS-232C Communication 4.2. DDC EDID Write (RGB 128Byte )

• Connect D-sub Signal Cable to D-sub Jack.
* Auto-control interface and directions • Write EDID Data to EEPROM(24C02) by using DDC2B
1) Adjust in the place where the influx of light like floodlight protocol.
around is blocked. (illumination is less than 10 lux). • Check whether written EDID data is correct or not.
2) Adhere closely the Color Analyzer (CA210) to the module * For SVC main Assembly, EDID have to be downloaded to
less than 10 cm distance, keep it with the surface of the Insert Process in advance.
Module and Color Analyzer’s prove vertically.(80° ~ 100°).
3) Aging time 4.3. DDC EDID Write (HDMI 256Byte)
- After aging start, keep the power on (no suspension of • Connect HDMI Signal Cable to HDMI Jack.
power supply) and heat-run over 5 minutes. • Write EDID Data to EEPROM(24C02) by using DDC2B
- Using ‘no signal’ or ‘full white pattern’ or the others, protocol.
check the back light on. • Check whether written EDID data is correct or not.
* For SVC main Assembly, EDID have to be downloaded to
Insert Process in advance.
4.4. EDID DATA 1) FHD RGB EDID data
1) All Data : HEXA Value 0 1 2 3 4 5 6 7 8 9 A B C D E F
2) Changeable Data : 00 00 FF FF FF FF FF FF 00 1E 6D a b
*: Serial No : Controlled / Data:01 10 c 01 03 68 10 09 78 0A EE 91 A3 54 4C 99 26
**: Month : Controlled / Data:00 20 0F 50 54 A1 08 00 81 80 61 40 45 40 31 40 01 01
***:Year : Controlled 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
****:Check sum 40 45 00 A0 5A 00 00 00 1E 01 1D 00 72 51 D0 1E 20
50 6E 28 55 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 d
- Auto Download 70 d 00 e
• After enter Service Mode by pushing “ADJ” key, 80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
• Enter EDID D/L mode. 90 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
• Enter “START” by pushing “OK” key. A0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
B0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
EZ ADJUT EDID D/L
C0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0. Tool Option1 HDMI1 NG D0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
1. Tool Option2 HDMI2 NG E0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
2. Tool Option3 HDMI3 NG
F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
3. Tool Option4 RGB NG
4. Country Group
5. ADC Calibration Start Reset 2) FHD HDMI EDID data
6. White Balance
7. Test Pattern 0 1 2 3 4 5 6 7 8 9 A B C D E F
8. EDID D/L EDID D/L
00 FF FF FF FF FF FF 00 1E 6D a b
9. Sub B/C
HDMI1 OK 10 c 01 03 80 10 09 78 0A EE 91 A3 54 4C 99 26
10. V-Com
11. P-Gamma HDMI2 OK 20 0F 50 54 A1 08 00 71 4F 81 80 01 01 01 01 01 01
HDMI3 OK
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
RGB OK
40 45 00 A0 5A 00 00 00 1E 1B 21 50 A0 51 00 1E 30
Start Reset 50 48 88 35 00 A0 5A 00 00 00 1C 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 d
* Caution : Never connect HDMI & D-sub Cable when EDID 70 d 01 e
download 80 02 03 26 F1 4E 10 1F 84 13 05 14 03 02 12 20 21
90 22 15 01 26 15 07 50 09 57 07 f
A0 f E3 05 03 01 01 1D 80 18 71 1C 16 20 58 2C
* Edid data and Model option download (RS232) B0 25 00 A0 5A 00 00 00 9E 01 1D 00 72 51 D0 1E 20
C0 6E 28 55 00 A0 5A 00 00 00 1E 02 3A 80 18 71 38
Item CMD1 CMD2 Data0
D0 2D 40 58 2C 45 00 A0 5A 00 00 00 1E 01 1D 00 BC
Download A A 0 0 When transfer the ‘Mode In’, E0 52 D0 1E 20 B8 28 55 40 A0 5A 00 00 00 1E 00 00
‘Mode In’ Carry the command. F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e
Download A E 00 10 Automatically Download

* Detail EDID Options are below
(The use of a internal pattern) ⓐ Product ID
Model Name HEX EDID Table DDC Function
- Manual Download FHD Model 0001 01 00 Analog/Digital
* Caution
1) Use the proper signal cable for EDID Download. ⓑ Serial No: Controlled on production line.
- Analog EDID : Pin3 exists
ⓒ Month, Year: Week : ‘01’ -> ‘01’
- Digital EDID : Pin3 exists
2) Never connect HDMI & D-sub Cable at the same time. Year : ‘2011’ -> ‘15’ fix
3) Use the proper cables below for EDID Writing. ⓓ Model Name(Hex):
4) Download HDMI1, HDMI2, separately because HDMI1 is MODEL MODEL NAME(HEX)
different from HDMI2.
all 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20
For Analog EDID For HDMI EDID
D-sub to D-sub DVI-D to HDMI or HDMI to HDMI ⓔ Checksum: Changeable by total EDID data.
ⓕ Vendor Specific(HDMI)
INPUT MODEL NAME(HEX)
HDMI1 67030C001000B82D
HDMI2 67030C002000B82D
HDMI3 67030C003000B82D
Item Condition Data(Hex) HDMI4 67030C004000B82D
Manufacturer ID GSM 1E6D
Version Digital : 1 01
Revision Digital : 3 03
4.5. V-COM Adjust(Only LGD(M+S) Module) 5. Model name & Serial number D/L
- Why need Vcom adjustment? • Press “Power on” key of service remocon.
A The Vcom (Common Voltage) is a Reference Voltage of (Baud rate : 115200 bps)
Liquid Crystal Driving. • Connect RS232 Signal Cable to RS-232 Jack.
-> Liquid Crystal need for Polarity Change with every frame. • Write Serial number by use RS-232.
Circuit Block • Must check the serial number at the Diagnostics of SET UP
Data (R ,G,B ) & Ga mma menu. (Refer to below).
Con t rol si gnal Re f e r e nce V o ltage
Data (R ,G,B ) & C ont ro l s ignal
Ti m i n g
S Co nt r o ll e r
Gamm a Reference
In t e r f a ce
Cont rol si gnal Volta ge

Y Da t a I n p u t
So urce D r i v e I C
S
T Column Line
Pane l
Gat e Driv e IC
E Power
Po w e rInput
I nput Po w e r V COM
Blo ck
M CLC CST
Liquid
Crys tal
V COM Row Li ne TFT
V COM
5.1. Signal TABLE
CMD LENGTH ADH ADL DATA_1 ... Data_n CS DELAY
- Adjust sequence CMD : A0h

· Press the PIP key of th ADJ remote control.(This PIP key is LENGTH : 85~94h (1~16 bytes)
hot key to enter the VCOM adjuting mode) ADH : EEPROM Sub Address high (00~1F)
(Or After enter Service Mode by pushing “ADJ” key, then ADL : EEPROM Sub Address low (00~FF)
Data : Write data
Enter V-Com Adjust mode by pushing “G” key at “10. V-
CS : CMD + LENGTH + ADH + ADL + Data_1 +…+ Data_n
Com”.)
Delay : 20ms
· As pushing the right or the left key on the remote control,
and find the V-COM value which is no or minimized the
Flicker. (If there is no flicker at default value, Press the exit 5.2. Command Set
key and finish the VCOM adjustment.) No. Adjust mode CMD(hex) LENGTH(hex) Description
· Push the “OK” key to store value. Then the message “Saing
1 EEPROM WRITE A0h 84h+n n-bytes Write(n=1~16)
OK” is pop.
· Press the exit key to finish VCOM adjustment.
* Description
FOS Default write : <7mode data> write
Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart, 0,
Phase
Data write : Model Name and Serial Number write in
EEPROM,.
(Visual Adjust and control the Voltage level) 5.3. Method & notice
A. Serial number D/L is using of scan equipment.
4.6. Outgoing condition Configuration B. Setting of scan equipment operated by Manufacturing
- When pressing IN-STOP key by SVC remocon, Red LED are Technology Group.
blinked alternatively. And then Automatically turn off. C. Serial number D/L must be conformed when it is produced
(Must not AC power OFF during blinking) in production line, because serial number D/L is mandatory
by D-book 4.0.
4.7. Hi-pot Test
Confirm whether is normal or not when between power
board’s ac block and GND is impacted on 1.5 kV(dc) or 2.2
kV(dc) for one second.
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or Service man, Sometimes
model name or serial number is initialized.(Not always)
There is impossible to download by bar code scan, so It need
Manual download.
1) Press the ‘instart’ key of ADJ remote controller.
2) Go to the menu ‘5.Model Number D/L’ like below photo.
3) Input the Factory model name(ex 42LD450-ZA) or Serial
=> Check the Download to CI+ Key value in LGset.

1. check the method of CI+ Key value
a. check the method on Instart menu
number like photo. b. check the method of RS232C Command
1) into the main ass’y mode (RS232 : aa 00 00)
4) Check the model name Instart menu -> Factory name CMD 1 CMD 2 Data 0
displayed (ex 42LD450-ZA)
5) Check the Diagnostics (DTV country only) -> Buyer model A A 0 0
2) check the key download for transmitted command

(RS232 : ci 00 10)
CMD 1 CMD 2 Data 0
C I 1 0
3) result value
- normally status for download : OKx
- abnormally status for download : NGx
2. Check the method of CI+ Key value (RS232)

1) into the main ass’y mode (RS232 : aa 00 00)
CMD 1 CMD 2 Data 0
A A 0 0
2) Check the method of CI+ key by command (RS232 :

ci 00 20)
CMD 1 CMD 2 Data 0
displayed (ex 42LD450)
C I 2 0
3) Result value
6. CI+ Key Download method i 01 OK 1d1852d21c1ed5dcx
(1) Download Procedure
CI+ key Value
1) Press "Power on" button of a service remote control.
(Baud rate : 115200 bps)
2) Connect RS232-C Signal Cable.
3) Write CI+ Key through RS-232-C.
4) Check whether the key was downloaded or not at ‘In 7. Local Dimming Function Check
Start’ menu. (Refer to below). Step1) Turn on TV.
Step2) Press “P-only” key, entrance to power only mode and
Press “Exit” key
Step3) Press “Tilt” key, entrance to Local Dimming mode.
Step4) At the Local Dimming mode, module Edge Backlight
moving right to left Back light of module moving
Step5) confirm the Local Dimming mode
Step6) Press “Exit” key
DATA
Video
Audio
Tuner_SI F 41P
Tuner_CVBS 51P
TUNER
SCL/ SDA
( T/ C) 30P
FE_TS_DATA[ 0] / CLK/ Valid/ Sync

SYSTEM
CI _TS_DATA[ 7: 0] / CLK/ Valid/ Sync DDR3 X 16 X 1
( 1Gb)
CI _DATA[ 7:0]
CI _ADDR[ 14:0] SPI
PCMCIA
Flash( 2Mb)
Copyright ©2011 LG Electronics. Inc. All rights reserved.

USB_DM/ DP For FRC
USB
HP_OUT
H/ P SYSTEM
DDR3 X 16 X 2
HDMI _TMDS/ HPD/ CEC ( 2Gb)
HDMI 3
Side LGE101 (S7R)
- 15 -
SPI
LGE107 (S7+URSA) Flash( 8Mb)
HDMI _TMDS/ HPD/ CEC
HDMI 1
NAND
HDMI _TMDS/ HPD/ CEC
HDMI 2 Flash( 8Gb)
COMP_ YPbPr/ LR_I N
COMP1
BLOCK DIAGRAM
AV_CVBS/ LR_I N SCL/ SDA SYSTEM EEPROM X 1

A/V1 ( 1Mb)
DSUB_RGB/ HVsync
PC- RGB SCL/ SDA
DDC_SDA/ UART_TX HDCP EEPROM X 1
PC_ Audio I N
( 8Kb)
PC- AUDI O
SPDI F SPDI F_OUT Sub Micom

( NEC)
SC_CVBS/ RGB/ LR_I N
SCART SC_VI DEO/ LR_OUT
I 2S_I / F
Audio
SCL/ SDA
Debug _TX/ RX AMP
Rear RS-232C
LGE Internal Use Only

EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
710
400
910
900
521
540
810
LV1
530
* Stand Base + Body

* Set + Stand
A10
200
A5
A2
A21
120
511
300
510
Copyright LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only
IC102
NAND FLASH MEMORY +3.3V_Normal

NAND01GW3B2CN6E
+3.3V_Normal
S7M-PLUS_DivX_MS10
LGE107DC-RP [S7M+ DIVX/MS10]
NC_1 NC_29
1 48
/PF_CE0 NAND_FLASH_1G_NUMONYX
H : Serial Flash NC_2
2 EAN60762401 47
NC_28 IC101
L : NAND Flash PCM_A[0-7] PCM_D[0-7]
/PF_CE1 NC_3 NC_27
3 46
H : 16 bit
NC_4 NC_26 <T3 CHIP Config(AUD_LRCH)>
3.9K
1K
L : 8 bit 4 45 AR101 Boot from SPI flash : 1’b0 PCM_D[0] U22 N21
NC_5 I/O7 PCM_A[7]
Boot from NOR flash : 1’b1 PCM_D0 GPIO143/TCON0 5V_DET_HDMI_1
5 44 PCM_D[1] T21 M21
PCM_D1 GPIO145/TCON2 5V_DET_HDMI_2
NC_6 I/O6 PCM_A[6] PCM_D[2] T22 L22
R109
6 43
R107
PCM_D2 GPIO147/TCON4 5V_DET_HDMI_4

PCM_D[3] AB18 L21
RB I/O5 PCM_A[5] PCM_D3 GPIO149/TCON6
/F_RB 7 42 PCM_D[4] AC18 P21
PCM_D4 GPIO151/TCON8 SIDEAV_DET
R
8 41
I/O4 PCM_A[4] <T3 CHIP Config> PCM_D[5] AC19
/PF_OE PCM_D5
E NC_25 22 (AUD_SCK, AUD_MASTER_CLK, PWM1, PWM0) PCM_D[6] AC20
9 40 PCM_D6
/PF_CE0 PCM_A[0-14] PCM_D[7] AC21 K21 M_REMOTE_RX
NC_7 NC_24 MIPS_no_EJ_NOR8 : 4’h3 (MIPS as host. No EJ PAD. Byte mode NAND flash.) PCM_D7 GPIO36/UART3_RX 3D SG
L23 M_REMOTE_TX
R108 1K
10 39 MIPS_EJ1_NOR8 : 4’h4 (MIPS as host. EJ use PAD1. Byte mode NAND flash.) GPIO37/UART3_TX 3D SG
C102 PCM_A[0] U21 K20
MIPS_EJ2_NOR8 : 4’h5 (MIPS as host. EJ use PAD2. Byte mode NAND flash.)
NC_8 NC_23 10uF ET_RXER
OPT
11 38 B51_Secure_no scramble : 4’hb (8051 as host. Internal SPI flash secure boot, no scramble) PCM_A[1] PCM_A0 GPIO38
C101 V21 L20
0.1uF B51_Sesure_scramble : 4’hc (8051 as host. Internal SPI flash secure boot with scarmble) PCM_A[2] PCM_A1 GPIO39 FRC_RESET
VDD_1 VDD_2 Y22 M20
12 37 PCM_A2 GPIO40 SC1/COMP1_DET
+3.3V_Normal PCM_A[3] AA22 G20
+3.3V_Normal VSS_1 VSS_2 C103
0.1uF PCM_A[4] PCM_A3 GPIO41 ERROR_OUT
13 36 R22 G19
PCM_A[5] PCM_A4 GPIO42 MODEL_OPT_0
R105 NC_9 NC_22 R21
1K 14 35 PCM_A5
PCM_A[6]
R125
R123
T23 F20
R117
R115
NC_10 NC_21 PCM_A6 GPIO50/UART1_RX DC_MREMOTE 3D SG
PCM_A[7]
OPT 1K
OPT 15 34
OPT1K
T24 F19
1K
1K
PCM_A[8] PCM_A7 GPIO51/UART1_TX DD_MREMOTE 3D SG
CL NC_20 AA23
16 33 AUD_LRCH
/PF_CE1 AR102 PCM_A[9] PCM_A8
R104
Y20 E7
10K
OPT
AL I/O3 PCM_A[3] PCM_A9 GPIO6/PM0/INT0 USB1_OCD

17 32 AUD_SCK PCM_A[10] AB17 D7
PF_ALE
AUD_MASTER_CLK R148 PCM_A[11] PCM_A10 GPIO7/PM1/PM_UART_TX USB1_CTL
W I/O2 PCM_A[2] AA21 E11
18 31 AUD_MASTER_CLK_0 HP_DET
/PF_WE PCM_A[12] PCM_A11 GPIO8/PM2
56 U23 G9
WP I/O1 PCM_A[1] PCM_A12 GPIO9/PM3 CONTROL_ATTEN
19 30 PWM1 PCM_A[13] Y23 F9
PCM_A[14] PCM_A13 GPIO10/PM4 MODEL_OPT_6
C NC_11 I/O0 PCM_A[0]
R106
C112 PWM0 W23 C5

20 29 PCM_A14 GPIO11/PM5/PM_UART_RX/INT1 MODEL_OPT_1
100pF
1K
B Q101 E8 33 R146
22
1K OPT
R118
R121
NC_12 NC_19
R124
R126
1K OPT
50V
R116
/PF_WP KRC103S 21 28 PM_SPI_CS1/GPIO12/PM6
W22 E9
/PCM_REG PCM_REG_N PM_SPI_WP1/GPIO13/PM7 /FLASH_WP
OPT NC_13 NC_18
3.3K
F7
R102
1K
1K
1K
E 22 27 PM_SPI_WP2/GPIO14/PM8/INT2 MODEL_OPT_2
AA17 F6
NC_14 NC_17 /PCM_OE PCM_OE_N GPIO15/PM9 TUNER_RESET
23 26 V22 D8
/PCM_WE PCM_WE_N PM_SPI_CS2/GPIO16/PM10 DEMOD_RESET
NC_15 NC_16 W21 G12
24 25 +5V_Normal /PCM_IORD AV_CVBS_DET
PCM_IORD_N GPIO17/PM11/INT3
Y21 F10
/PCM_IOWR PCM_IOWR_N GPIO18/PM12/INT4
R132 AA20 D9 33 R147
10K /PCM_CE PCM_CE_N PM_SPI_CK/GPIO1 SPI_SCK
V23 D11
/PCM_IRQA PCM_IRQA_N GPIO0/PM_SPI_CZ /SPI_CS
R133 P23 E10
10K /PCM_CD PCM_CD_N PM_SPI_DI/GPIO2 SPI_SDI for SERIAL FLASH
R23 D10 33 R151
/PCM_WAIT PCM_WAIT_N PM_SPI_DO/GPIO3 SPI_SDO
P22
NAND_FLASH_1G_SS NAND_FLASH_1G_TOSHIBA PCM_RST C109 PCM_RESET
NAND_FLASH_1G_HYNIX C108 CI_TS_CLK
EAN61857001 EAN61508001 AR104 0.1uF 0.1uF
EAN35669102 AA9 CI_TS_VAL
IC102-*2 IC102-*3 OPT
TS0_CLK CI_TS_SYNC
from CI SLOT
IC102-*1 K9F1G08U0D-SCB0 TC58NVG0S3ETA0BBBH /PF_CE0 AC17 AA5
H27U1G8F2BTR-BC PCM_PF_CE0Z TS0_VLD
/PF_CE1 AB20 AA10 CI_TS_DATA[0-7]
PCM_PF_CE1Z TS0_SYNC
/PF_OE AA18
NC_1 NC_29 NC_1 NC_29 22 PCM_PF_OEZ CI_TS_DATA[0]
1 48 1 48 /PF_WE AR103 AB21 AB5
NC_1 NC_29 PCM_PF_WEZ TS0_D0
1 48 AB19 AC4 CI_TS_DATA[1]
NC_2 NC_28 NC_2 NC_28 PF_ALE
NC_2 NC_28 2 47 2 47 PCM_PF_ALE TS0_D1 CI_TS_DATA[2]
/PF_WP AD17 Y6
2 47 PCM_PF_AD[15] TS0_D2
NC_3 NC_27 NC_3 NC_27 AA19 AA6 CI_TS_DATA[3]
NC_3 NC_27 3 46 3 46 /F_RB
3 46 22 PCM_PF_RBZ TS0_D3 CI_TS_DATA[4]
NC_4 NC_26 NC_4 NC_26 W6
NC_4 NC_26 4 45 4 45 TS0_D4 CI_TS_DATA[5]
AA7
4 45 TS0_D5
NC_5 I/O7 NC_5 I/O8 R134 22 M23 Y9 CI_TS_DATA[6]
NC_5 I/O7 5 44 5 44 S7_NEC_TXD UART_TX2/GPIO65 TS0_D6
5 44 R135 22 N23 AA8 CI_TS_DATA[7]
NC_6 I/O6 NC_6 I/O7 S7_NEC_RXD UART_RX2/GPIO64 TS0_D7
NC_6 I/O6 6 43 6 43 FE_TS_CLK
6 43
R/B I/O5 RY/BY I/O6 FE_TS_VAL_ERR Internal demod out
7 42 7 42 for SYSTEM/HDCP R136 22 M22 AC5
R/B
7 42
I/O5 I2C_SDA
R137 22 N22
DDCR_DA/GPIO71 TS1_CLK
AC6
FE_TS_SYNC /External demod in
RE I/O4 RE I/O5 EEPROM&URSA3 I2C_SCL DDCR_CK/GPIO72 TS1_VLD FE_TS_DATA[0-7]
RE I/O4 8 41 8 41 AB6
8 41 TS1_SYNC
CE NC_25 CE NC_25 R138 22 A5
CE NC_25 9 40 9 40 RGB_DDC_SDA DDCA_DA/UART0_TX
9 40 R139 22 B5 AC10 FE_TS_DATA[0]
NC_7 NC_24 NC_7 NC_24 RGB_DDC_SCL DDCA_CK/UART0_RX TS1_D0
NC_7 NC_24 10 39 10 39 AB10 FE_TS_DATA[1]
10 39 TS1_D1
NC_8 NC_23 NC_8 NC_23 AC9 FE_TS_DATA[2]
NC_8 NC_23 11 38 11 38 TS1_D2
11 38 K23 AB9 FE_TS_DATA[3]
VCC_1 VCC_2 VCC_1 VCC_2 PWM0
VCC_1 VCC_2 12 37 12 37 PWM0/GPIO66 TS1_D3 FE_TS_DATA[4]
PWM1 K22 AC8
12 37 PWM1/GPIO67 TS1_D4
VSS_1 VSS_2 VSS_1 VSS_2 G23 AB8 FE_TS_DATA[5]
VSS_1 VSS_2 13 36 13 36 PWM2
13 36 PWM2/GPIO68 TS1_D5 FE_TS_DATA[6]
NC_9 NC_22 NC_9 NC_22 G22 AC7
14 35 14 35 SC_RE2 PWM3/GPIO69 TS1_D6 FE_TS_DATA[7]
NC_9 NC_22 G21 AB7
14 35 TO SCART1 SC_RE1 PWM4/GPIO70 TS1_D7
NC_10 NC_21 NC_10 NC_21
NC_10 NC_21 15 34 15 34
15 34
CLE NC_20 CLE NC_20
CLE NC_20 16 33 16 33 C6 D12
16 33 DSUB_DET SAR0/GPIO31 MPIF_CLK
ALE I/O3 ALE I/O4 B6 D14
ALE I/O3 17 32 17 32 MODEL_OPT_3 SAR1/GPIO32 MPIF_CS_N Delete /PIF_SPI_CS
17 32 C8
WE I/O2 WE I/O3 PCM_5V_CTL R160
WE I/O2 18 31 18 31 SAR2/GPIO33 1K
C7 E14
18 31 SAR3/GPIO34 MPIF_BUSY
WP I/O1 WP I/O2 /RST-PHY A6
WP I/O1 19 30 19 30 SAR4/GPIO35
19 30 M_RFModule_RESET E12
NC_11 I/O0 NC_11 I/O1 3D SG
NC_11 I/O0 20 29 20 29 MPIF_D0
F12
20 29 MPIF_D1
NC_12 NC_19 NC_12 NC_19 D13
NC_12 NC_19 21 28 21 28 MPIF_D2
21 28 E13
NC_13 NC_18 NC_13 NC_18 MPIF_D3
NC_13 NC_18 22 27 22 27
22 27
NC_14 NC_17 NC_14 NC_17
NC_14 NC_17 23 26 23 26
NC_15
23 26
NC_16
NC_15
24 25
NC_16 NC_15
24 25
NC_16 S7R S7MR
24 25 S7R_MS10 S7R_DivX S7R_DivX_MS10
S7R_BASIC S7R_RM S7MR_BASIC S7MR_MS10 S7MR_DivX S7MR_DivX_MS10 S7MR_RM
IC101-*1 IC101-*2 IC101-*3 IC101-*4 IC101-*5 IC101-*6 IC101-*7 IC101-*8 IC101-*9 IC101-*10
LGE101C-R-1 [S7R BASIC] LGE101C-R [S7R MS10] LGE101DC-R-1 [S7R DIVX] LGE101DC-R [S7R DIVX/MS10] LGE101RC-R [S7R RM] LGE107C-R-1 [S7MR BASIC] LGE107C-R [S7MR MS10] LGE107DC-R-1 [S7MR DIVX] LGE107DC-R [S7MR DIVX/MS10] LGE107RC-R [S7MR RM]
AE1 W26 AE1 W26 AE1 W26 AE1 W26 AE1 W26 AE1 W26 AE1 W26 AE1 W26 AE1 W26 AE1 W26
NC_48 LVACLKP/LLV6P/BLUE[3] NC_48 LVACLKP/LLV6P/BLUE[3] NC_48 LVACLKP/LLV6P/BLUE[3] NC_48 LVACLKP/LLV6P/BLUE[3] NC_48 LVACLKP/LLV6P/BLUE[3] FRC_DDR3_A0/DDR2_NC ACKP/RLV3P/RED[3] FRC_DDR3_A0/DDR2_NC ACKP/RLV3P/RED[3] FRC_DDR3_A0/DDR2_NC ACKP/RLV3P/RED[3] FRC_DDR3_A0/DDR2_NC ACKP/RLV3P/RED[3] FRC_DDR3_A0/DDR2_NC ACKP/RLV3P/RED[3]
AF16 W25 AF16 W25 AF16 W25 AF16 W25 AF16 W25 AF16 W25 AF16 W25 AF16 W25 AF16 W25 AF16 W25
NC_78 LVACLKN/LLV6N/BLUE[2] NC_78 LVACLKN/LLV6N/BLUE[2] NC_78 LVACLKN/LLV6N/BLUE[2] NC_78 LVACLKN/LLV6N/BLUE[2] NC_78 LVACLKN/LLV6N/BLUE[2] FRC_DDR3_A1/DDR2_A6 ACKM/RLV3N/RED[2] FRC_DDR3_A1/DDR2_A6 ACKM/RLV3N/RED[2] FRC_DDR3_A1/DDR2_A6 ACKM/RLV3N/RED[2] FRC_DDR3_A1/DDR2_A6 ACKM/RLV3N/RED[2] FRC_DDR3_A1/DDR2_A6 ACKM/RLV3N/RED[2]
AF1 U26 AF1 U26 AF1 U26 AF1 U26 AF1 U26 AF1 U26 AF1 U26 AF1 U26 AF1 U26 AF1 U26
NC_64 LVA0P/LLV3P/BLUE[9] NC_64 LVA0P/LLV3P/BLUE[9] NC_64 LVA0P/LLV3P/BLUE[9] NC_64 LVA0P/LLV3P/BLUE[9] NC_64 LVA0P/LLV3P/BLUE[9] FRC_DDR3_A2/DDR2_A7 A0P/RLV0P/RED[9] FRC_DDR3_A2/DDR2_A7 A0P/RLV0P/RED[9] FRC_DDR3_A2/DDR2_A7 A0P/RLV0P/RED[9] FRC_DDR3_A2/DDR2_A7 A0P/RLV0P/RED[9] FRC_DDR3_A2/DDR2_A7 A0P/RLV0P/RED[9]
AE3 U25 AE3 U25 AE3 U25 AE3 U25 AE3 U25 AE3 U25 AE3 U25 AE3 U25 AE3 U25 AE3 U25
NC_50 LVA0N/LLV3N/BLUE[8] NC_50 LVA0N/LLV3N/BLUE[8] NC_50 LVA0N/LLV3N/BLUE[8] NC_50 LVA0N/LLV3N/BLUE[8] NC_50 LVA0N/LLV3N/BLUE[8] FRC_DDR3_A3/DDR2_A1 A0M/RLV0N/RED[8] FRC_DDR3_A3/DDR2_A1 A0M/RLV0N/RED[8] FRC_DDR3_A3/DDR2_A1 A0M/RLV0N/RED[8] FRC_DDR3_A3/DDR2_A1 A0M/RLV0N/RED[8] FRC_DDR3_A3/DDR2_A1 A0M/RLV0N/RED[8]
AD14 U24 AD14 U24 AD14 U24 AD14 U24 AD14 U24 AD14 U24 AD14 U24 AD14 U24 AD14 U24 AD14 U24
NC_45 LVA1P/LLV4P/BLUE[7] NC_45 LVA1P/LLV4P/BLUE[7] NC_45 LVA1P/LLV4P/BLUE[7] NC_45 LVA1P/LLV4P/BLUE[7] NC_45 LVA1P/LLV4P/BLUE[7] FRC_DDR3_A4/DDR2_CASZ A1P/RLV1P/RED[7] FRC_DDR3_A4/DDR2_CASZ A1P/RLV1P/RED[7] FRC_DDR3_A4/DDR2_CASZ A1P/RLV1P/RED[7] FRC_DDR3_A4/DDR2_CASZ A1P/RLV1P/RED[7] FRC_DDR3_A4/DDR2_CASZ A1P/RLV1P/RED[7]
AD3 V26 AD3 V26 AD3 V26 AD3 V26 AD3 V26 AD3 V26 AD3 V26 AD3 V26 AD3 V26 AD3 V26
AF15 V25 AF15 V25 AF15 V25 AF15 V25 AF15 V25 AF15 V25 AF15 V25 AF15 V25 AF15 V25 AF15 V25
AF2 V24 AF2 V24 AF2 V24 AF2 V24 AF2 V24 AF2 V24 AF2 V24 AF2 V24 AF2 V24 AF2 V24
AE15 W24 AE15 W24 AE15 W24 AE15 W24 AE15 W24 AE15 W24 AE15 W24 AE15 W24 AE15 W24 AE15 W24
AD2 Y26 AD2 Y26 AD2 Y26 AD2 Y26 AD2 Y26 AD2 Y26 AD2 Y26 AD2 Y26 AD2 Y26 AD2 Y26
AD16 Y25 AD16 Y25 AD16 Y25 AD16 Y25 AD16 Y25 AD16 Y25 AD16 Y25 AD16 Y25 AD16 Y25 AD16 Y25
AD15
NC_47 LVA4P/LLV8P
Y24 AD15
NC_47 LVA4P/LLV8P
Y24 AD15
NC_47 LVA4P/LLV8P
Y24 AD15
NC_47 LVA4P/LLV8P
Y24 AD15
NC_47 LVA4P/LLV8P
Y24 AD15
FRC_DDR3_A10/DDR2_A11 A4P/RLV5P/GREEN[9]
Y24 AD15
Y24 AD15
Y24 AD15
Y24 AD15
Y24 URSA_DEBUG
NC_46 LVA4N/LLV8N NC_46 LVA4N/LLV8N NC_46 LVA4N/LLV8N NC_46 LVA4N/LLV8N NC_46 LVA4N/LLV8N FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8] FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8] FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8] FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8] FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8]
AE16
NC_63
AE16
NC_63
AE16
NC_63
AE16
NC_63
AE16
NC_63
AE16
FRC_DDR3_A12/DDR2_A8
AE16
AE16
AE16
AE16
FRC_DDR3_A12/DDR2_A8 P3904
LVBCLKP/LLV0P/GREEN[5]
AC26
AC26
AC26
AC26
AC26
BCKP/TCON13/GREEN[1]
AC26
AC26
AC26
AC26
AC26 12505WS-03A00
AC25 AC25 AC25 AC25 AC25 AC25 AC25 AC25 AC25 AC25
LVBCLKN/LLV0N/GREEN[4] LVBCLKN/LLV0N/GREEN[4] LVBCLKN/LLV0N/GREEN[4] LVBCLKN/LLV0N/GREEN[4] LVBCLKN/LLV0N/GREEN[4] BCKM/TCON12/GREEN[0] BCKM/TCON12/GREEN[0] BCKM/TCON12/GREEN[0] BCKM/TCON12/GREEN[0] BCKM/TCON12/GREEN[0]
AA26 AA26 AA26 AA26 AA26 AA26 AA26 AA26 AA26 AA26
LVB0P/RLV6P/RED[1] LVB0P/RLV6P/RED[1] LVB0P/RLV6P/RED[1] LVB0P/RLV6P/RED[1] LVB0P/RLV6P/RED[1] B0P/RLV6P/GREEN[7] B0P/RLV6P/GREEN[7] B0P/RLV6P/GREEN[7] B0P/RLV6P/GREEN[7] B0P/RLV6P/GREEN[7]
AF3 AA25 AF3 AA25 AF3 AA25 AF3 AA25 AF3 AA25 AF3 AA25 AF3 AA25 AF3 AA25 AF3 AA25 AF3 AA25
NC_66 LVB0N/RLV6N/RED[0] NC_66 LVB0N/RLV6N/RED[0] NC_66 LVB0N/RLV6N/RED[0] NC_66 LVB0N/RLV6N/RED[0] NC_66 LVB0N/RLV6N/RED[0] FRC_DDR3_BA0/DDR2_BA2 B0M/RLV6N/GREEN[6] FRC_DDR3_BA0/DDR2_BA2 B0M/RLV6N/GREEN[6] FRC_DDR3_BA0/DDR2_BA2 B0M/RLV6N/GREEN[6] FRC_DDR3_BA0/DDR2_BA2 B0M/RLV6N/GREEN[6] FRC_DDR3_BA0/DDR2_BA2 B0M/RLV6N/GREEN[6]
AF14 AA24 AF14 AA24 AF14 AA24 AF14 AA24 AF14 AA24 AF14 AA24 AF14 AA24 AF14 AA24 AF14 AA24 AF14 AA24
NC_76 LVB1P/RLV7P/GREEN[9] NC_76 LVB1P/RLV7P/GREEN[9] NC_76 LVB1P/RLV7P/GREEN[9] NC_76 LVB1P/RLV7P/GREEN[9] NC_76 LVB1P/RLV7P/GREEN[9] FRC_DDR3_BA1/DDR2_ODT B1P/RLV7P/GREEN[5] FRC_DDR3_BA1/DDR2_ODT B1P/RLV7P/GREEN[5] FRC_DDR3_BA1/DDR2_ODT B1P/RLV7P/GREEN[5] FRC_DDR3_BA1/DDR2_ODT B1P/RLV7P/GREEN[5] FRC_DDR3_BA1/DDR2_ODT B1P/RLV7P/GREEN[5]
AD1 AB26 AD1 AB26 AD1 AB26 AD1 AB26 AD1 AB26 AD1 AB26 AD1 AB26 AD1 AB26 AD1 AB26 AD1 AB26
NC_32 LVB1N/RLV7N/GREEN[8] NC_32 LVB1N/RLV7N/GREEN[8] NC_32 LVB1N/RLV7N/GREEN[8] NC_32 LVB1N/RLV7N/GREEN[8] NC_32 LVB1N/RLV7N/GREEN[8] FRC_DDR3_BA2/DDR2_A12 B1M/RLV7N/GREEN[4] FRC_DDR3_BA2/DDR2_A12 B1M/RLV7N/GREEN[4] FRC_DDR3_BA2/DDR2_A12 B1M/RLV7N/GREEN[4] FRC_DDR3_BA2/DDR2_A12 B1M/RLV7N/GREEN[4] FRC_DDR3_BA2/DDR2_A12 B1M/RLV7N/GREEN[4]
AB25 AB25 AB25 AB25 AB25 AB25 AB25 AB25 AB25 AB25
AD13
LVB2P/RLV8P/GREEN[7]
AB24 AD13
AB24 AD13
AB24 AD13
AB24 AD13
AB24 AD13
B2P/RLV8P/GREEN[3]
AB24 AD13
B2P/RLV8P/GREEN[3]
AB24 AD13
B2P/RLV8P/GREEN[3]
AB24 AD13
B2P/RLV8P/GREEN[3]
AB24 AD13
B2P/RLV8P/GREEN[3]
AB24
1
NC_44 LVB2N/RLV8N/GREEN[6] NC_44 LVB2N/RLV8N/GREEN[6] NC_44 LVB2N/RLV8N/GREEN[6] NC_44 LVB2N/RLV8N/GREEN[6] NC_44 LVB2N/RLV8N/GREEN[6] FRC_DDR3_MCLK/DDR2_MCLK B2M/RLV8N/GREEN[2] FRC_DDR3_MCLK/DDR2_MCLK B2M/RLV8N/GREEN[2] FRC_DDR3_MCLK/DDR2_MCLK B2M/RLV8N/GREEN[2] FRC_DDR3_MCLK/DDR2_MCLK B2M/RLV8N/GREEN[2] FRC_DDR3_MCLK/DDR2_MCLK B2M/RLV8N/GREEN[2]
AE14 AC24 AE14 AC24 AE14 AC24 AE14 AC24 AE14 AC24 AE14 AC24 AE14 AC24 AE14 AC24 AE14 AC24 AE14 AC24
NC_61 LVB3P/LLV1P/GREEN[3] NC_61 LVB3P/LLV1P/GREEN[3] NC_61 LVB3P/LLV1P/GREEN[3] NC_61 LVB3P/LLV1P/GREEN[3] NC_61 LVB3P/LLV1P/GREEN[3] FRC_DDR3_CKE/DDR2_RASZ B3P/TCON11/BLUE[9] FRC_DDR3_CKE/DDR2_RASZ B3P/TCON11/BLUE[9] FRC_DDR3_CKE/DDR2_RASZ B3P/TCON11/BLUE[9] FRC_DDR3_CKE/DDR2_RASZ B3P/TCON11/BLUE[9] FRC_DDR3_CKE/DDR2_RASZ B3P/TCON11/BLUE[9]
AE13 AD26 AE13 AD26 AE13 AD26 AE13 AD26 AE13 AD26 AE13 AD26 AE13 AD26 AE13 AD26 AE13 AD26 AE13 AD26
NC_60 LVB3N/LLV1N/GREEN[2] NC_60 LVB3N/LLV1N/GREEN[2] NC_60 LVB3N/LLV1N/GREEN[2] NC_60 LVB3N/LLV1N/GREEN[2] NC_60 LVB3N/LLV1N/GREEN[2] FRC_DDR3_MCLKZ/DDR2_MCLKZ B3M/TCON10/BLUE[8] FRC_DDR3_MCLKZ/DDR2_MCLKZ B3M/TCON10/BLUE[8] FRC_DDR3_MCLKZ/DDR2_MCLKZ B3M/TCON10/BLUE[8] FRC_DDR3_MCLKZ/DDR2_MCLKZ B3M/TCON10/BLUE[8] FRC_DDR3_MCLKZ/DDR2_MCLKZ B3M/TCON10/BLUE[8]
AD25 AD25 AD25 AD25 AD25 AD25 AD25 AD25 AD25 AD25
LVB4P/LLV0P/GREEN[1] LVB4P/LLV0P/GREEN[1] LVB4P/LLV0P/GREEN[1] LVB4P/LLV0P/GREEN[1] LVB4P/LLV0P/GREEN[1] B4P/TCON9/BLUE[7] B4P/TCON9/BLUE[7] B4P/TCON9/BLUE[7] B4P/TCON9/BLUE[7] B4P/TCON9/BLUE[7]
AE4
AD5
NC_51
LVB4N/LLV0N/GREEN[0]
AD24
AE4
AD5
NC_51
AD24
AE4
AD5
NC_51
AD24
AE4
AD5
NC_51
AD24
AE4
AD5
NC_51
AD24
AE4
AD5
FRC_DDR3_ODT/DDR2_BA1
B4M/TCON8/BLUE[6]
AD24
AE4
AD5
B4M/TCON8/BLUE[6]
AD24
AE4
AD5
B4M/TCON8/BLUE[6]
AD24
AE4
AD5
B4M/TCON8/BLUE[6]
AD24
AE4
AD5
B4M/TCON8/BLUE[6]
AD24
FRC_SCL 2
NC_36 NC_36 NC_36 NC_36 NC_36 FRC_DDR3_RASZ/DDR2_WEZ FRC_DDR3_RASZ/DDR2_WEZ FRC_DDR3_RASZ/DDR2_WEZ FRC_DDR3_RASZ/DDR2_WEZ FRC_DDR3_RASZ/DDR2_WEZ
AF4 AD23 AF4 AD23 AF4 AD23 AF4 AD23 AF4 AD23 AF4 AD23 AF4 AD23 AF4 AD23 AF4 AD23 AF4 AD23
NC_67 RLV3P/RED[7] NC_67 RLV3P/RED[7] NC_67 RLV3P/RED[7] NC_67 RLV3P/RED[7] NC_67 RLV3P/RED[7] FRC_DDR3_CASZ/DDR2_CKE CCKP/LLV3P FRC_DDR3_CASZ/DDR2_CKE CCKP/LLV3P FRC_DDR3_CASZ/DDR2_CKE CCKP/LLV3P FRC_DDR3_CASZ/DDR2_CKE CCKP/LLV3P FRC_DDR3_CASZ/DDR2_CKE CCKP/LLV3P
AD4 AE23 AD4 AE23 AD4 AE23 AD4 AE23 AD4 AE23 AD4 AE23 AD4 AE23 AD4 AE23 AD4 AE23 AD4 AE23
NC_35 RLV3N/RED[6] NC_35 RLV3N/RED[6] NC_35 RLV3N/RED[6] NC_35 RLV3N/RED[6] NC_35 RLV3N/RED[6] FRC_DDR3_WEZ/DDR2_BA0 CCKM/LLV3N FRC_DDR3_WEZ/DDR2_BA0 CCKM/LLV3N FRC_DDR3_WEZ/DDR2_BA0 CCKM/LLV3N FRC_DDR3_WEZ/DDR2_BA0 CCKM/LLV3N FRC_DDR3_WEZ/DDR2_BA0 CCKM/LLV3N
AE26 AE26 AE26 AE26 AE26 AE26 AE26 AE26 AE26 AE26
3
AE2
NC_49
RLV0P/LVSYNC
RLV0N/LHSYNC
RLV1N/LCK
AE25
AF26
AE2
NC_49
RLV0P/LVSYNC
RLV0N/LHSYNC
RLV1N/LCK
AE25
AF26
AE2
NC_49
RLV0P/LVSYNC
RLV0N/LHSYNC
RLV1N/LCK
AE25
AF26
AE2
NC_49
RLV0P/LVSYNC
RLV0N/LHSYNC
RLV1N/LCK
AE25
AF26
AE2
NC_49
RLV0P/LVSYNC
RLV0N/LHSYNC
RLV1N/LCK
AE25
AF26
AE2
FRC_DDR3_RESETB/DDR2_A3
C0P/LLV0P/BLUE[5]
C0M/LLV0N/BLUE[4]
C1P/LLV1P/BLUE[3]
AE25
AF26
AE2
C0P/LLV0P/BLUE[5]
C0M/LLV0N/BLUE[4]
C1P/LLV1P/BLUE[3]
AE25
AF26
AE2
C0P/LLV0P/BLUE[5]
C0M/LLV0N/BLUE[4]
C1P/LLV1P/BLUE[3]
AE25
AF26
AE2
C0P/LLV0P/BLUE[5]
C0M/LLV0N/BLUE[4]
C1P/LLV1P/BLUE[3]
AE25
AF26
AE2
C0P/LLV0P/BLUE[5]
C0M/LLV0N/BLUE[4]
C1P/LLV1P/BLUE[3]
AE25
AF26
FRC_SDA
AF25 AF25 AF25 AF25 AF25 AF25 AF25 AF25 AF25 AF25
RLV2P/RED[9] RLV2P/RED[9] RLV2P/RED[9] RLV2P/RED[9] RLV2P/RED[9] C1M/LLV1N/BLUE[2] C1M/LLV1N/BLUE[2] C1M/LLV1N/BLUE[2] C1M/LLV1N/BLUE[2] C1M/LLV1N/BLUE[2]
AF8 AE24 AF8 AE24 AF8 AE24 AF8 AE24 AF8 AE24 AF8 AE24 AF8 AE24 AF8 AE24 AF8 AE24 AF8 AE24
AD9
NC_71 RLV1P/LDE
AF24 AD9
NC_71 RLV1P/LDE
AF24 AD9
NC_71 RLV1P/LDE
AF24 AD9
NC_71 RLV1P/LDE
AF24 AD9
NC_71 RLV1P/LDE
AF24 AD9
FRC_DDR3_DQSL/DDR2_DQS0 C2P/LLV2P/BLUE[1]
AF24 AD9
AF24 AD9
AF24 AD9
AF24 AD9
AF24
4
NC_40 RLV2N/RED[8] NC_40 RLV2N/RED[8] NC_40 RLV2N/RED[8] NC_40 RLV2N/RED[8] NC_40 RLV2N/RED[8] FRC_DDR3_DQSLB/DDR2_DQSB0 C2M/LLV2N/BLUE[0] FRC_DDR3_DQSLB/DDR2_DQSB0 C2M/LLV2N/BLUE[0] FRC_DDR3_DQSLB/DDR2_DQSB0 C2M/LLV2N/BLUE[0] FRC_DDR3_DQSLB/DDR2_DQSB0 C2M/LLV2N/BLUE[0] FRC_DDR3_DQSLB/DDR2_DQSB0 C2M/LLV2N/BLUE[0]
RLV4P/RED[5] RLV4P/RED[5] RLV4P/RED[5] RLV4P/RED[5] RLV4P/RED[5] C3P/LLV4P C3P/LLV4P C3P/LLV4P C3P/LLV4P C3P/LLV4P
NC_56 RLV4N/RED[4] NC_56 RLV4N/RED[4] NC_56 RLV4N/RED[4] NC_56 RLV4N/RED[4] NC_56 RLV4N/RED[4] FRC_DDR3_DQSU/DDR2_DQS1 C3M/LLV4N FRC_DDR3_DQSU/DDR2_DQS1 C3M/LLV4N FRC_DDR3_DQSU/DDR2_DQS1 C3M/LLV4N FRC_DDR3_DQSU/DDR2_DQS1 C3M/LLV4N FRC_DDR3_DQSU/DDR2_DQS1 C3M/LLV4N
AF9 AE22 AF9 AE22 AF9 AE22 AF9 AE22 AF9 AE22 AF9 AE22 AF9 AE22 AF9 AE22 AF9 AE22 AF9 AE22
NC_72 RLV5P/RED[3] NC_72 RLV5P/RED[3] NC_72 RLV5P/RED[3] NC_72 RLV5P/RED[3] NC_72 RLV5P/RED[3] FRC_DDR3_DQSUB/DDR2_DQSB1 C4P/LLV5P FRC_DDR3_DQSUB/DDR2_DQSB1 C4P/LLV5P FRC_DDR3_DQSUB/DDR2_DQSB1 C4P/LLV5P FRC_DDR3_DQSUB/DDR2_DQSB1 C4P/LLV5P FRC_DDR3_DQSUB/DDR2_DQSB1 C4P/LLV5P
RLV5N/RED[2] RLV5N/RED[2] RLV5N/RED[2] RLV5N/RED[2] RLV5N/RED[2] C4M/LLV5N C4M/LLV5N C4M/LLV5N C4M/LLV5N C4M/LLV5N
AE11 AE11 AE11 AE11 AE11 AE11 AE11 AE11 AE11 AE11
NC_58 NC_58 NC_58 NC_58 NC_58 FRC_DDR3_DML/DDR2_DQ7 FRC_DDR3_DML/DDR2_DQ7 FRC_DDR3_DML/DDR2_DQ7 FRC_DDR3_DML/DDR2_DQ7 FRC_DDR3_DML/DDR2_DQ7
NC_69 NC_69 NC_69 NC_69 NC_69 FRC_DDR3_DMU/DDR2_DQ11 FRC_DDR3_DMU/DDR2_DQ11 FRC_DDR3_DMU/DDR2_DQ11 FRC_DDR3_DMU/DDR2_DQ11 FRC_DDR3_DMU/DDR2_DQ11
TCON3/OE/GOE/GCLK2 TCON3/OE/GOE/GCLK2 TCON3/OE/GOE/GCLK2 TCON3/OE/GOE/GCLK2 TCON3/OE/GOE/GCLK2 DCKP/TCON5 DCKP/TCON5 DCKP/TCON5 DCKP/TCON5 DCKP/TCON5
AE6 AE19 AE6 AE19 AE6 AE19 AE6 AE19 AE6 AE19 AE6 AE19 AE6 AE19 AE6 AE19 AE6 AE19 AE6 AE19
NC_53 TCON15/SCAN_BLK1 NC_53 TCON15/SCAN_BLK1 NC_53 TCON15/SCAN_BLK1 NC_53 TCON15/SCAN_BLK1 NC_53 TCON15/SCAN_BLK1 FRC_DDR3_DQL0/DDR2_DQ6 DCKM/TCON4 FRC_DDR3_DQL0/DDR2_DQ6 DCKM/TCON4 FRC_DDR3_DQL0/DDR2_DQ6 DCKM/TCON4 FRC_DDR3_DQL0/DDR2_DQ6 DCKM/TCON4 FRC_DDR3_DQL0/DDR2_DQ6 DCKM/TCON4
AF11 AD21 AF11 AD21 AF11 AD21 AF11 AD21 AF11 AD21 AF11 AD21 AF11 AD21 AF11 AD21 AF11 AD21 AF11 AD21
NC_74 TCON18/CS7/GCLK5 NC_74 TCON18/CS7/GCLK5 NC_74 TCON18/CS7/GCLK5 NC_74 TCON18/CS7/GCLK5 NC_74 TCON18/CS7/GCLK5 FRC_DDR3_DQL1/DDR2_DQ0 D0P/LLV6P FRC_DDR3_DQL1/DDR2_DQ0 D0P/LLV6P FRC_DDR3_DQL1/DDR2_DQ0 D0P/LLV6P FRC_DDR3_DQL1/DDR2_DQ0 D0P/LLV6P FRC_DDR3_DQL1/DDR2_DQ0 D0P/LLV6P
AD6 AE21 AD6 AE21 AD6 AE21 AD6 AE21 AD6 AE21 AD6 AE21 AD6 AE21 AD6 AE21 AD6 AE21 AD6 AE21
NC_37 TCON19/CS8/GCLK6 NC_37 TCON19/CS8/GCLK6 NC_37 TCON19/CS8/GCLK6 NC_37 TCON19/CS8/GCLK6 NC_37 TCON19/CS8/GCLK6 FRC_DDR3_DQL2/DDR2_DQ1 D0M/LLV6N FRC_DDR3_DQL2/DDR2_DQ1 D0M/LLV6N FRC_DDR3_DQL2/DDR2_DQ1 D0M/LLV6N FRC_DDR3_DQL2/DDR2_DQ1 D0M/LLV6N FRC_DDR3_DQL2/DDR2_DQ1 D0M/LLV6N
AD12 AF21 AD12 AF21 AD12 AF21 AD12 AF21 AD12 AF21 AD12 AF21 AD12 AF21 AD12 AF21 AD12 AF21 AD12 AF21
NC_43 TCON11/CS5/HCON NC_43 TCON11/CS5/HCON NC_43 TCON11/CS5/HCON NC_43 TCON11/CS5/HCON NC_43 TCON11/CS5/HCON FRC_DDR3_DQL3/DDR2_DQ2 D1P/LLV7P FRC_DDR3_DQL3/DDR2_DQ2 D1P/LLV7P FRC_DDR3_DQL3/DDR2_DQ2 D1P/LLV7P FRC_DDR3_DQL3/DDR2_DQ2 D1P/LLV7P FRC_DDR3_DQL3/DDR2_DQ2 D1P/LLV7P
NC_52 TCON10/CS4/OPT_N NC_52 TCON10/CS4/OPT_N NC_52 TCON10/CS4/OPT_N NC_52 TCON10/CS4/OPT_N NC_52 TCON10/CS4/OPT_N FRC_DDR3_DQL4/DDR2_DQ4 D1M/LLV7N FRC_DDR3_DQL4/DDR2_DQ4 D1M/LLV7N FRC_DDR3_DQL4/DDR2_DQ4 D1M/LLV7N FRC_DDR3_DQL4/DDR2_DQ4 D1M/LLV7N FRC_DDR3_DQL4/DDR2_DQ4 D1M/LLV7N
EEPROM_1MBIT_ATMEL AF12
AF5
NC_75
NC_68
TCON9/CS3/OPT_P
TCON16/WPWM
AE20
AF20
AF12
AF5
NC_75
NC_68
TCON9/CS3/OPT_P
TCON16/WPWM
AE20
AF20
AF12
AF5
NC_75
NC_68
TCON9/CS3/OPT_P
TCON16/WPWM
AE20
AF20
AF12
AF5
NC_75
NC_68
TCON9/CS3/OPT_P
TCON16/WPWM
AE20
AF20
AF12
AF5
NC_75
NC_68
TCON9/CS3/OPT_P
TCON16/WPWM
AE20
AF20
AF12
AF5
FRC_DDR3_DQL5/DDR2_NC
FRC_DDR3_DQL6/DDR2_DQ3
D2P/LLV8P
D2M/LLV8N
AE20
AF20
AF12
AF5
D2P/LLV8P
D2M/LLV8N
AE20
AF20
AF12
AF5
D2P/LLV8P
D2M/LLV8N
AE20
AF20
AF12
AF5
D2P/LLV8P
D2M/LLV8N
AE20
AF20
AF12
AF5
D2P/LLV8P
D2M/LLV8N
AE20
AF20
AE12 AF19 AE12 AF19 AE12 AF19 AE12 AF19 AE12 AF19 AE12 AF19 AE12 AF19 AE12 AF19 AE12 AF19 AE12 AF19
NC_59 TCON12/DPM NC_59 TCON12/DPM NC_59 TCON12/DPM NC_59 TCON12/DPM NC_59 TCON12/DPM FRC_DDR3_DQL7/DDR2_DQ5 D3P/TCON3 FRC_DDR3_DQL7/DDR2_DQ5 D3P/TCON3 FRC_DDR3_DQL7/DDR2_DQ5 D3P/TCON3 FRC_DDR3_DQL7/DDR2_DQ5 D3P/TCON3 FRC_DDR3_DQL7/DDR2_DQ5 D3P/TCON3
IC104-*1 AE10
AF7
AD11
NC_57
NC_70
TCON1/STV/GSP/VST
TCON5/TP/SOE
TCON14/SACN_BLK
AE18
AF18
AE10
AF7
AD11
NC_57
NC_70
TCON1/STV/GSP/VST
TCON5/TP/SOE
TCON14/SACN_BLK
AE18
AF18
AE10
AF7
AD11
NC_57
NC_70
TCON1/STV/GSP/VST
TCON5/TP/SOE
TCON14/SACN_BLK
AE18
AF18
AE10
AF7
AD11
NC_57
NC_70
TCON1/STV/GSP/VST
TCON5/TP/SOE
TCON14/SACN_BLK
AE18
AF18
AE10
AF7
AD11
NC_57
NC_70
TCON1/STV/GSP/VST
TCON5/TP/SOE
TCON14/SACN_BLK
AE18
AF18
AE10
AF7
AD11
FRC_DDR3_DQU0/DDR2_DQ8
D3M/TCON2
D4P/TCON1
D4M/TCON0
AE18
AF18
AE10
AF7
AD11
D3M/TCON2
D4P/TCON1
D4M/TCON0
AE18
AF18
AE10
AF7
AD11
D3M/TCON2
D4P/TCON1
D4M/TCON0
AE18
AF18
AE10
AF7
AD11
D3M/TCON2
D4P/TCON1
D4M/TCON0
AE18
AF18
AE10
AF7
AD11
D3M/TCON2
D4P/TCON1
D4M/TCON0
AE18
AF18
NC_42 NC_42 NC_42 NC_42 NC_42 FRC_DDR3_DQU2/DDR2_DQ13 FRC_DDR3_DQU2/DDR2_DQ13 FRC_DDR3_DQU2/DDR2_DQ13 FRC_DDR3_DQU2/DDR2_DQ13 FRC_DDR3_DQU2/DDR2_DQ13
AT24C1024BN-SH-T AD7
AD10
AE7
NC_38
NC_41 TCON21/CS10/VGH_ODD
AB22
AB23
AD7
AD10
AE7
NC_38
AB22
AB23
AD7
AD10
AE7
NC_38
AB22
AB23
AD7
AD10
AE7
NC_38
AB22
AB23
AD7
AD10
AE7
NC_38
AB22
AB23
AD7
AD10
AE7
FRC_DDR3_DQU4/DDR2_DQ15 GPIO0/TCON15/HSYNC/VDD_ODD
AB22
AB23
AD7
AD10
AE7
AB22
AB23
AD7
AD10
AE7
AB22
AB23
AD7
AD10
AE7
AB22
AB23
AD7
AD10
AE7
AB22
AB23
NC_54 TCON20/CS9/VGH_EVEN NC_54 TCON20/CS9/VGH_EVEN NC_54 TCON20/CS9/VGH_EVEN NC_54 TCON20/CS9/VGH_EVEN NC_54 TCON20/CS9/VGH_EVEN FRC_DDR3_DQU5/DDR2_DQ9 GPIO1/TCON14/VSYNC/VDD_EVEN FRC_DDR3_DQU5/DDR2_DQ9 GPIO1/TCON14/VSYNC/VDD_EVEN FRC_DDR3_DQU5/DDR2_DQ9 GPIO1/TCON14/VSYNC/VDD_EVEN FRC_DDR3_DQU5/DDR2_DQ9 GPIO1/TCON14/VSYNC/VDD_EVEN FRC_DDR3_DQU5/DDR2_DQ9 GPIO1/TCON14/VSYNC/VDD_EVEN
IC103-*1 AF10
AD8
NC_73
NC_39
TCON13/LEDON
TCON17/CS6/GCLK4
AC23
AC22
AF10
AD8
NC_73
NC_39
TCON13/LEDON
TCON17/CS6/GCLK4
AC23
AC22
AF10
AD8
NC_73
NC_39
TCON13/LEDON
TCON17/CS6/GCLK4
AC23
AC22
AF10
AD8
NC_73
NC_39
TCON13/LEDON
TCON17/CS6/GCLK4
AC23
AC22
AF10
AD8
NC_73
NC_39
TCON13/LEDON
TCON17/CS6/GCLK4
AC23
AC22
AF10
AD8
FRC_DDR3_DQU7/DDR2_DQM1
GPIO2/TCON7/LDE/GCLK4
GPIO3/TCON6/LCK/GCLK2
AC23
AC22
AF10
AD8
AC23
AC22
AF10
AD8
AC23
AC22
AF10
AD8
AC23
AC22
AF10
AD8
AC23
AC22
CAT24C08WI-GT3-H-RECV(TV) NC_26
AB16
AA14
NC_26
AB16
AA14
NC_26
AB16
AA14
NC_26
AB16
AA14
NC_26
AB16
AA14
FRC_GPIO0/UART_RX
AB16
AA14
FRC_GPIO0/UART_RX
AB16
AA14
FRC_GPIO0/UART_RX
AB16
AA14
FRC_GPIO0/UART_RX
AB16
AA14
FRC_GPIO0/UART_RX
AB16
AA14
NC VCC NC_19
NC_30
AC15
NC_19
NC_30
AC15
NC_19
NC_30
AC15
NC_19
NC_30
AC15
NC_19
NC_30
AC15
FRC_GPIO1
FRC_GPIO3
AC15
FRC_GPIO1
FRC_GPIO3
AC15
FRC_GPIO1
FRC_GPIO3
AC15
FRC_GPIO1
FRC_GPIO3
AC15
FRC_GPIO1
FRC_GPIO3
AC15
1 8 NC_15
Y16
NC_15
Y16
NC_15
Y16
NC_15
Y16
NC_15
Y16
FRC_GPIO8
Y16
FRC_GPIO8
Y16
FRC_GPIO8
Y16
FRC_GPIO8
Y16
FRC_GPIO8
Y16
AC16 AC16 AC16 AC16 AC16 AC16 AC16 AC16 AC16 AC16
NC_31 NC_31 NC_31 NC_31 NC_31 FRC_GPIO9/UART_TX FRC_GPIO9/UART_TX FRC_GPIO9/UART_TX FRC_GPIO9/UART_TX FRC_GPIO9/UART_TX
AE8 AC14 AE8 AC14 AE8 AC14 AE8 AC14 AE8 AC14 AE8 AC14 AE8 AC14 AE8 AC14 AE8 AC14 AE8 AC14
NC_1 VCC NC_55 NC_29 NC_55 NC_29 NC_55 NC_29 NC_55 NC_29 NC_55 NC_29 FRC_DDR3_NC/DDR2_DQM0 FRC_GPIO10 FRC_DDR3_NC/DDR2_DQM0 FRC_GPIO10 FRC_DDR3_NC/DDR2_DQM0 FRC_GPIO10 FRC_DDR3_NC/DDR2_DQM0 FRC_GPIO10 FRC_DDR3_NC/DDR2_DQM0 FRC_GPIO10
1 8 Y11
Y19
NC_12 NC_21
AA16
AA15
Y11
Y19
NC_12 NC_21
AA16
AA15
Y11
Y19
NC_12 NC_21
AA16
AA15
Y11
Y19
NC_12 NC_21
AA16
AA15
Y11
Y19
NC_12 NC_21
AA16
AA15
Y11
Y19
FRC_REXT FRC_I2CM_DA
AA16
AA15
Y11
Y19
AA16
AA15
Y11
Y19
AA16
AA15
Y11
Y19
AA16
AA15
Y11
Y19
AA16
AA15
A1 WP GND_105 NC_20 GND_105 NC_20 GND_105 NC_20 GND_105 NC_20 GND_105 NC_20 FRC_TESTPIN FRC_I2CM_CK FRC_TESTPIN FRC_I2CM_CK FRC_TESTPIN FRC_I2CM_CK FRC_TESTPIN FRC_I2CM_CK FRC_TESTPIN FRC_I2CM_CK
2 7 NC_11
NC_17
Y10
AA11
NC_11
NC_17
Y10
AA11
NC_11
NC_17
Y10
AA11
NC_11
NC_17
Y10
AA11
NC_11
NC_17
Y10
AA11
FRC_I2CS_DA
FRC_I2CS_CK
Y10
AA11
FRC_I2CS_DA
FRC_I2CS_CK
Y10
AA11
FRC_I2CS_DA
FRC_I2CS_CK
Y10
AA11
FRC_I2CS_DA
FRC_I2CS_CK
Y10
AA11
FRC_I2CS_DA
FRC_I2CS_CK
Y10
AA11
NC_2 WP AB15 AB15 AB15 AB15 AB15 AB15 AB15 AB15 AB15 AB15
2 7 NC_25
NC_24
AB14
NC_25
NC_24
AB14
NC_25
NC_24
AB14
NC_25
NC_24
AB14
NC_25
NC_24
AB14
FRC_PWM0
FRC_PWM1
AB14
FRC_PWM0
FRC_PWM1
AB14
FRC_PWM0
FRC_PWM1
AB14
FRC_PWM0
FRC_PWM1
AB14
FRC_PWM0
FRC_PWM1
AB14
A2 SCL
3 6
A2 SCL
3 6
GND SDA
VSS SDA 4 5
4 5
S7MR-PLUS I2C +3.3V_Normal

HDCP_EEPROM_ON_SEMI_NEW S7M-PLUS_BASIC S7M-PLUS_MS10 S7M-PLUS_DivX S7M-PLUS_RM
IC101-*11
LGE107C-RP-1 [S7M+ BASIC]
IC101-*12
LGE107C-RP [S7M+ MS10]
IC101-*13
LGE107DC-RP-1 [S7M+ DIVX]
IC101-*14
LGE107RC-RP [S7M+ RM] DIMMING
+3.3V_Normal AE1
AF16
FRC_DDR3_A0/DDR2_NC
FRC_DDR3_A1/DDR2_A6
ACKP/RLV3P/RED[3]
ACKM/RLV3N/RED[2]
W26
W25
AE1
AF16
FRC_DDR3_A0/DDR2_NC
FRC_DDR3_A1/DDR2_A6
ACKP/RLV3P/RED[3]
ACKM/RLV3N/RED[2]
W26
W25
AE1
AF16
FRC_DDR3_A0/DDR2_NC
FRC_DDR3_A1/DDR2_A6
ACKP/RLV3P/RED[3]
ACKM/RLV3N/RED[2]
W26
W25
AE1
AF16
FRC_DDR3_A0/DDR2_NC
FRC_DDR3_A1/DDR2_A6
ACKP/RLV3P/RED[3]
ACKM/RLV3N/RED[2]
W26
W25
AF1 AF1 AF1 AF1
HDCP EEPROM
U26 U26 U26 U26
FRC_DDR3_A2/DDR2_A7 A0P/RLV0P/RED[9] FRC_DDR3_A2/DDR2_A7 A0P/RLV0P/RED[9] FRC_DDR3_A2/DDR2_A7 A0P/RLV0P/RED[9] FRC_DDR3_A2/DDR2_A7 A0P/RLV0P/RED[9]
+3.3V_Normal AE3
AD14
AD3
FRC_DDR3_A3/DDR2_A1
FRC_DDR3_A4/DDR2_CASZ
A0M/RLV0N/RED[8]
A1P/RLV1P/RED[7]
U25
U24
V26
AE3
AD14
AD3
FRC_DDR3_A3/DDR2_A1
A0M/RLV0N/RED[8]
A1P/RLV1P/RED[7]
U25
U24
V26
AE3
AD14
AD3
FRC_DDR3_A3/DDR2_A1
A0M/RLV0N/RED[8]
A1P/RLV1P/RED[7]
U25
U24
V26
AE3
AD14
AD3
FRC_DDR3_A3/DDR2_A1
A0M/RLV0N/RED[8]
A1P/RLV1P/RED[7]
U25
U24
V26
Addr:10101-- AF15
AF2
FRC_DDR3_A6/DDR2_A0
A1M/RLV1N/RED[6]
A2P/RLV2P/RED[5]
V25 AF15
AF2
FRC_DDR3_A6/DDR2_A0
A1M/RLV1N/RED[6]
A2P/RLV2P/RED[5]
V25 AF15
AF2
FRC_DDR3_A6/DDR2_A0
A1M/RLV1N/RED[6]
A2P/RLV2P/RED[5]
V25 AF15
AF2
FRC_DDR3_A6/DDR2_A0
A1M/RLV1N/RED[6]
A2P/RLV2P/RED[5]
V25
EEPROM
V24 V24 V24 V24
R140
R141
R142
3.3K
R143
3.3K
R144
2.2K
R145
2.2K
FRC_DDR3_A7/DDR2_A5 A2M/RLV2N/RED[4] FRC_DDR3_A7/DDR2_A5 A2M/RLV2N/RED[4] FRC_DDR3_A7/DDR2_A5 A2M/RLV2N/RED[4] FRC_DDR3_A7/DDR2_A5 A2M/RLV2N/RED[4]
AE15 W24 AE15 W24 AE15 W24 AE15 W24
FRC_DDR3_A8/DDR2_A2 A3P/RLV4P/RED[1] FRC_DDR3_A8/DDR2_A2 A3P/RLV4P/RED[1] FRC_DDR3_A8/DDR2_A2 A3P/RLV4P/RED[1] FRC_DDR3_A8/DDR2_A2 A3P/RLV4P/RED[1]
AD2 Y26 AD2 Y26 AD2 Y26 AD2 Y26
FRC_DDR3_A9/DDR2_A9 A3M/RLV4N/RED[0] FRC_DDR3_A9/DDR2_A9 A3M/RLV4N/RED[0] FRC_DDR3_A9/DDR2_A9 A3M/RLV4N/RED[0] FRC_DDR3_A9/DDR2_A9 A3M/RLV4N/RED[0]
AD16 Y25 AD16 Y25 AD16 Y25 AD16 Y25
FRC_DDR3_A10/DDR2_A11 A4P/RLV5P/GREEN[9] FRC_DDR3_A10/DDR2_A11 A4P/RLV5P/GREEN[9] FRC_DDR3_A10/DDR2_A11 A4P/RLV5P/GREEN[9] FRC_DDR3_A10/DDR2_A11 A4P/RLV5P/GREEN[9]
AD15 Y24 AD15 Y24 AD15 Y24 AD15 Y24
1K
1K
FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8] FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8] FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8] FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8]

AE16 AE16 AE16 AE16
FRC_DDR3_A12/DDR2_A8 FRC_DDR3_A12/DDR2_A8 FRC_DDR3_A12/DDR2_A8 FRC_DDR3_A12/DDR2_A8
AC26
AC26
AC26
AC26
R156 10K
C105 AF3
BCKM/TCON12/GREEN[0]
B0P/RLV6P/GREEN[7]
AC25
AA26
AA25 AF3
B0P/RLV6P/GREEN[7]
AC25
AA26
AA25 AF3
B0P/RLV6P/GREEN[7]
AC25
AA26
AA25 AF3
B0P/RLV6P/GREEN[7]
AC25
AA26
AA25 A_DIM PWM0
FRC_DDR3_BA0/DDR2_BA2 B0M/RLV6N/GREEN[6] FRC_DDR3_BA0/DDR2_BA2 B0M/RLV6N/GREEN[6] FRC_DDR3_BA0/DDR2_BA2 B0M/RLV6N/GREEN[6] FRC_DDR3_BA0/DDR2_BA2 B0M/RLV6N/GREEN[6]
HDCP_EEPROM_CATALYST_OLD EEPROM_1MBIT_ST AF14

FRC_DDR3_BA1/DDR2_ODT B1P/RLV7P/GREEN[5]
AA24 AF14
AA24 AF14
AA24 AF14
AA24
0.1uF AD1
FRC_DDR3_BA2/DDR2_A12 B1M/RLV7N/GREEN[4]
AB26
AB25
AD1
AB26
AB25
AD1
AB26
AB25
AD1
AB26
AB25
IC103 IC104 AD13

AE14
FRC_DDR3_MCLK/DDR2_MCLK
B2P/RLV8P/GREEN[3]
B2M/RLV8N/GREEN[2]
AB24
AC24
AD13
AE14
B2P/RLV8P/GREEN[3]
B2M/RLV8N/GREEN[2]
AB24
AC24
AD13
AE14
B2P/RLV8P/GREEN[3]
B2M/RLV8N/GREEN[2]
AB24
AC24
AD13
AE14
B2P/RLV8P/GREEN[3]
B2M/RLV8N/GREEN[2]
AB24
AC24 R157 100
CAT24WC08W-T
AE13
FRC_DDR3_CKE/DDR2_RASZ
FRC_DDR3_MCLKZ/DDR2_MCLKZ
B3P/TCON11/BLUE[9]
B3M/TCON10/BLUE[8]
AD26 AE13
B3P/TCON11/BLUE[9]
B3M/TCON10/BLUE[8]
AD26 AE13
B3P/TCON11/BLUE[9]
B3M/TCON10/BLUE[8]
AD26 AE13
B3P/TCON11/BLUE[9]
B3M/TCON10/BLUE[8]
AD26
PWM_DIM PWM2
C107 M24M01-HRMN6TP B4P/TCON9/BLUE[7]
B4M/TCON8/BLUE[6]
AD25
AD24
B4P/TCON9/BLUE[7]
B4M/TCON8/BLUE[6]
AD25
AD24
B4P/TCON9/BLUE[7]
B4M/TCON8/BLUE[6]
AD25
AD24
B4P/TCON9/BLUE[7]
B4M/TCON8/BLUE[6]
AD25
AD24
R113 AE4
AD5
AE4
AD5
AE4
AD5
AE4
AD5
4.7K 0.1uF AF4

FRC_DDR3_RASZ/DDR2_WEZ
FRC_DDR3_CASZ/DDR2_CKE CCKP/LLV3P
AD23 AF4
AD23 AF4
AD23 AF4
AD23
AMP_SDA
A0 VCC
AD4
FRC_DDR3_WEZ/DDR2_BA0 CCKM/LLV3N
AE23
AE26
AD4
AE23
AE26
AD4
AE23
AE26
AD4
AE23
AE26 R155
1 8 AE2
C0P/LLV0P/BLUE[5]
C0M/LLV0N/BLUE[4]
AE25
AF26
AE2
C0P/LLV0P/BLUE[5]
C0M/LLV0N/BLUE[4]
AE25
AF26
AE2
C0P/LLV0P/BLUE[5]
C0M/LLV0N/BLUE[4]
AE25
AF26
AE2
C0P/LLV0P/BLUE[5]
C0M/LLV0N/BLUE[4]
AE25
AF26 AMP_SCL 0
NC VCC C1P/LLV1P/BLUE[3]
AF25
C1P/LLV1P/BLUE[3]
AF25
C1P/LLV1P/BLUE[3]
AF25
C1P/LLV1P/BLUE[3]
AF25
$0.199 1 8 AF8
AD9
FRC_DDR3_DQSL/DDR2_DQS0
C1M/LLV1N/BLUE[2]
C2P/LLV2P/BLUE[1]
AE24
AF24
AF8
AD9
C1M/LLV1N/BLUE[2]
C2P/LLV2P/BLUE[1]
AE24
AF24
AF8
AD9
C1M/LLV1N/BLUE[2]
C2P/LLV2P/BLUE[1]
AE24
AF24
AF8
AD9
C1M/LLV1N/BLUE[2]
C2P/LLV2P/BLUE[1]
AE24
AF24
C111 OPT
A1 WP R127 4.7K
FRC_DDR3_DQSLB/DDR2_DQSB0 C2M/LLV2N/BLUE[0]
AF23
AF23
AF23
AF23
2 7 AE9
AF9
FRC_DDR3_DQSU/DDR2_DQS1
FRC_DDR3_DQSUB/DDR2_DQSB1
C3P/LLV4P
C3M/LLV4N
C4P/LLV5P
AD22
AE22
AE9
AF9
C3P/LLV4P
C3M/LLV4N
C4P/LLV5P
AD22
AE22
AE9
AF9
C3P/LLV4P
C3M/LLV4N
C4P/LLV5P
AD22
AE22
AE9
AF9
C3P/LLV4P
C3M/LLV4N
C4P/LLV5P
AD22
AE22
I2C_SDA 2.2uF
AF22 AF22 AF22 AF22
C4M/LLV5N C4M/LLV5N C4M/LLV5N C4M/LLV5N
I2C_SCL E1 WP AE11
AF6
FRC_DDR3_DML/DDR2_DQ7
AE11
AF6
AE11
AF6
AE11
AF6
I2C_SCL
A2 SCL R128 22 2 7
FRC_DDR3_DMU/DDR2_DQ11
AD19
AD19
AD19
AD19
3 6 AE6
AF11
AD6
AD12
DCKP/TCON5
DCKM/TCON4
D0P/LLV6P
D0M/LLV6N
AE19
AD21
AE21
AF21
AE6
AF11
AD6
AD12
DCKP/TCON5
DCKM/TCON4
D0P/LLV6P
D0M/LLV6N
AE19
AD21
AE21
AF21
AE6
AF11
AD6
AD12
DCKP/TCON5
DCKM/TCON4
D0P/LLV6P
D0M/LLV6N
AE19
AD21
AE21
AF21
AE6
AF11
AD6
AD12
DCKP/TCON5
DCKM/TCON4
D0P/LLV6P
D0M/LLV6N
AE19
AD21
AE21
AF21
LD650 Scan
FRC_DDR3_DQL3/DDR2_DQ2 D1P/LLV7P FRC_DDR3_DQL3/DDR2_DQ2 D1P/LLV7P FRC_DDR3_DQL3/DDR2_DQ2 D1P/LLV7P FRC_DDR3_DQL3/DDR2_DQ2 D1P/LLV7P
VSS SDA
AE5 AD20 AE5 AD20 AE5 AD20 AE5 AD20
NEC_SDA
A0’h
FRC_DDR3_DQL4/DDR2_DQ4 D1M/LLV7N FRC_DDR3_DQL4/DDR2_DQ4 D1M/LLV7N FRC_DDR3_DQL4/DDR2_DQ4 D1M/LLV7N FRC_DDR3_DQL4/DDR2_DQ4 D1M/LLV7N
4 5 E2 SCL
R111 22
AF12
AF5
D2P/LLV8P
D2M/LLV8N
AE20
AF20
AF12
AF5
D2P/LLV8P
D2M/LLV8N
AE20
AF20
AF12
AF5
D2P/LLV8P
D2M/LLV8N
AE20
AF20
AF12
AF5
D2P/LLV8P
D2M/LLV8N
AE20
AF20 SCAN_BLK2 R158 100
3 6 I2C_SCL AE12
FRC_DDR3_DQL7/DDR2_DQ5 D3P/TCON3
D3M/TCON2
AF19
AD18
AE12
D3M/TCON2
AF19
AD18
AE12
D3M/TCON2
AF19
AD18
AE12
D3M/TCON2
AF19
AD18
NEC_SCL FRC_PWM1
AE10 AE18 AE10 AE18 AE10 AE18 AE10 AE18
R129 22 I2C_SDA AF7
AD11
D4P/TCON1
D4M/TCON0
AF18 AF7
AD11
D4P/TCON1
D4M/TCON0
AF18 AF7
AD11
D4P/TCON1
D4M/TCON0
AF18 AF7
AD11
D4P/TCON1
D4M/TCON0
AF18
OPT
FRC_DDR3_DQU2/DDR2_DQ13 FRC_DDR3_DQU2/DDR2_DQ13 FRC_DDR3_DQU2/DDR2_DQ13 FRC_DDR3_DQU2/DDR2_DQ13
AD7 AD7 AD7 AD7
FRC_DDR3_DQU3/DDR2_DQ12 FRC_DDR3_DQU3/DDR2_DQ12 FRC_DDR3_DQU3/DDR2_DQ12 FRC_DDR3_DQU3/DDR2_DQ12
AD10 AB22 AD10 AB22 AD10 AB22 AD10 AB22
VSS
4 5
SDA
R112 22 AE7
AF10
GPIO0/TCON15/HSYNC/VDD_ODD
GPIO1/TCON14/VSYNC/VDD_EVEN
AB23
AC23
AE7
AF10
AB23
AC23
AE7
AF10
AB23
AC23
AE7
AF10
AB23
AC23
R159 100 FRC_PWM0
I2C_SDA AD8
AC22 AD8
AC22 AD8
AC22 AD8
AC22
AB16 AB16 AB16 AB16

SCAN_BLK1/OPC_OUT OPT
C104 C106 FRC_SPI_CZ
FRC_GPIO1
FRC_SPI1_CK
AA14
AC15
FRC_SPI_CZ
FRC_GPIO1
FRC_SPI1_CK
AA14
AC15
FRC_SPI_CZ
FRC_GPIO1
FRC_SPI1_CK
AA14
AC15
FRC_SPI_CZ
FRC_GPIO1
FRC_SPI1_CK
AA14
AC15
8pF 8pF FRC_GPIO8

FRC_SPI_DO
Y16
AC16
FRC_GPIO8
FRC_SPI_DO
Y16
AC16
FRC_GPIO8
FRC_SPI_DO
Y16
AC16
FRC_GPIO8
FRC_SPI_DO
Y16
AC16
AE8 AC14 AE8 AC14 AE8 AC14 AE8 AC14
FRC_DDR3_NC/DDR2_DQM0 FRC_SPI1_DI FRC_DDR3_NC/DDR2_DQM0 FRC_SPI1_DI FRC_DDR3_NC/DDR2_DQM0 FRC_SPI1_DI FRC_DDR3_NC/DDR2_DQM0 FRC_SPI1_DI
OPT OPT Y11

Y19
FRC_VSYNC_LIKE FRC_SPI_CK
AA16
AA15
Y11
Y19
AA16
AA15
Y11
Y19
AA16
AA15
Y11
Y19
AA16
AA15
FRC_TESTPIN FRC_SPI_DI FRC_TESTPIN FRC_SPI_DI FRC_TESTPIN FRC_SPI_DI FRC_TESTPIN FRC_SPI_DI
Y10 Y10 Y10 Y10

FRC_I2CS_DA FRC_I2CS_DA FRC_I2CS_DA FRC_I2CS_DA
AA11 AA11 AA11 AA11
FRC_I2CS_CK FRC_I2CS_CK FRC_I2CS_CK FRC_I2CS_CK
AB15 AB15 AB15 AB15

FRC_PWM0 FRC_PWM0 FRC_PWM0 FRC_PWM0
AB14 AB14 AB14 AB14
FRC_PWM1 FRC_PWM1 FRC_PWM1 FRC_PWM1
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS GP3_Saturn7M Ver. 0.1
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. FLASH/EEPROM/GPIO 1
Copyright © 2010 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
+3.3V_Normal RSDS Power OPT +1.26V_VDDC +1.26V_VDDC
MODEL OPTION VDD_RSDS:88mA
VDDC 1.26V VDDC : 2026mA
MODEL OPTION
VDD_RSDS
100/120Hz LVDS
OPT
PIN NAME LOW HIGH
1K
1K
1K
1K
PIN NO.
FRC_H/W_OPT
1K
1K
1K
OPT_0 OPT_4
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
L213
10uF
10uF
10uF
BLM18PG121SN1D
DVB_T2
PHM_ON
NO_FRC : LOW LOW +2.5V_Normal

MODEL_OPT_0 G19 NO FRC FRC_HW_OPT
FHD
OPT
OPT
U3_INTERNAL : HIGH LOW

R206
R208
R211
R226
R294
R295
R214
U5_EXTERNALBOOT :HIGH HIGH L214
C275
C276
C228
MODEL_OPT_4 OPT OPT
C4006
C4011
C4013
C4019
C4024
E18 50/60Hz LVDS 100/120Hz LVDS reserved for FRC : LOW HIGH VDD33 BLM18PG121SN1D OPT OPT
C277
C280
C283
C292
C299
OPT 100 MODEL_OPT_1 C5 PHM_ON --> This option is only applied in EU. FRC C4005
R201 PHM_OFF
IF_AGC_SEL MODEL_OPT_0 In case of NON_EU, default value set LOW. 0.1uF
R202 BOOSTER_OPT100
LNA2_CTL MODEL_OPT_1 MODEL_OPT_2 F7 NON_DVB_T2 DVB_T2
R203 RF_SW_OPT 100
RF_SWITCH_CTL MODEL_OPT_2
R204 100 MODEL_OPT_3 HD FHD
MODEL_OPT_3 B6
R210 OPT 100 S7M-PLUS_DivX_MS10
MODEL_OPT_4 IC101
R213 OPT 0 MODEL_OPT_5 D18 Ready default
3D_GPIO_1 MODEL_OPT_5 -->In case of GP2, This port was used for GIP/NON_GIP
3D_SG 0
LGE107DC-RP
+1.26V_VDDC [S7M+ DIVX/MS10]
3D_GPIO_2 R216 MODEL_OPT_6 MODEL_OPT_6 F9 LCD OLED
3D_SG --> MODEL_OPT_5, MODEL_OPT_6
Normal Power 3.3V
50/60Hz LVDS
: Only 3D_SG GPIO OUTPUT CONTROL

1K
1K
1K
1K
R293 OPT 1K
1K
1K
NON_DVB_T2
+3.3V_Normal VDD33 H11 G18

PHM_OFF
VDDC_1 GND_1
NO_FRC
H12 H9
HD
OPT
VDD33_T/VDDP/U3_VD33_2:47mA VDDC_2 GND_2

L204 H13 H10
R207
R209
R212
R227
R297
VDDC_3 GND_3
R215
BLM18PG121SN1D H14 H18

VDDC_4 GND_4
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
H15 H19
0.1uF
0.1uF
0.1uF
Close to MSTAR DTV_IF VDDC_5 GND_5
C284 10uF
C293 10uF
C4001 10uF
J12 J10
R288 100 C257 0.1uF VDDC_6 GND_6
S7M-PLUS_DivX_MS10 R289 100 C258 0.1uF
IF_P_MSTAR J13 J17
IC101 IF_N_MSTAR VDDC_7 GND_7
C4020
C4007
C4012
C4014
C4031
J14 J18
C4025
C4043
C4044
LGE107DC-RP [S7M+ DIVX/MS10] OPT OPT VDDC_8 GND_8
OPT OPT J15 J19
C250 0.1uF R4002 47 TU_SIF VDDC_9 GND_9
J16 K9
C251 0.1uF R4003 47
1000pF
VDDC_10 GND_10
OPT
L18 K10
C264
F1 W2 VDDC_11 GND_11
TP201 ANALOG SIF K11
CK+_HDMI1 A_RXCP VIFP GND_12
F2 W1 AVDD_MEMPLL:24mA AU33:31mA FRC_AVDD:60mA H16 K12
CK-_HDMI1 A_RXCN VIFM TP202 Close to MSTAR MIU0VDDC A_DVDD GND_13
G2 +2.5V_Normal K19 K13
D0+_HDMI1 A_RX0P VDD33 AU33 FRC_AVDD MIU1VDDC
G3 V2 B_DVDD GND_14
K14
D0-_HDMI1 A_RX0N IP GND_15
H3 V1 L215 L221 L19 K15
D1+_HDMI1 A_RX1P IM FRC_VDDC_0 GND_16
G1 +3.3V_Normal BLM18PG121SN1D BLM18PG121SN1D
0.1uF
0.1uF
D1-_HDMI1 M18 K16
A_RX1N L227 FRC_VDDC_1 GND_17
H1 Y2 M19 K17
D2+_HDMI1 A_RX2P SSIF/SIFP BLM18PG121SN1D C4015 FRC FRC_VDDC_2 GND_18
H2 Y1 N18 K18
D2-_HDMI1 A_RX2N SSIF/SIFM 0.1uF
F5 FRC_VDDC_3 GND_19
C4023
C4040
OPT N19 L9
DDC_SDA_1 DDCDA_DA/GPIO24 C4064 Close to MSTAR FRC_VDDC_4 GND_20
F4 U3 R4019 N20 L10
DDC_SCL_1 DDCDA_CK/GPIO23 QP TP203 0.1uF FRC_VDDC_5 GND_21
E6 V3 1K P18 L11
HPD1 HOTPLUGA/GPIO19 QM TP204 R4020 FRC_VDDC_6 GND_22
FRC_VDD33_DDR:50mA P19 L12
10K FRC_LPLL:13mA FRC_MPLL:4mA FRC_VDDC_7 GND_23
D3 Y5 VDD33 P20 L13
CK+_HDMI2 B_RXCP IFAGC IF_AGC_MAIN VDD33 FRC_LPLL FRC_VDD33_DDR
C1 Y4 FRC_VDDC_8 GND_24
FRC L14
CK-_HDMI2 B_RXCN RF_TAGC TP205 AMP_SCL C4065 GND_25
D1 0.022uF L206 L222 Y12 L15
D0+_HDMI2 B_RX0P AMP_SDA TU/DEMOD_I2C BLM18PG121SN1D BLM18PG121SN1D FRCVDDC U3_DVDD_DDR GND_26
D2 U1 FULL_NIM R291 16V
0.1uF
0.1uF
0.1uF
22 L16
D0-_HDMI2 B_RX0N TGPIO0/UPGAIN DEMOD_SCL GND_27
E2 U2 FULL_NIM R292 22 L17
D1+_HDMI2 B_RX1P TGPIO1/DNGAIN DEMOD_SDA GND_28
E3 R3 J11 M9
D1-_HDMI2 B_RX1N TGPIO2/I2C_CLK TU_SCL FRC
F3 T3 OPT AVDD1P2 GND_29
C4016
C4041
C4045 1uF L7 M10
D2+_HDMI2 TU_SDA
C286
B_RX2P TGPIO3/I2C_SDA DVDD_NODIE GND_30
E1 M11
D2-_HDMI2 B_RX2N GND_31
D4 T2 C261 27pF M12
DDC_SDA_2 DDCDB_DA/GPIO26 XTALIN GND_32
E4 T1 AVDD2P5 H7 M13
R287
DDC_SCL_2 X201 VDD33_DVI:163mA

DDCDB_CK/GPIO25 XTALOUT AVDD2P5_ADC_1 GND_33
1M
D5 24MHz +3.3V_Normal VDD33_DVI AVDD_DMPLL J7 M14

HPD2 HOTPLUGB/GPIO20 C262 27pF AVDD2P5_ADC_2 GND_34
HDMI
J8 M15
AA2 G14 L207 L217 AVDD25_REF GND_35
BLM18PG121SN1D BLM18PG121SN1D M16
CK+_HDMI4 C_RXCP SPDIF_IN/GPIO177 LED_DRIVER_D/L_SDA GND_36
AA1 G13 R296 100 M17
CK-_HDMI4 C_RXCN SPDIF_OUT/GPIO178 SPDIF_OUT GND_37
AB1 AU25
0.1uF
C4002
0.1uF
C4008
0.1uF
C4017
0.1uF
C287 C288 L8 N10
D0+_HDMI4
C294
C_RX0P 10uF AVDD_AU25 GND_38
AA3 0.1uF N11
D0-_HDMI4 C_RX0N B/T USB GND_39
AB3 B7 N12
D1+_HDMI4 C_RX1P DM_P0 GND_40
AB2 A7 AVDD2P5 W15 N13
D1-_HDMI4 C_RX1N DP_P0 OPT
AC2 PVDD_1 GND_41
AVDD2P5 Y15 N14
D2+_HDMI4 C_RX2P AVDD_DMPLL/AVDD_NODIE:7.362mA PVDD_2 GND_42
AC1 AF17 N15
D2-_HDMI4 C_RX2N DM_P1 SIDE_USB_DM GND_43
AB4 AE17 AVDD25_PGA U8 N16
DDC_SDA_4 DDCDC_DA/GPIO28 DP_P1 SIDE_USB_DP AVDD25_PGA GND_44
AA4 N17
DDC_SCL_4 DDCDC_CK/GPIO27 SIDE USB GND_45
AC3 P10
HPD4 HOTPLUGC/GPIO21 GND_46
F14 AVDD_DMPLL M8 P11
I2S_IN_BCK/GPIO175 NEC_SDA AVDD_NODIE GND_47
A2 F13 P12
D_RXCP I2S_IN_SD/GPIO176 COMP2_DET GND_48
A3 F15 P13
D_RXCN I2S_IN_WS/GPIO174 NEC_SCL VDD33_DVI GND_49
B3 N9 P14
D_RX0P
A1
D_RX0N I2S_OUT_BCK/GPIO181
D20
AUD_SCK
Normal 2.5V P9
AVDD_DVI_1
AVDD_DVI_2
GND_50
GND_51
P15
I2S_I/F
B1 E20 AVDD2P5/ADC2P5:162mA N8 P16
D_RX1P I2S_OUT_MCK/GPIO179 AUD_MASTER_CLK_0 AVDD3P3_CVBS GND_52
B2 D19 AVDD_DMPLL P8 P17
D_RX1N I2S_OUT_SD/GPIO182 AUD_LRCH +2.5V_Normal AVDD2P5 AVDD2P5 AVDD2P5
C2 F18 AVDD_DMPLL GND_53
R10
D_RX2P I2S_OUT_SD1/GPIO183 LED_DRIVER_D/L_SCL GND_54
C3 E18 L211 R11
D_RX2N I2S_OUT_SD2/GPIO184 MODEL_OPT_4 GND_55
B4 D18 BLM18PG121SN1D AU33 T7 R12
DDCDD_DA/GPIO30 I2S_OUT_SD3/GPIO185 MODEL_OPT_5
0.1uF
0.1uF
C4 E19 AVDD_AU33 GND_56
U7 R13
C289 10uF
DDCDD_CK/GPIO29 I2S_OUT_WS/GPIO180 AUD_LRCK AVDD_EAR33 GND_57
E5 R14
HOTPLUGD/GPIO22 GND_58
D6 R15
CEC_REMOTE_S7 CEC/GPIO5
C4026
N1 C236 2.2uF VDD33 GND_59
C295
T9 R16
LINE_IN_0L SC1/COMP1_L_IN AVDD33_T GND_60
P3 C237 2.2uF R17
R4024 22 LINE_IN_0R SC1/COMP1_R_IN GND_61
G5 P1 C238 2.2uF R8 R18
AUDIO IN
DSUB_HSYNC R4025 22 HSYNC0 LINE_IN_1L AV_L_IN VDDP_1 GND_62

G6 P2 C239 2.2uF R9 T10
DSUB_VSYNC VSYNC0 LINE_IN_1R AV_R_IN +2.5V_Normal AU25 +2.5V_Normal AVDD25_PGA
R228 33 C204 0.047uF K1 P4 C4059 2.2uF VDDP_2 GND_63
T8 T11
DSUB_R+ RIN0P LINE_IN_2L SIDEAV_L_IN VDDP_3 GND_64
DSUB
R229 68 C205 0.047uF L3 P5 C4060 2.2uF L212 L219 T12

RIN0M LINE_IN_2R SIDEAV_R_IN BLM18PG121SN1D BLM18PG121SN1D GND_65
R230 33 C206 0.047uF K3 R6 C242 2.2uF T13
DSUB_G+ GIN0P LINE_IN_3L COMP2_L_IN
0.1uF
0.1uF
R231 68 C207 0.047uF K2 T6 GND_66
C243 2.2uF V20 T14
GIN0M LINE_IN_3R COMP2_R_IN FRC_VD33_2_1 GND_67
R232 33 C208 0.047uF J3 U5 C244 2.2uF W20 T15
DSUB_B+ BIN0P LINE_IN_4L PC_L_IN AU25:10mA AVDD25_PGA:13mA FRC_VD33_2_2 GND_68
R233 68 C209 0.047uF J2 V5 C245 2.2uF T16
BIN0M PC_R_IN
C4027
LINE_IN_4R VDD_RSDS GND_69
C210 1000pF J1 U6 C246
C296
2.2uF OPT U19 T17
10K
10K
R4026
R4023
SOGIN0 LINE_IN_5L FRC_AVDD_RSDS_1 GND_70

V6 C247 2.2uF OPT U20 T18
SCART1_RGB/COMP1 LINE_IN_5R
V19
FRC_AVDD_RSDS_2 GND_71
T19
G4 FRC_AVDD_RSDS_3 GND_72
U10
SC1_ID HSYNC1 GND_73
H6 U4 W19 U11
AUDIO OUT
SC1_FB VSYNC1 LINE_OUT_0L FRC_AVDD FRC_AVDD GND_74

R253 33 C211 0.047uF K5 W3 U18 U12
SC1_R+/COMP1_Pr+ RIN1P LINE_OUT_2L SCART1_Lout FRC_LPLL FRC_AVDD_LPLL GND_75
R254 68 C212 0.047uF K4 W4 TP207 T20 U13
RIN1M LINE_OUT_3L FRC_AVDD_MPLL GND_76
R255 C213 J4 V4
SC1_G+/COMP1_Y+
R256
33
68 C214
0.047uF
0.047uF K6
GIN1P LINE_OUT_0R
Y3
TP208 DDR3 1.5V FRC_VDD33_DDR Y14
GND_77
U14
U15
GIN1M LINE_OUT_2R SCART1_Rout
BLM18PG121SN1D
R257 33 0.047uF H4 W5 FRC_VDD33_DDR GND_78
C215 TP209 U16
SC1_B+/COMP1_Pb+ BIN1P LINE_OUT_3R GND_79
R258 68 C216 0.047uF J6 AVDD_DDR0 U17
BIN1M +1.5V_DDR
J5 R4 AVDD_DDR0:55mA AVDD_DDR1:55mA GND_80
C217 1000pF VDD33 V7
SC1_SOG_IN SOGIN1 MIC_DET_IN GND_81
R236 0 T5 C234 OPT 2.2uF R19 V8
0.1uF
MICCM AVDD_DDR0 AVDD_DDR0
C4046
0.1uF
AVDD_MEMPLL GND_82
L209
NON_EU R5 C235 2.2uF W14 V9

MICIN FRC_AVDD_MEMPLL GND_83
H5 OPT V10
HSYNC2 GND_84
R237 33 C218 0.047uF N3 T4 V11
COMP2
COMP2_Pr+ RIN2P AUCOM L202 GND_85
C285
R238 68 C219 0.047uF N2 AVDD_DDR0 D15 V12
C278
C281
C4018
C4022
RIN2M BLM18SG121TN1D OPT
0.1uF
0.1uF
C4003
0.1uF
C4009
0.1uF
C4028
0.1uF
C4032
0.1uF
C4038
0.1uF
C4036
0.1uF
AVDD_DDR0_D_1 GND_86
C4042
0.1uF
R239 M2 P7
C290
C297
33 C220 0.047uF D16 V13
10uF
10uF
10uF
10uF
COMP2_Y+ GIN2P VRM AVDD_DDR0_D_2 GND_87
R240 68 C221 0.047uF M1 C249 C253 C256 C263 E15 V14
GIN2M 4.7uF 1uF 0.1uF 10uF AVDD_DDR0_D_3 GND_88
R241 33 C222 0.047uF L2 R7 OPT OPT OPT OPT E16 V15
COMP2_Pb+ BIN2P VAG OPT
R242 68 C223 0.047uF L1 P6 AVDD_DDR0_D_4 GND_89
E17 V16
BIN2M VRP AVDD_DDR0_C GND_90
C224 1000pF M3 V17
BLM18PG121SN1D
CM2012F5R6KT
SOGIN2
R1 L203 5.6uH HEAD_PHONE
H/P OUT AVDD_DDR0 F16
GND_91
V18
C248 0.047uF HP_OUT_1L HP_LOUT +1.5V_FRC_DDR AVDD_DDR0 AVDD_DDR1_D_1 GND_92
R2 L205 5.6uH AVDD_DDR_FRC:55mA F17 W7
HP_OUT_1R HP_ROUT AVDD_DDR1_D_2 GND_93
R244 33 C225 0.047uF N4 HEAD_PHONE G16 W8
CM2012F5R6KT
4.7uF
4.7uF
TU_CVBS CVBS0P AVDD_DDR1_D_3
R4014
1/16W
GND_94
C268
C272
R245 33 C226 0.047uF N6 AVDD_DDR_FRC MVREF G17 W9

HEAD_PHONE
L210
SC1_CVBS_IN CVBS1P
FRC
R246 33 C227 0.047uF L4 E21 AVDD_DDR1_D_4 GND_95
1K
1%
HEAD_PHONE H17 W10
ET_RXD0
CVBS In/OUT
AV_CVBS_IN CVBS2P ET_RXD0 AVDD_DDR1_C GND_96

R4016 33 C4057 0.047uF L5 E22 W11
SIDEAV_CVBS_IN CVBS3P ET_TXD0 ET_TXD0 GND_97
R248 33 C229 0.047uF L6 W12
FRC
FRC
FRC
OPT
C4004 OPT
C4010 FRC
Delete CHB_CVBS_IN
C240 FRC
CVBS4P
R4015
1/16W
R249 33 C230 0.047uF M4 D21 AVDD_DDR_FRC GND_98
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
AB11 W13
0.1uF
C241
AV_CVBS_IN2 CVBS5P ET_RXD1 ET_RXD1 FRC_AVDD_DDR_D_1 GND_99
10uF
10uF
R250 33 C231 0.047uF M5 F21

1K
1% AB12 W16
ET_TXD1
C279
C282
C291
C298
C203 CVBS6P ET_TXD1 FRC_AVDD_DDR_D_2 GND_100

R251 33 C232 0.047uF K7 AC11 W17
1000pF CVBS7P FRC_AVDD_DDR_D_3 GND_101
E23 AC12 W18
OPT ET_REFCLK ET_REF_CLK FRC_AVDD_DDR_D_4 GND_102
M6 D22 AA12 Y13
TP210 CVBS_OUT1 ET_TX_EN ET_TX_EN FRC_AVDD_DDR_C GND_103
DTV/MNT_VOUT M7 F22 Y18
CVBS_OUT2 ET_MDC
D23
ET_MDC GND_104
AA13
R252 68 C233 0.047uF N5
ET_MDIO
F23
ET_MDIO RSDS Power OPT GND_105
AB13
VCOM0 ET_CRS ET_CRS +1.26V_VDDC GND_106
AC13
MIU0VDDC MVREF GND_107
Close to MSTAR +1.26V_VDDC FRCVDDC G15 D17
F8 FRC MVREF GND_108
TP206 L228 H23
AVLINK OPT GND_109
G8 R298 100 BLM18SG700TN1D L225 AF13
IRINT IR BLM18SG700TN1D GND_110
K8 Y7 J9 L223
0.1uF
TESTPIN NC_1 GND_FU

0.1uF
A4 MIU1VDDC U9 BLM18SG121TN1D
C4066 10uF
Y8
SOC_RESET
C4061 10uF
AV_CVBS_IN2 RESET NC_2 PGA_VCOM

Y17 FRC L226
TP211 U3_RESET +3.3V_Normal
R205 BLM18SG700TN1D
0.1uF
FRC
C4062
FRC
R4006
C4063 10uF
C4058
10K
FRC
22 10K
FRC_RESET
R4018
C4056
R4017
10K
OPT
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS GP2R 20101023
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN2, HW OPT 2
EAN61829001 EAN61857101
EAN61857201
IC301-*3
IC301-*2
K4B1G1646G-BCH9 IC301-*4
H5TQ1G63DFR-PBC
NT5CB64M16DP-CF
FRC_DDR_1600_HYNIX FRC_DDR_1333_SS_NEW
N3 M8 FRC_DDR_1333_NANYA_NEW
N3 M8 A0 VREFCA
A0 VREFCA P7 N3 M8
P7 A1 A0 VREFCA
A1 P3 P7
P3 A2 A1
A2 N2 H1 P3
N2 H1 A3 VREFDQ A2
A3 VREFDQ P8 N2 H1
P8 A4 A3 VREFDQ
A4 P2 P8
P2 A5 A4
A5 R8 L8 P2
R8 L8 A6 ZQ A5
A6 ZQ R2 R8 L8
R2 A7 A6 ZQ
A7 T8 R2
VCC1.5V_U3_DDR T8 A8 A7
DDR3 1.5V By CAP - Place these Caps near Memory VCC1.5V_U3_DDR A8 R3 B2 T8
R3 B2 A9 VDD_1 A8
A9 VDD_1 L7 D9 R3 B2
+1.5V_FRC_DDR L7 D9 A10/AP VDD_2 A9 VDD_1
A10/AP VDD_2 R7 G7 L7 D9
R7 G7 A11 VDD_3 A10/AP VDD_2
A11 VDD_3 N7 K2 R7 G7
N7 K2 A12/BC VDD_4 A11 VDD_3
L301 A12/BC VDD_4 T3 K8 N7 K2
T3 K8 A13 VDD_5 A12 VDD_4
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
N1 T3 K8
C301
10uF
C315
A13 VDD_5
C303
C305
C306
C307
C308
C309
C310
C311
C313
C316
C317
C318
C319
C320
C321
C322
C323
N1 VDD_6 NC_6 VDD_5
C324 C325 VDD_6 M7 N9 N1
10uF M7 N9 NC_5 VDD_7 VDD_6
0.1uF A15 VDD_7 R1 M7 N9
OPT 10V 16V R1 VDD_8 NC_5 VDD_7
VDD_8 M2 R9 R1
M2 R9 BA0 VDD_9 VDD_8
BA0 VDD_9 N8 M2 R9
Close to DDR Power Pin N8 BA1 BA0 VDD_9
BA1 M3 N8
M3 BA2 BA1
BA2 A1 M3
A1 VDDQ_1 BA2
VDDQ_1 J7 A8 A1
J7 A8 CK VDDQ_2 VDDQ_1
CK VDDQ_2 K7 C1 J7 A8
K7 C1 CK VDDQ_3 CK VDDQ_2
CK VDDQ_3 K9 C9 K7 C1
K9 C9 CKE VDDQ_4 CK VDDQ_3
CKE VDDQ_4 D2 K9 C9
D2 VDDQ_5 CKE VDDQ_4
VCC1.5V_U3_DDR VDDQ_5 L2 E9 D2
VCC1.5V_U3_DDR L2 E9 CS VDDQ_6 VDDQ_5
CS VDDQ_6 K1 F1 L2 E9
K1 F1 ODT VDDQ_7 CS VDDQ_6
ODT VDDQ_7 J3 H2 K1 F1
J3 H2 RAS VDDQ_8 ODT VDDQ_7
RAS VDDQ_8 K3 H9 J3 H2
R301
1K 1%
K3 H9
R304
1K 1%
CAS VDDQ_9 RAS VDDQ_8

S7M-PLUS_DivX_MS10 L3
CAS VDDQ_9 L3
WE
K3
CAS VDDQ_9
H9
WE J1 L3
J1 NC_1 WE
C-MVREFDQ IC101 NC_1 T2 J9 J1
0.1uF
C-MVREFCA
1000pF
T2 J9 RESET NC_2 NC_1

0.1uF
1000pF
1%
LGE107DC-RP [S7M+ DIVX/MS10] L1 T2 J9

1%
RESET NC_2
L1
R302
NC_3 RESET NC_2

R305
NC_3 L9 L1
L9 NC_4 NC_3
C304
F3 T7 L9
1K
NC_4
C302
C314
1K
AR301 F3 T7
C312
DQSL NC_6 NC_4

AE1 W26 DQSL NC_6 G3 F3 T7
C-MA9 C-TMA9 C-TMA0 FRC_DDR3_A0/DDR2_NC ACKP/RLV3P/RED[3] RXBCK+ G3 DQSL DQSL NC_7
AF16 W25 DQSL G3
C-MA2 C-TMA2 C-TMA1 FRC_DDR3_A1/DDR2_A6 ACKM/RLV3N/RED[2] RXBCK- DQSL
AF1 U26 C7 A9
C-MA0 C-TMA0 C-TMA2 FRC_DDR3_A2/DDR2_A7 A0P/RLV0P/RED[9] RXB0+ C7 A9 DQSU VSS_1
AE3 U25 DQSU VSS_1 B7 B3 C7 A9
C-MBA2 C-TMBA2 C-TMA3 FRC_DDR3_A3/DDR2_A1 A0M/RLV0N/RED[8] RXB0- B7 B3 DQSU VSS_2 DQSU VSS_1
AD14 U24 DQSU VSS_2 E1 B7 B3
22 C-TMA4 RXB1+ E1
CLose to DDR3 CLose to Saturn7M IC AR302 AD3
FRC_DDR3_A4/DDR2_CASZ A1P/RLV1P/RED[7]
V26 VSS_3 E7
VSS_3
G8
DQSU VSS_2
E1
C-TMA5 FRC_DDR3_A5/DDR2_A10 A1M/RLV1N/RED[6] RXB1- E7 G8 DML VSS_4 VSS_3
C-MA8 C-TMA8 AF15 V25 DML VSS_4 D3 J2 E7 G8
C-TMA6 FRC_DDR3_A6/DDR2_A0 A2P/RLV2P/RED[5] RXB2+ D3 J2 DMU VSS_5 DML VSS_4
C-MA6 C-TMA6 AF2 V24 DMU VSS_5 J8 D3 J2
C-TMA7 FRC_DDR3_A7/DDR2_A5 A2M/RLV2N/RED[4] RXB2- J8 VSS_6 DMU VSS_5
C-MA4 C-TMA4 AE15 W24 VSS_6 E3 M1 J8
C-TMA8 FRC_DDR3_A8/DDR2_A2 A3P/RLV4P/RED[1] RXB3+ E3 M1 DQL0 VSS_7 VSS_6
EAN61828901 C-MBA1 C-TMBA1 AD2 Y26 DQL0 VSS_7 F7 M9 E3 M1
C-TMA9 FRC_DDR3_A9/DDR2_A9 A3M/RLV4N/RED[0] RXB3- F7 M9 DQL1 VSS_8 DQL0 VSS_7
IC301 22 AD16 Y25 DQL1 VSS_8 F2 P1 F7 M9
C-TMA10 FRC_DDR3_A10/DDR2_A11 A4P/RLV5P/GREEN[9] RXB4+ F2 P1 DQL2 VSS_9 DQL1 VSS_8
H5TQ1G63DFR-H9C AR303 AD15 Y24 DQL2 VSS_9 F8 P9 F2 P1
C-TMA11 FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8] RXB4- F8 P9 DQL3 VSS_10 DQL2 VSS_9
C-MA10 C-TMA10 AE16 DQL3 VSS_10 H3 T1 F8 P9
C-TMA12 FRC_DDR3_A12/DDR2_A8 H3 T1 DQL4 VSS_11 DQL3 VSS_10
FRC_DDR_1333_HYNIX C-MA12 C-TMA12 DQL4 VSS_11 H8 T9 H3 T1
H8 T9 DQL5 VSS_12 DQL4 VSS_11
M8 N3 C-MA1 C-TMA1 AC26 DQL5 VSS_12 G2 H8 T9
C-MVREFCA C-MA0 BCKP/TCON13/GREEN[1] RXACK+ G2 DQL6 DQL5 VSS_12
VREFCA A0 AC25 DQL6 H7 G2
P7 C-MA11 C-TMA11 RXACK- H7
A1 C-MA1 BCKM/TCON12/GREEN[0] DQL7 DQL6
P3 22 AA26 DQL7 B1 H7
C-MA2 B0P/RLV6P/GREEN[7] RXA0+ B1 VSSQ_1 DQL7
A2 AF3 AA25 VSSQ_1 D7 B9 B1
H1 N2 AR304 C-TMBA0 FRC_DDR3_BA0/DDR2_BA2 RXA0- D7 B9 DQU0
C-MVREFDQ VREFDQ A3 C-MA3 B0M/RLV6N/GREEN[6] VSSQ_2 VSSQ_1
P8 C-MA3 C-TMA3 AF14 AA24 DQU0 VSSQ_2 C3 D1 D7 B9
C-MA4 C-TMBA1 FRC_DDR3_BA1/DDR2_ODT B1P/RLV7P/GREEN[5] RXA1+ C3 D1 DQU1 VSSQ_3 DQU0 VSSQ_2
A4 AD1 AB26 DQU1 VSSQ_3 C8 D8 C3 D1
P2 C-MA5 C-TMA5 C-TMBA2 RXA1- C8 D8
R303 A5 C-MA5 FRC_DDR3_BA2/DDR2_A12 B1M/RLV7N/GREEN[4] DQU2 VSSQ_4 DQU1 VSSQ_3
L8 R8 C-MA7 C-TMA7 AB25 DQU2 VSSQ_4 C2 E2 C8 D8
C-MA6 B2P/RLV8P/GREEN[3] RXA2+ C2 E2 DQU3 VSSQ_5 DQU2 VSSQ_4
ZQ A6 AD13 AB24 DQU3 VSSQ_5 A7 E8 C2 E2
240 R2 C-MRESETB C-TMRESETB C-TMCK RXA2- A7 E8
A7 C-MA7 FRC_DDR3_MCLK/DDR2_MCLK B2M/RLV8N/GREEN[2] DQU4 VSSQ_6 DQU3 VSSQ_5
1% T8 22 AE14 AC24 DQU4 VSSQ_6 A2 F9 A7 E8
C-MA8 C-TMCKE FRC_DDR3_CKE/DDR2_RASZ B3P/TCON11/BLUE[9] RXA3+ A2 F9 DQU5 VSSQ_7 DQU4 VSSQ_6
A8 AE13 AD26 DQU5 VSSQ_7 B8 G1 A2 F9
B2 R3 R307 C-TMCKB RXA3- B8 G1
VDD_1 A9 C-MA9 FRC_DDR3_MCLKZ/DDR2_MCLKZ B3M/TCON10/BLUE[8] DQU6 VSSQ_8 DQU5 VSSQ_7
D9 L7 C-MCK C-TMCK AD25 DQU6 VSSQ_8 A3 G9 B8 G1
C-MA10 22 B4P/TCON9/BLUE[7] RXA4+ A3 G9 DQU7 VSSQ_9 DQU6 VSSQ_8
VDD_2 A10/AP AD24 DQU7 VSSQ_9 A3 G9
G7 R7 R308 RXA4- DQU7
VDD_3 A11 C-MA11 B4M/TCON8/BLUE[6] VSSQ_9
K2 N7 AE4
C-MCKB C-TMCKB C-TMODT FRC_DDR3_ODT/DDR2_BA1
VDD_4 A12/BC C-MA12 22 AD5
K8 T3 C-TMRASB FRC_DDR3_RASZ/DDR2_WEZ
VDD_5 A13 R309 AF4 AD23
N1 C-TMCASB FRC_DDR3_CASZ/DDR2_CKE RXCCK+
VDD_6 CCKP/LLV3P
N9 M7 C-MCKE C-TMCKE AD4 AE23
22 C-TMWEB FRC_DDR3_WEZ/DDR2_BA0 CCKM/LLV3N RXCCK-
VDD_7 NC_5 AE26
R1 RXC0+
VDD_8 R310 C0P/LLV0P/BLUE[5]
R9 M2 AE2 AE25
VCC1.5V_U3_DDR C-MBA0 C-MRASB C-TMRASB C-TMRESETB FRC_DDR3_RESETB/DDR2_A3 C0M/LLV0N/BLUE[4] RXC0-
VDD_9 BA0 22 AF26
N8 RXC1+
BA1 C-MBA1 C1P/LLV1P/BLUE[3]
M3 AR305 AF25
C-MBA2 C1M/LLV1N/BLUE[2] RXC1-
BA2 AF8 AE24
A1 C-MCASB C-TMCASB C-TMDQSL RXC2+
VDDQ_1 C-MCK FRC_DDR3_DQSL/DDR2_DQS0 C2P/LLV2P/BLUE[1]
A8 J7 C-MODT C-TMODT AD9 AF24
R306
150
C-TMDQSLB FRC_DDR3_DQSLB/DDR2_DQSB0 C2M/LLV2N/BLUE[0] RXC2-

OPT
VDDQ_2 CK AF23
C1 K7 C-MWEB C-TMWEB RXC3+
VDDQ_3 CK C3P/LLV4P
C9 K9 C-MBA0 C-TMBA0 AE9 AD22
C-MCKB C-TMDQSU FRC_DDR3_DQSU/DDR2_DQS1 C3M/LLV4N RXC3-
VDDQ_4 CKE 22 AF9 AE22
D2 C-TMDQSUB FRC_DDR3_DQSUB/DDR2_DQSB1 RXC4+
VDDQ_5 C-MCKE C4P/LLV5P
E9 L2 R311 AF22
CS C4M/LLV5N RXC4- +3.3V_Normal
VDDQ_6 AE11
L/DIM_EDGE_32/37
F1 K1 C-MDQSL C-TMDQSL
C-MODT 22 C-TMDML FRC_DDR3_DML/DDR2_DQ7 <U3 CHIP Config>
VDDQ_7 ODT AF6
H2 J3 R312 C-TMDMU
VDDQ_8 RAS C-MRASB FRC_DDR3_DMU/DDR2_DQ11
H9 K3 C-MDQSLB C-TMDQSLB AD19 (FRC_CONF0)
C-MCASB DCKP/TCON5 RXDCK+
R336
VDDQ_9 CAS 22
R340
R338
AE6 AE19
R342
L3 VCC1.5V_U3_DDR C-TMDQL0 RXDCK- HIGH : I2C ADR = B8
OPT
C-MWEB R313 FRC_DDR3_DQL0/DDR2_DQ6 DCKM/TCON4
1K
WE R333
LVDS_EXT_URSA5 1K
OPT 1K
AF11 AD21
1K
J1 10K C-TMDQL1 RXD0+ LOW : I2C ADR = B4
NC_1 C-MDQSU C-TMDQSU FRC_DDR3_DQL1/DDR2_DQ0 D0P/LLV6P
J9 T2 22 AD6 AE21
C-TMDQL2 FRC_DDR3_DQL2/DDR2_DQ1 D0M/LLV6N RXD0-
L1
NC_2 RESET C-MRESETB R314 AD12 AF21 (FRC_CONF1,FRC_PWM1, FRC_PWM0)
C-MDQSUB C-TMDQSUB C-TMDQL3 FRC_DDR3_DQL3/DDR2_DQ2 D1P/LLV7P RXD1+
NC_3 AE5 AD20 FRC_MODEL_OPT_0 3’d5 : boot from internal SRAM
L9 22 C-TMDQL4 FRC_DDR3_DQL4/DDR2_DQ4 RXD1-
NC_4 D1M/LLV7N 3’d6 : boot from EEPROM
T7 F3 AF12 AE20 FRC_MODEL_OPT_1
R315 C-TMDQL5 FRC_DDR3_DQL5/DDR2_NC D2P/LLV8P RXD2+ 3’d7 : boot form SPI flash
NC_6 DQSL C-MDQSL AF5 AF20
G3 C-MDMU C-TMDMU C-TMDQL6 RXD2-
DQSL C-MDQSLB 22 FRC_DDR3_DQL6/DDR2_DQ3 D2M/LLV8N FRC_MODEL_OPT_2
AE12 AF19
C-TMDQL7 FRC_DDR3_DQL7/DDR2_DQ5 D3P/TCON3 RXD3+
A9 C7 AR306 AD18 2D/3D_CTL +3.3V_Normal
L/DIM_EDGE_42/47/55
C-MDQSU D3M/TCON2 RXD3-
VSS_1 DQSU C-MDQL7 C-TMDQL7 AE10 AE18
R341
R339
B3 B7
R337
R343
C-TMDQU0 FRC_DDR3_DQU0/DDR2_DQ8 D4P/TCON1 RXD4+
OPT
VSS_2 DQSU C-MDQSUB C-MDQL3 C-TMDQL3 AF7 AF18
E1 C-TMDQU1 FRC_DDR3_DQU1/DDR2_DQ14 RXD4-
VSS_3 D4M/TCON0
1K
1K
C-MDQL1 C-TMDQL1 AD11
1K
1K
R322
G8 E7
R321
R323
C-TMDQU2
R320
VSS_4 DML C-MDML FRC_DDR3_DQU2/DDR2_DQ13
C-MDML C-TMDML AD7
OPT1K
J2 D3
1K
1K
C-TMDQU3
FRC 1K
C-MDMU FRC_DDR3_DQU3/DDR2_DQ12
LVDS_S7M-PLUS
VSS_5 DMU 22 AD10 AB22
J8 C-TMDQU4 FRC_DDR3_DQU4/DDR2_DQ15 FRC_MODEL_OPT_0
VSS_6 AR307 GPIO0/TCON15/HSYNC/VDD_ODD
S7M-PLUS
FRC
M1 E3 AE7 AB23
C-MDQL0 C-TMDQU5 FRC_DDR3_DQU5/DDR2_DQ9 GPIO1/TCON14/VSYNC/VDD_EVEN FRC_MODEL_OPT_1
VSS_7 DQL0 C-MDQL0 C-TMDQL0 AF10 AC23
M9 F7 C-TMDQU6 FRC_MODEL_OPT_2 FRC_CONF0
VSS_8 DQL1 C-MDQL1 C-MDQL2 C-TMDQL2 FRC_DDR3_DQU6/DDR2_DQ10 GPIO2/TCON7/LDE/GCLK4
P1 F2 AD8 AC22
C-MDQL2 C-TMDQU7 FRC_DDR3_DQU7/DDR2_DQM1 GPIO3/TCON6/LCK/GCLK2 2D/3D_CTL FRC_CONF1
VSS_9 DQL2 C-MDQL6 C-TMDQL6
P9 F8
VSS_10 DQL3 C-MDQL3 C-MDQL4 C-TMDQL4 FRC_PWM1
T1 H3
VSS_11 DQL4 C-MDQL4 22 AB16
T9 H8 FRC_PWM0
VSS_12 DQL5 C-MDQL5 R316 FRC_SPI_CZ FRC_/SPI_CS
G2 AA14
FRC_CONF0
R324
R325
C-MDQL5 C-TMDQL5 FRC_GPIO1
R318
C-MDQL6
R319
DQL6 AC15
H7 22 R300 33
DQL7 C-MDQL7 FRC_SPI1_CK L/DIM_SCLK
B1 FRC_L/DIM
OPT 1K
1K
AR308
FRC 1K
OPT1K
VSSQ_1 Y16
B9 D7 C-MDQU2 C-TMDQU2 FRC_CONF1
C-MDQU0 FRC_GPIO8
S7M-R
VSSQ_2 DQU0 FRC_L/DIM AC16
D1 C3 C-MDQU6 C-TMDQU6 33 R332
VSSQ_3 DQU1 C-MDQU1 FRC_SPI_DO FRC_SPI_SDO
D8 C8 V_SYNC AE8 AC14 R348 33
C-MDQU0 C-TMDQU0 FRC_DDR3_NC/DDR2_DQM0 FRC_SPI1_DI L/DIM_MOSI
VSSQ_4 DQU2 C-MDQU2
E2 C2 C-MDQU4 C-TMDQU4 R317 FRC_L/DIM
VSSQ_5 DQU3 C-MDQU3 820 Y11 AA16
E8 A7 22
VSSQ_6 DQU4 C-MDQU4 FRC_VSYNC_LIKE FRC_SPI_CK FRC_SPI_SCK
F9 A2 AR309 S7M-R Y19 AA15
VSSQ_7 DQU5 C-MDQU5 FRC_TESTPIN FRC_SPI_DI FRC_SPI_SDI
G1 B8 C-MDQU7 C-TMDQU7
VSSQ_8 DQU6 C-MDQU6 Y10 R326 22
G9 A3 C-MDQU1 C-TMDQU1 R317-*1 FRC
C-MDQU7 FRC_I2CS_DA I2C_SDA
VSSQ_9 DQU7 4.7K AA11 R331 22
C-MDQU5 C-TMDQU5 FRC I2C_SCL
FRC_I2CS_CK
C-MDQU3 C-TMDQU3 S7M-PLUS
R335 22
22 AB15 FRC_SCL
FRC_PWM0 FRC_PWM0 OPT
AB14
FRC_PWM1 FRC_PWM1
FRC_SDA +3.3V_Normal
R334 22
OPT +3.3V_Normal
R349 S7M-PLUS_S_FLASH_2MBIT_WIN
S7M-PLUS 10K IC302
R350
4.7K
R344 W25X20BVSNIG
0
3D_SYNC_RF S7M-PLUS
OPT
3D_SG R329
10 CS VCC
FRC_/SPI_CS 1 $ 0.17 8
R330
10 DO HOLD
FRC_SPI_SDO 2 7
S7M-PLUS S7M-PLUS
R328
WP CLK 10
3 6 FRC_SPI_SCK
R327
GND DIO 10
4 5
FRC_SPI_SDI
S7M-PLUS

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. FRC_DDR 3
ST_3.5V--> 3.375V --> 3.46V
+12V/+15V
20V-->3.51V --> 3.76V (3.59V)
+12V/+15V +3.5V_ST +3.5V_ST -> 3.375V
FROM LIPS & POWER B/D PANEL_POWER 24V-->3.78V --> 3.92V (3.79V)
12V -->3.58V --> 3.82V (3.68V)
+3.5V_ST
L412
R488
18.5V-->3.5V --> 3.75V (3.59V) 100K
PD_+3.5V
PD_+12V
R463
10K
OPT
R450
R448
2.7K
R405-*1 R407-*1 IC408
5%
1%
0
3K 3K NCP803SN293
0.01uF C438 C442
0.015uF C409
0.015uF C436 0.1uF 10uF New item PANEL_DISCHARGE_RES R402 POWER_DET
0.01uF 16V 16V PANEL_DISCHARGE_RES VCC RESET 100
50V 25V 3 2
OPT Q409
PD_+12V
+3.5V_ST
1.21K
1/10W
RT1P141C-T112 AO3407A 1
R447
Q402 C474
1%
C411 GND PWR_DET_ON_SEMI
PANEL_VCC 0.1uF 0.1uF
R439
33K
C443 16V
R406 1 3
4.7K 10uF
NORMAL_EXPEPT_32 NORMAL_32 G
R401 C P403 L407-*1 25V
2 P404
RL_ON 10K FW20020-24S FM20020-24 CIS21J121 +24V R404
B Q401 R431 C451 +24V PD_+12V
R440
5.6K
2SC3052 22K 0.1uF
100K
L404-*1 L407 50V
E PWR ON 1 24V 1608 IC409
R482
8.2K
CIS21J121 2 MLB-201209-0120P-N2 OPT
1%
24V 24V OPT C POWER_+24V NCP803SN293 PD_+12V
3 4
R430
+3.5V_ST GND 5 6 GND 10K R480
L404 C418 C426 B Q407 R407 100
GND GND R405 VCC 3 2 RESET
MLB-201209-0120P-N2 7 8 0.1uF 68uF 2SC3052 C455 2.2K 2.2K
3.5V 3.5V 50V 35V 0.1uF
R403
1.5K
9 10 C 1
E
1%
R429 R435 16V C412 POWER_+24V
3.5V 11 12 3.5V 47K GND
C401 PANEL_CTL B Q406 22K OPT 0.1uF PD_+12V_PWR_DET_ON_SEMI
C406 C408 GND GND
100uF 13 14 2SC3052 16V
0.1uF 0.1uF PD_+12V
16V 16V 16V GND 15 16 GND/V-sync 1:AK10 OPT
E
+12V/+15V
OPT 12V
12V
12V
17
19
18
20
INV ON
A.DIM
P.DIM1 +3.3V_Normal
Power_DET
21 22
L402 GND/P.DIM2 Err OUT
MLB-201209-0120P-N2 23 24
+3.5V_ST
POWER_16_GND
R419
1K
S7M DDR 1.5V
0
C402
100uF
16V
C404
0.1uF
16V
C407
0.1uF
16V
OPT
25
POWER_18_INV_CTL
R415
100 R426
10K OPT POWER_ON/OFF1 1074 mA +3.3V_Normal +3.3V_Normal
R412
POWER_23_GND
L402-*1 SLIM_32~52
10K
R464
P401 R425
CIS21J121 100 +12V/+15V
SMAW200-H24S2 C
IC405
POWER_24_GND
R418 R421
R476
C475 1934 mA
POWER_24_INV_CTL B 10K INV_CTL
6.8K AOZ1073AIL-3
0
R475
L416
OPT Q405 0.1uF L424
+3.5V_ST 16V C462 +1.5V_DDR L421
2SC3052
0
E R427 CIC21J501NE
0.1uF PGND LX_2 3.6uH
10K
POWER_18_A_DIM 1 8
OPT
EP[GND]
R451 0 NR8040T3R6N
16V
VIN_3
PWRGD
BOOT
POWER_22_A_DIM VIN LX_1
L420
R460
R485 0 2 7
EN
1%
27K
C492
POWER_20_A_DIM A_DIM
0.1uF
L423 AGND 3A EN POWER_ON/OFF2_2 C469 C473 C485
16
15
14
13
0 16V
POWER_20_PWM_DIM R453 3.6uH 3 6 R1
4.7K
VIN_1 PH_3 22uF 0.1uF 0.1uF
1%
R461
1 12 R456 16V
POWER_24_PWM_DIM R484 PWM_DIM C457 C459 10K 16V 16V
0 THERMAL 10uF
R472 0 VIN_2 2 11 PH_2 NR8040T3R6N 10uF FB COMP
C461 C468 17 C470 25V 4 5
25V OPT
10uF 0.1uF C472 C476 0.1uF
R471 0 PWM_PULL-DOWN_3.9K
GND_1 3 IC407 10 PH_1 12K C423
POWER_22_PWM_DIM 10V 16V 22uF 22uF 16V 2200pF
R606 TPS54319TRE R454 100pF
3.9K C465 10V 10V C464
OPT C416 R606-*1 GND_2 4 9 SS/TR 50V
0.1uF 1K
0.01uF
47K 1%
16V PWM_PULL-DOWN_1K C463
8
50V
R457
R462
100pF
1%
10K
R1 50V
AGND
VSENSE
COMP
RT/CLK
R452
R2
+3.3V_Normal 1/16W 330K 5%
POWER_20_ERROR_OUT
R455 C467
R486
4.7K
R437 100
Vout=(1+R1/R2)*0.8
OPT
15K 4700pF
POWER_24_ERROR_OUT ERROR_OUT 1/16W 5% 50V

R2
R420 100
R449
56K
1/16W
3A $ 0.145 1%
<MODULE PIN MAP>

Vout=0.827*(1+R1/R2)=1.521V +5V_Normal
PIN No LGD(PSU) SHARP IPS-@
CMO10"Lamp AUO 10"Lamp OLP
TP5302
or LIPS (PSU) (PSU) (PSU) (PSU) +12V/+15V MAX 1A
IC406
16 GND GND GND GND AOZ1072AI-3
GND TP5303 V_SYNC
TP5304 +2.5V/+1.8V L422
L417
SCAN_BLK2
PGND LX_2 3.6uH
18 INV_ON A-DIM INV_ON INV_ON INV_ON TP5305 SCAN_BLK1/OPC_OUT 1 8
+3.3V_Normal NR8040T3R6N
52/60:ERROR OPC_OUT
TP5306 IC402 VIN LX_1
20 VBR-A NC Err_out Err_out +2.5V_Normal
R465
26/32HD:NC 2 7
1%
AZ2940D-2.5TRE1
24K
C490
26/32/52:PWM
22 PWM_DIM PWM_DIM NC 60:NC NC VIN 1 Vd=550mV3 VOUT
300 mA
0.1uF
16V
AGND
3
2A 6
EN POWER_ON/OFF2_2
R1
C471
22uF
1%
51K
R466
C458 C460 R459 C477
2 10K 16V
26/32/52:GND 10uF 10uF 0.1uF
R473
Err_out INV_ON PWM_DIM PWM_DIM GND FB COMP 16V

24 60:PWM C432 25V 25V 4 5
1
OPT
0.1uF 12K C427
16V 2200pF
R458 100pF
23 GND GND GND GND GND C466 50V
C403 C440
10uF 0.1uF
10V 16V
R467
1%
10K
<LED MODULE PIN MAP -> latest update 20100618> <Module Inv to Main Pin Connection> R2
32LE5300-TA 32LE4500-TA 32LE5300-TA Vout=0.8*(1+R1/R2)
PIN No LGD LPB/ CMO10"LED AUO 10"LED
LGD 10"LED INV <--> MAIN
OS LPB (PSU) (PSU) (PSU)
#11 <--> #24
16 NC NC NC NC #12 <--> #18
18 INV_ON INV_ON INV_ON INV_ON
#13 <--> #20
#14 <--> #22 +5V_TUNER
20 err_out err_out
NC NC IC410
+5V_Normal IC411
--> NC --> NC AP1117EG-13 AP1117EG-13
22 PWM_DIM NC NC PWM_DIM IN OUT IN OUT
err_out ADJ/GND R422 ADJ/GND

err_out 1 R424
24 --> NC PWM_DIM PWM_DIM --> NC 5% 1
5%
23 NC NC NC NC
S7M core 1.26V volt C491
0.1uF
50V
330
R411
110
R417
C414
0.1uF
16V
C415
10uF
C422
0.1uF 330
R409
110
R408 C417
0.1uF
C419
10uF
POWER_ON/OFF2_1 10V 50V
16V 10V
10K
R445
LGD edge led error-out use or not? checking is necessary...

C447
0.1uF
+5V_USB +5V_USB +3.5V_ST 16V

C441
0.1uF
+1.26V_VDDC C421,C422 Close to LDO
EP[GND]
+12V/+15V
VIN_3
PWRGD
IC401
BOOT
2000 mA 16V
L413
EN
AOZ1073AIL-3
L401
L406 L415
16
15
14
13
3.6uH 3.6uH
PGND LX_2 VIN_1 1 12 PH_3 +1.5V_DDR
1 8 +1.5V_FRC_DDR
THERMAL
NR8040T3R6N VIN_2 2 11 PH_2 NR8040T3R6N Q408
C430 C431 17 C444
VIN LX_1 10uF C453 C456 0.1uF AO3438
0.1uF
R414
2 7 GND_1 3 IC403 10 PH_1 FRC

1%
22uF 22uF
51K
C489 10V 16V 16V

22K 1% 24K 1%
S
OPT SN1007054RTER C488 10V 10V
0.1uF GND_2 SS
R442
16V AGND 3A EN POWER_ON/OFF2_1 C429 C420 C424 C428 4 9
4.7uF
3 6 R1
1.5K
100pF 0.1uF 0.01uF
R443
22uF 0.1uF
OPT
50V
C445
1%
R416
FRC 10K
R410
5
50V 16V 50V
G
C405 C410 10K 16V 16V 100pF
10uF 10uF FB COMP OPT C439 OPT C435
R1
AGND
VSENSE
COMP
RT/CLK
R444
25V 25V 4 5
R432 4.7uF
12K 1/16W 330K 5% 10V
2200pF
R413
C413 R436 C448
7.5K 3300pF
1/16W 5% 50V
R2
R423
POWER_ON/OFF2_1
1%
10K
R2
R441
75K
R434
120K
OPT
4A $ 0.165 1/8W
1%
Vout=(1+R1/R2)*0.8
Vout=0.8*(1+R1/R2)=1.29V
+1.5V_DDR_FRC
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. POWER_LARGE 4
CRYSTAL_KDS
X1002-*1
FLMD0
32.768KHz
S/T_SCL
S/T_SDA
15pF
15pF
10K
NEW_SUB +3.5V_ST
C1007
C1008
R4034
MICOM_RESET
4.7K
X1002
R1030
32.768KHz NEW_SUB
R4035
CRYSTAL_EPSON 4.7K
R1034
4.7M
CRYSTAL_KDS +3.5V_ST
47K
NEW_SUB
22
22
NEW_SUB
R1091 10K
R1046
R1060
R1043
P122/X2/EXCLK/OCD0B
for Debugger GND
MICOM_DEBUG_WAFER
TP1601
22
+3.5V_ST
P120/INTP0/EXLVI
P1001
12505WS-12A00
P124/XT2/EXCLKS
0.1uF
C1010
1
0.1uF
R1039
TOP SIDE for reset.
P121/X1/OCD0A
+3.5V_ST
2
MICOM_RESET TP1602
MICOM_DEBUG +3.5V_ST
R1076 22
C1006
3
NEC_ISP_Tx
4
MICOM_DEBUG
R1078 22
P123/XT1
5 NEC_ISP_Rx
6
R1047 20K
MICOM_DEBUG C1003
R1010 22 1/16W
7 0.1uF
FLMD0
RESET
OCD1A 1%
REGC
8
R1089
1/16W
MICOM_DEBUG
VDD
VSS
P40
P41
R1081 22 EDID_WP
20K
9
OCD1B
1%
C
10
MICOM_DEBUG B Q1001
11 R1013 22 2SC3052
FLMD0
12
MICOM_DEBUG
E
48
47
46
45
44
43
42
41
40
39
38
37
13
R1002 10K
R1018 22
P60/SCL0 1 36 P140/PCL/INTP6 R1048 22
NEC_SCL RL_ON
R1019 22
P61/SDA0 2 35 P00/TI000 R1049 22
NEC_SDA
OPT NEC CONFIGURATION OPT
+3.5V_ST +3.5V_ST
NEC_EEPROM_SCL
P62/EXSCL0 3 34 P01/TI010/TO00 R1050 10K
R1006 10K
NEC_ISP_Tx
OPT P63 4 33 P130 R1090 22
R1072 10K
NEC_ISP_Rx
OPT
R1084
NEC_EEPROM_SDA
P33/TI51/TO51/INTP4 IC1002 P20/ANI0
OPT
OPT
10K CEC_REMOTE_NEC
R1020 0
5 32 R1055 22
SCART1_MUTE
R1073 10K
OCD1A R1065 22 P75 6 uPD78F0514 31 ANI1/P21 R1056 22
OPT POWER_ON/OFF2_1 CEC_ON/OFF
R1005 10K P74 7 30 ANI2/P22 R1057 22

(MODEL_OPT_3)
OCD1B AMP_MUTE MODEL1_OPT_2
R1066 22 P73/KR3 NEC_MICOM ANI3/P23
AMP_RESET 8 29 POWER_ON/OFF1
(MODEL_OPT_0) R1023 22 P72/KR2 9 28 ANI4/P24 R1054 22 19-22_LAMP
SOC_RESET OLP
P71/KR1 10 27 ANI5/P25 R1052 10K
INV_CTL SIDE_HP_MUTE
EEPROM for Micom R1063 22 P70/KR0 11 26 ANI6/P26
+3.5V_ST PANEL_CTL KEY2
(MODEL_OPT_1)
P32/INTP3/OCD1B 12 25 ANI7/P27
IC1001-*1 OCD1B KEY1
IC1001 AT24C16BN-SH-B
13
14
15
16
17
18
19
20
21
22
23
24
M24C16-WMN6T
NC_1 VCC
NC/E0 VCC 1 8
1 8
P31/INTP2/OCD1A
P30/INTP1
P17/TI50/TO50
P16/TOH1/INTP5
P15/TOH0
P14/RXD6
P13/TXD6
P12/SO10
P11/SL10/RXD0
P10/SCK10/TXD0
AVREF
AVSS
R1014 2.7K
R1015 2.7K
R1001
47K
NC_2 WP
C1002
0.1uF
NC/E1 WC 2 7
2 7
TP1001
+3.5V_ST
NC_3 SCL
NC/E2 SCL TP1002 3 6
R1080
3 6 NEC_EEPROM_SCL
22
GND SDA
VSS SDA TP1003 4 5
R1008
4 5 NEC_EEPROM_SDA
22
C1009 1uF
EEPROM_NEC_16KBIT_ATMEL
EEPROM_NEC_16KBIT_STM
22
22
+3.5V_ST
R1041
R1037
+3.5V_ST
MICOM MODEL OPTION
PWM_BUZZ/IIC_LED
10K
10K
10K
10K
TOUCH_KEY
22
22
B/L_LED
GP2
R1079
R1075
R1009
R1071
R1069
R1068
AMP_RESET MODEL_OPT_0 R1083 10K
PANEL_CTL MODEL_OPT_1 OPT
MODEL1_OPT_2
CEC_ON/OFF MODEL_OPT_3
LED_R/BUZZ
LED_B/LG_LOGO
10K
10K
10K
10K
POWER_DET
IR
NEC_ISP_Rx
NEC_ISP_Tx
POWER_ON/OFF2_2
S7_NEC_RXD
S7_NEC_TXD
OCD1A
TACT_KEY
B/L_LAMP
PWM_LED
GP3
R1074
R1011
R1004
R1012
2011Y,GP2R, 101125 Update 2010Y,GP2

MODEL OPTION
MODEL OPTION MODEL_OPT_0 MODEL_OPT_1 MODEL_OPT_2 MODEL_OPT_3
MODEL_OPT_0 MODEL_OPT_1 MODEL_OPT_2 MODEL_OPT_3 Description
PIN NAME PIN NO. HIGH LOW LD350/450/550
PIN NAME PIN NO. HIGH LOW LK330/LK430 for KR/US LOW LOW LOW LOW
LOW LOW LOW LOW 10Y EYE-Q Sensor PWM LED & No Buzz & No LED Blink
KEY & PWM LED & No Buzz & No LED Blink MODEL_OPT_0 8 B/L_LED B/L_LAMP
MODEL_OPT_0 8 B/L_LED B/L_LAMP 19/22/26LE5300/5300
LK330/LK430/LK530 HIGH LOW HIGH LOW IIC LED & PWM IIC BUZZ
LOW LOW LOW HIGH PWM_LED
KEY & PWM LED & No Buzz & No LED Blink MODEL_OPT_1 11 PWM_BUZZ/IIC_LED
MODEL_OPT_1 11 PWM_BUZZ/IIC_LED PWM_LED HIGH HIGH HIGH LOW 32/37/42/47/55LE5300
LOW : LED HIGH LV25/LV35/LV45/LW45/LV55/LK45/LK55 IIC LED & PWM BUZZ
HIGH LOW
HIGH : LAMP S/T & IIC LED & NO BUZZ & LED Blink MODEL_OPT_2 30 TOUCH_KEY TACT_KEY
MODEL_OPT_2 30 TOUCH_KEY TACT_KEY LOW LD420
TBD LOW HIGH LOW IIC LED(09Y IIC Protocol) & No BUZZ
HIGH LOW LOW
IIC LED(09Y IIC Protocol) & No BUZZ MODEL_OPT_3 31 GPIO_LED NON_GPIO_LED
MODEL_OPT_3 31 GP2 LE7300
GP3 HIGH
Low LOW TBD PWM_BUZZ/IIC_LED : For model that use LED Lighting used IIC HIGH LOW LOW GPIO LED & NO BUZZ
HIGH
PWM_BUZZ/IIC_LED :Using IIC for LED Breathing & PWM Buzz S/T & IIC LED & No Buzz & LED Blink
PWM_LED : For model that use LED Lighting used PWM Signal
PWM_LED : Using PWM Signal for LED Lighting

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM Rev.4 5
CONTROL
IR & LED
+3.5V_ST
EYEQ/TOUCH_KEY
R2404 R2405 R2411
100 EYEQ/TOUCH_KEY OLD_SUB NEW_SUB
10K 10K
1% 1% NEC_EEPROM_SCL P2401 P2402
12507WR-12L 12507WR-15L
C2408 5.6V
18pF D2403
50V
L2401 OPT
R2401 BLM18PG121SN1D 1 1
100
KEY1 EYEQ/TOUCH_KEY
100 EYEQ/TOUCH_KEY
R2402 L2402 2 2
BLM18PG121SN1D D2402 NEC_EEPROM_SDA
100 5.6V
KEY2 R2412 C2409 5.6V
AMOTECH D2404
C2401 C2402 18pF
50V 3 3
0.1uF 0.1uF
D2401 OPT
5.6V
AMOTECH JP2407
4 4
+3.5V_ST
+3.5V_ST JP2408
5 5
L2403
BLM18PG121SN1D
+3.5V_ST 6 6
R2425
47K
R2428 OPT
22 +3.5V_ST R2413 1.5K
IR R2429 C2403 C2404 7 7
0.1uF 1000pF LED_B/LG_LOGO
47K 16V 50V OPT
R2430 OPT C2410
Q2406 C 10K 0.1uF JP2409
B R2426 16V 8 8
2SC3052
E OPT 47K
OPT R2431
C 47K JP2410
B 9 9
Q2405 E OPT
2SC3052 C2407
100pF D2405
OPT +3.3V_Normal 50V 5.6V 10 10
L2404
BLM18PG121SN1D
JP2411
R2427 11 11
0
R2414
LED_R/BUZZ 12 12
C2405 C2406 1.5K
0.1uF 1000pF OPT
16V 50V R2416 13
13
10K
14
15
16
S/T_SCL
NEW_SUB
C906 D902
18pF CDS3C05HDMI1
50V 5.6V
OPT
S/T_SDA
NEW_SUB
C907 D903
18pF CDS3C05HDMI1
50V 5.6V
OPT

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. IR/CONTROL-L 6
USB_DIODES
EAN61849601
IC1450
L1451-*1 AP2191DSG
CIS21J121
NC GND
8 1 +5V_USB
L1451
MLB-201209-0120P-N2 OUT_2 $0.077 IN_1
7 2
120-ohm
OUT_1 IN_2 C1452
C1453
R1458 R1459 6 3 10uF
2K 2K C1451 10V 0.1uF
1/8W 1/8W
1% 1% 22uF +3.3V_Normal
FLG EN
16V 5 4
R1455
4.7K
SIGN6409
OPT
USB_JACK USB1_CTL
3AU04S-305-ZC-(LG)
R1454
10K
USB_JACK_LV3400
R1451 47 USB1_OCD
JK1450-*1 JK1450
3AU04S-345-ZC-H-LG
1
USB DOWN STREAM
USB DOWN STREAM

2
SIDE_USB_DM
3
SIDE_USB_DP
4
D1451
5
RCLAMP0502BA
OPT

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. USB_OCP_DIODE 7
HDMI EEPROM
5V_HDMI_1 +5V_Normal
A2
A1
ENKMC2838-T112
D821
C
HDMI_1_RENESAS
5V_HDMI_1 5V_DET_HDMI_1 HDMI_1_ATMEL
HDMI_1 IC801-*1
R1EX24002ASAS0A
IC801
EDID_WP
AT24C02BN-SH-T
R874
10K
C A0 VCC A0 VCC
SHIELD 1 8 1 8
Q802 B R830
R896 2SC3052 HPD1 $0.055
20 10K A1 WP A1 WP C806 R884 R888
1K E 2 7 2 7
C802 0.1uF 2.7K 2.7K
19
R804 0.1uF
A2 SCL A2 SCL
16V 3 6
3.3K
18 3 6
1.8K DDC_SCL_1
R876 22
R802
17 VSS SDA GND SDA

DDC_SDA_1 4 5 4 5
16 DDC_SDA_1
R875 22
DDC_SCL_1
15
14 5V_HDMI_2 +5V_Normal
R824 0
HDMI_CEC
EAG59023302
13
CK-_HDMI1
A2
A1
12
HDMI_1
ENKMC2838-T112
11 D822
CK+
10 CK+_HDMI1
C
HDMI_2_RENESAS
D0- HDMI_2_ATMEL
9 D0-_HDMI1 IC802-*1 IC802
D0_GND R1EX24002ASAS0A AT24C02BN-SH-T EDID_WP
8
10K
R873
D0+
7 D0+_HDMI1
A0 VCC A0 VCC
D1- 1 8 1 8
6 D1-_HDMI1
D1_GND $0.055 C807 R885 R889
5 A1 WP A1 WP
2 7 2 7
D1+ 0.1uF 2.7K 2.7K
4 D1+_HDMI1
D2- A2 SCL A2 SCL JP810
3 D2-_HDMI1 3 6 3 6 DDC_SCL_2
D2_GND R878 22
2
VSS SDA GND SDA
D2+ 4 5 4 5 DDC_SDA_2
1 D2+_HDMI1
R877 22
OPT
D802
JK802
HDMI_2 5V_HDMI_2
SIDE_HDMI 5V_HDMI_4 +5V_Normal
5V_DET_HDMI_2
5V_HDMI_4 5V_DET_HDMI_4
A2
A1
C C ENKMC2838-T112
SHIELD R828 BODY_SHIELD HDMI_SIDE_RENESAS D824
10K R862
Q801 B Q803 B
C
R895 HPD2 HPD4 HDMI_SIDE_ATMEL
2SC3052 R897 2SC3052 IC804-*1
20 20 10K IC804
1K E 1K E R1EX24002ASAS0A AT24C02BN-SH-T
C801 C803 EDID_WP
19 19
10K
0.1uF R837 0.1uF
R871
R803
16V 16V A0 VCC
18 1.8K 18 A0 VCC
R835
3.3K
1 8
R801
3.3K
1.8K JP805 1 8
17 17 $0.055
DDC_SDA_2 DDC_SDA_4 A1 WP A1 WP
16 16 2 7 2 7 C809 R887 R891
DDC_SCL_2 DDC_SCL_4 0.1uF 2.7K 2.7K
15 15 JP806 JP812
A2 SCL A2 SCL
3 6 3 6 DDC_SCL_4
14 R815 0 14
R841 0 R881 22
HDMI_CEC
HDMI_CEC VSS SDA
13 13 GND SDA
EAG59023302
EAG62611201
4 5 4 5 DDC_SDA_4
CK-_HDMI2
12 12 CK-_HDMI4 R882 22
HDMI_2
HDMI_SIDE
11 11
CK+ CK+
10 CK+_HDMI2 10
CK+_HDMI4
D0- D0-
9 D0-_HDMI2 9 D0-_HDMI4
D0_GND D0_GND
8 8
D0+ D0+
7 D0+_HDMI2 7 D0+_HDMI4 +3.3V_Normal
D1- D1-
6 D1-_HDMI2 6 D1-_HDMI4
68K
D1_GND D1_GND
5 5
R854
4
D1+
D1+_HDMI2 4
D1+
D1+_HDMI4
For CEC
D804
R855
D2- D2-
3 D2-_HDMI2 3 0 R856
D2-_HDMI4 R857
10K 68K
D2_GND D2_GND OPT
2 2 OPT
D2+ D2+
1 D2+_HDMI2 1 D2+_HDMI4
S
B
D
CEC_REMOTE_S7
OPT
D801
OPT
D811
AVRL161A1R1NT
JK801
JK803 Q806
G
BSS83
D803
OPT
C805
0.1uF
16V
GND GND
CEC_ON/OFF
68K
+3.5V_ST
R892
D825
R883
0 R893
R853
10K 68K
OPT
HDMI_CEC
S
B
D
CEC_REMOTE_NEC
AVRL161A1R1NT Q805
G
BSS83
D826
OPT
C810
0.1uF
16V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES GND GND

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 8
RGB/SPDIF/PC/HP
New Item Development
EARPHONE BLOCK
HP_LOUT
C1118
002:V7 10uF
16V C1115 HEAD_PHONE
1000pF
50V R1125 C
OPT 1K E
JK3301
Q1101 B +3.3V_Normal
MMBT3904-(F) KJA-PH-0-0177
MMBT3904-(F)
B Q1104
GND 5
R1130
E C
10K
L 4 +3.5V_ST
ISA1530AC1
R1155
1K DETECT 3
Q1105
HP_ROUT HP_DET
R 1
C1119
E
002:V7 10uF
16V
C1116
1000pF C E
B
50V Q1102 B
OPT R1128 MMBT3904-(F) C
1K MMBT3904-(F) R1129
B Q1103
3.3K B
E SIDE_HP_MUTE
C Q1106
2SC3052
E
PC AUDIO RGB PC D1115

+5V_Normal
JK1102
SPDIF OPTIC JACK ENKMC2838-T112
A1
+3.3V_Normal
PEJ027-01 5.15 Mstar Circuit Application C
A2
3 E_SPRING
6A T_TERMINAL1
GND
1
B_TERMINAL1
Fiber Optic
JST1223-001
RGB_EEMPROM_ATMEL
7A RGB_EEMPROM_RENESAS R1140
PC_R_IN IC1105 R1139 C1129
002:S12 2.2K R1142
JK1103
IC1105-*1 AT24C02BN-SH-T 2.2K 0.1uF
D1101 R1107 10K
R_SPRING C1107 15K VCC R1EX24002ASAS0A 16V
4
2
AMOTECH 100pF R1102 A0 VCC
5.6V 50V 470K R1110 1 8
A0 VCC
T_SPRING OPT 10K 1 8
5 VINPUT A1
2 7
WP
3
SPDIF_OUT A1 WP EDID_WP
2 7
R1108 C1131
4
A2 SCL
7B B_TERMINAL2 15K C1121 3 6
002:T18 0.1uF A2 SCL RGB_DDC_SCL
PC_L_IN 002:S12 100pF 3 6
FIX_POLE
16V GND
4 5
SDA
T_TERMINAL2 D1102 C1108 R1103 50V VSS SDA

RGB_DDC_SDA
6B AMOTECH 4 5
100pF 470K
5.6V 50V R1111 C1127 C1128 R1141
OPT 10K 18pF 18pF 22 R1143
50V 50V 22
DSUB_VSYNC
DSUB_HSYNC
C1122 C1126 D1113 D1116
D1109 68pF D1114
68pF 30V 50V 5.6V
50V 5.6V
OPT 30V OPT
OPT OPT
DSUB_B+
R1133 D1110
75 30V
DSUB_G+
R1135 D1111
75 30V
+3.3V_Normal
R1146
10K
DSUB_DET
R1147
1K
DSUB_R+
D1112 D1117
R1137 30V 5.6V
75
OPT
GREEN_GND
DDC_CLOCK
DDC_DATA
BLUE_GND
SYNC_GND
RED_GND
DDC_GND
H_SYNC
V_SYNC
GND_2
GREEN
GND_1
BLUE
RED
NC
SPG09-DB-010
SHILED
11
12
13
14
15
JK1104
16
10
6
9
1
5
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. RGB/SPDIF/HP 9
RS232C
10
5
R1123 8
100 JP1121
3
7
R1124
+3.5V_ST 100 JP1122
D1107 D1108 6
CDS3C30GTH CDS3C30GTH
30V 30V 1
OPT OPT
C1101 0.33uF SPG09-DB-009

IC1101 JK1101
C1106
MAX3232CDR 0.1uF
C1+ VCC
1 16
C1102
0.1uF V+ GND
2 15
C1103
0.1uF C1- DOUT1
3 14
C2+ RIN1
4 13
C1104
0.1uF C2- ROUT1
5 12
S7_NEC_RXD
V- DIN1
6 11
C1105
0.1uF DOUT2 DIN2
7 10
S7_NEC_TXD
RIN2 ROUT2
8 9
EAN41348201

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. RS232C_9PIN 10
[51Pin LVDS Connector]
(For FHD 60/120Hz)
PANEL_VCC
[41Pin LVDS Connector] [30Pin LVDS Connector]

L702 (For FHD 120Hz) (For HD 60Hz_Normal)
120-ohm
WAFER_FHD
P705
P703 P704
FF10001-30
FI-RE51S-HF-J-R1500 FI-RE41S-HF-J-R1500
HD
WAFER_FHD WAFER_FHD_120HZ
C700 C709 C710
10uF 1000pF 0.1uF
16V 50V 16V 1
1 OPT OPT WAFER_FHD 1
OPT
2
2 2
0 R713
3 TP721 PWM_DIM
3 3 RXD4-
4 TP722 OPC_OUT
4 4 RXD4+
5
5 5 RXD3-
6 RXA3-
6 6 RXD3+
7 RXA3+
7 7
8
8 8 RXDCK-
9 RXACK-
9 9 RXDCK+
10 RXACK+
10 10
11
11 RXA4- 11 RXD2-
12 RXA2-
12 RXA4+ 12 RXD2+
13 RXA2+
13 RXA3- 13 RXD1-
14
14 RXA3+ 14 RXD1+
15 RXA1-
15 15 RXD0-
16 RXA1+ LVDS_SEL
16 RXACK- 16 RXD0+
17 +3.3V_Normal
17 RXACK+ 17
18 RXA0-
18 18
19 RXA0+ R712
19 RXA2- 19 RXC4- 3.3K
20 OPT
20 RXA2+ 20 RXC4+
21
21 RXA1- 21 RXC3- R711
22 10K
22 RXA1+ 22 RXC3+ OPT
23
23 RXA0- 23 PANEL_VCC
24
24 RXA0+ BIT_SEL 24 RXCCK-
25 L701
25 25 RXCCK+ 120-ohm
26 HD
26 R709 26
10K 27
27 RXB4- BIT_SEL_LOW 27 RXC2- OPT HD
28 C701 C702 C703
28 RXB4+ 28 RXC2+ 10uF 1000pF 0.1uF
29 16V 50V 16V
29 RXB3- 29 RXC1- OPT
30
30 RXB3+ 30 RXC1+
31 31 RXC0- 31
32 RXBCK- 32 RXC0+
33 RXBCK+ 33
34 34
35 RXB2- 35
36 RXB2+ 36
37 RXB1- 37
38 RXB1+ 38
39 RXB0- 39
40 RXB0+ 40
LVDS_SEL
41 SCAN_BLK2 41
42 +3.3V_Normal
42
43 SCAN_BLK1/OPC_OUT
R703 R705
44 0 PWM_DIM 3.3K
LVDS_PWM_44
45 OPT
46 R710
10K
47 OPT
R701
48 0 LED_DRIVER_D/L_SDA
3D_SG
49
R702
50 0 LED_DRIVER_D/L_SCL
3D_SG 100
51 2D/3D_CTL
LVDS_51PIN_GPIO
R706
52
R707
0
LVDS_51PIN_GND

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LVDS_LARGE 11
VCC_1.5V_DDR VCC_1.5V_DDR VCC_1.5V_DDR
VCC_1.5V_DDR
VCC_1.5V_DDR
R1201
DDR3 1.5V By CAP - Place these Caps near Memory VCC_1.5V_DDR

R1204
R1227
DDR3 1.5V By CAP - Place these Caps near Memory
1K 1%
R1224
1K 1%
1K 1%
1K 1%
A-MVREFDQ A-MVREFCA B-MVREFDQ
0.1uF
1000pF
B-MVREFCA
0.1uF
0.1uF
1000pF
1000pF
1%
0.1uF
1000pF
1%
1%
R1202
1%
R1205
R1228
C1205
C1216
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
R1225
C1221
C1206
C1207
C1208
C1210
C1211
C1212
C1213
C1214
C1215
C1217
C1218
C1219
C1220
C1222
C1223
C1224
C1235
C1246
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF
C1227
C1228
C1229
C1230
C1231
C1232
C1233
C1234
C1236
C1237
C1238
C1239
C1241
C1242
C1243
C1244
C1245
10uF
C1202
C1201
C1204
C1249
C1203
C1247
C1250
1K
C1248
1K
1K
1K
Close to DDR Power Pin Close to DDR Power Pin
CLose to DDR3 CLose to Saturn7M IC CLose to Saturn7M IC CLose to DDR3
IC1201-*1 IC1202-*1
K4B1G1646G-BCH9 K4B1G1646G-BCH9
DDR_1333_SS_NEW DDR_1333_SS_NEW
N3 M8 N3 M8
A0 VREFCA A0 VREFCA
P7 P7
A1 A1
P3 P3
A2 A2
N2 H1 N2 H1
A3 VREFDQ A3 VREFDQ
P8 P8
A4 A4
P2 P2
A5 A5
R8 L8 R8 L8
A6 ZQ A6 ZQ
R2 R2
A7 A7
T8 T8
A8 A8
R3 B2 R3 B2
A9 VDD_1 A9 VDD_1
L7 D9 L7 D9
A10/AP VDD_2 A10/AP VDD_2
R7 G7 R7 G7
VCC_1.5V_DDR A11 VDD_3 A11 VDD_3
N7 K2 N7 K2
A12/BC VDD_4 A12/BC VDD_4
+1.5V_DDR T3 K8 T3 K8
A13 VDD_5 A13 VDD_5
N1 N1
VDD_6 VDD_6
M7 N9 M7 N9
NC_5 VDD_7 NC_5 VDD_7
L1201 R1 R1
R1215 VDD_8 VDD_8
M2 R9 M2 R9
B-TMA0 B-MA0 BA0 VDD_9 BA0 VDD_9
56 1% N8 N8
C1225 C1226 BA1 BA1
R1216 M3 M3
R1213 10uF 0.1uF BA2
A1
BA2
A1
10V B-TMA2 1% B-MA2 VDDQ_1 VDDQ_1
A-MA0 A-TMA0 16V 56 J7 A8 J7 A8
56 1% EAN61828901 CK VDDQ_2 CK VDDQ_2
AR1211 K7 C1 K7 C1
R1214
B-TMA11
IC1202 K9
CK VDDQ_3
C9 K9
CK VDDQ_3
C9
A-MA2 A-TMA2 B-MA11 CKE VDDQ_4 CKE VDDQ_4
EAN61828901 56 1%
B-TMA1
H5TQ1G63DFR-H9C D2 D2
B-MA1 L2
VDDQ_5
E9 L2
VDDQ_5
E9
AR1208
IC1201 B-TMA8 B-MA8 K1
CS VDDQ_6
F1 K1
CS VDDQ_6
F1
A-MA11 A-TMA11 DDR_1333_HYNIX ODT VDDQ_7 ODT VDDQ_7
H5TQ1G63DFR-H9C B-TMA6 B-MA6 J3
RAS VDDQ_8
H2 J3
RAS VDDQ_8
H2
A-MA1 A-TMA1 N3 M8 K3 H9 K3 H9
56 B-MA0 A0 VREFCA B-MVREFCA CAS VDDQ_9 CAS VDDQ_9
DDR_1333_HYNIX A-MA8 A-TMA8 AR1214 P7 L3 L3
B-MA1 A1 WE
J1
WE
J1
A-MA6 A-TMA6 B-TMBA0 B-MBA0 P3 NC_1 NC_1
M8 N3 B-MA2 A2 T2 J9 T2 J9
A-MVREFCA VREFCA A0 A-MA0 56 S7M-PLUS_DivX_MS10 B-TMA3 B-MA3 N2 H1 RESET NC_2
L1
RESET NC_2
L1
P7 AR1203 B-MA3 A3 VREFDQ B-MVREFDQ
A-MA1 P8 NC_3 NC_3
A1
P3 IC101 B-TMA5 B-MA5 B-MA4 A4 NC_4
L9
NC_4
L9
A-MA2 A-MBA0 A-TMBA0 P2
H1
A2
N2 LGE107DC-RP [S7M+ DIVX/MS10] B-TMA7 B-MA7 B-MA5 A5 R1226
F3
DQSL NC_6
T7 F3
DQSL NC_6
T7
A-MVREFDQ VREFDQ A3 A-MA3 A-MA3 A-TMA3 56 R8 L8 G3 G3
P8 B-MA6 DQSL DQSL
A-MA5 A-TMA5 AR1215 A6 ZQ
A4 A-MA4 R2 240
P2 B-MA7 A7 C7 A9 C7 A9
R1203 A5 A-MA5 A-MA7 A-TMA7 B-TMA4 B-MA4 T8 1% DQSU VSS_1 DQSU VSS_1
L8 R8 B8 A25 B-MA8 B7 B3 B7 B3
56 A-TMA0 A_DDR3_A0/DDR2_A13 B_DDR3_A0/DDR2_A13 B-TMA0 A8 DQSU VSS_2 DQSU VSS_2
ZQ A6 A-MA6 B9 B24 B-TMA12 B-MA12 R3 B2 E1 E1
240 R2 AR1204 A-TMA1 A_DDR3_A1/DDR2_A8 B-TMA1 B-MA9 A9 VDD_1 VSS_3 VSS_3
A7 A-MA7 B_DDR3_A1/DDR2_A8 B-TMBA1 B-MBA1 L7 D9 E7 G8 E7 G8
1% T8 A8 A24 B-MA10 DML VSS_4 DML VSS_4
A-MA4 A-TMA4 A-TMA2 A_DDR3_A2/DDR2_A9 B_DDR3_A2/DDR2_A9 B-TMA2 A10/AP VDD_2 D3 J2 D3 J2
A8 A-MA8 C21 P25 B-TMA10 B-MA10 R7 G7 DMU VSS_5 DMU VSS_5
B2 R3 A-MA12 A-TMA12 B-MA11 A11 VDD_3 J8 J8
A-MA9 A-TMA3 A_DDR3_A3/DDR2_A1 B_DDR3_A3/DDR2_A1 B-TMA3 56 N7 K2 VSS_6 VSS_6
VDD_1 A9 B10 C24 E3 M1 E3 M1
D9 L7 A-MBA1 A-TMBA1 A-TMA4 B-TMA4 B-MA12 A12/BC VDD_4 DQL0 VSS_7 DQL0 VSS_7
VDD_2 A10/AP A-MA10 A_DDR3_A4/DDR2_A2 B_DDR3_A4/DDR2_A2 AR1219 T3 K8 F7 M9 F7 M9
G7 R7 A22 P26 B-MA13 A13 DQL1 VSS_8 DQL1 VSS_8
A-MA10 A-TMA10 A-TMA5 A_DDR3_A5/DDR2_A10 B_DDR3_A5/DDR2_A10 B-TMA5 VDD_5 F2 P1 F2 P1
VDD_3 A11 A-MA11 A10 B26 B-TMRESETB B-MRESETB N1 DQL2 VSS_9 DQL2 VSS_9
K2 N7 56 A-TMA6 B-TMA6 VDD_6 F8 P9 F8 P9
VDD_4 A12/BC A-MA12 A_DDR3_A6/DDR2_A4 B_DDR3_A6/DDR2_A4 B-TMBA2 B-MBA2 M7 N9 DQL3 VSS_10 DQL3 VSS_10
K8 T3 B22 R24 NC_5 H3 T1 H3 T1
AR1201 A-TMA7 A_DDR3_A7/DDR2_A3 B_DDR3_A7/DDR2_A3 B-TMA7 VDD_7 DQL4 VSS_11 DQL4 VSS_11
VDD_5 A13 A-MA13 C9 B25 B-TMA13 B-MA13 R1 H8 T9 H8 T9
N1 A-MRESETB A-TMRESETB A-TMA8 A_DDR3_A8/DDR2_A6 B-TMA8 VDD_8 DQL5 VSS_12 DQL5 VSS_12
VDD_6 B_DDR3_A8/DDR2_A6 B-TMA9 B-MA9 M2 R9 G2 G2
N9 M7 C23 T26 B-MBA0 BA0
VCC_1.5V_DDR DQL6 DQL6
A-MBA2 A-TMBA2 A-TMA9 A_DDR3_A9/DDR2_A12 B_DDR3_A9/DDR2_A12 B-TMA9 B-MCK VDD_9 H7 H7
VDD_7 NC_5 B11 D24 56 N8 DQL7 DQL7
R1 A-MA13 A-TMA13 A-TMA10 B-TMA10 B-MBA1 BA1 B1 B1
56
R1237
VDD_8 A_DDR3_A10/DDR2_RASZ B_DDR3_A10/DDR2_RASZ R1222 M3 VSSQ_1 VSSQ_1
A9 A26
1%
R9 M2 B-MBA2 BA2 D7 B9 D7 B9
VCC_1.5V_DDR A-MBA0 A-MA9 A-TMA9 A-TMA11 A_DDR3_A11/DDR2_A11 B_DDR3_A11/DDR2_A11 B-TMA11 B-TMCK B-MCK C1240 A1 DQU0 VSSQ_2 DQU0 VSSQ_2
VDD_9 BA0 A-MCK C10 C25 C3 D1 C3 D1
N8 22 VDDQ_1
R1235
56 A-TMA12 A_DDR3_A12/DDR2_A0 B_DDR3_A12/DDR2_A0 B-TMA12 DQU1 VSSQ_3 DQU1 VSSQ_3

BA1 A-MBA1 B23 T25 J7 A8 C8 D8 C8 D8
1%
M3 R1223 0.01uF CK VDDQ_2 DQU2 VSSQ_4 DQU2 VSSQ_4

R1206 A-TMA13 B-TMA13
56
R1238
A_DDR3_A13/DDR2_A7 B_DDR3_A13/DDR2_A7 C2 E2 C2 E2
56
BA2 A-MBA2 B-TMCKB B-MCKB 25V K7 C1 DQU3 VSSQ_5 DQU3 VSSQ_5
1%
A1 C1209 A-MCK A-TMCK 22 CK VDDQ_3 A7 E8 A7 E8
VDDQ_1 22 K9 C9 DQU4 VSSQ_6 DQU4 VSSQ_6
A8 J7 B-MCKE CKE VDDQ_4 A2 F9 A2 F9
R1236
AR1220 DQU5 VSSQ_7 DQU5 VSSQ_7

VDDQ_2 CK 0.01uF R1207 B-MCKB D2 B8 G1 B8 G1
1%
C1 K7 25V A-MCKB A-TMCKB B-TMRASB B-MRASB VDDQ_5 DQU6 VSSQ_8 DQU6 VSSQ_8
56
VDDQ_3 CK B21 P24 L2 E9 A3 G9 A3 G9

C9 K9 22 CS VDDQ_6 DQU7 VSSQ_9 DQU7 VSSQ_9
A-MCKE A-TMBA0 A_DDR3_BA0/DDR2_BA2 B_DDR3_BA0/DDR2_BA2 B-TMBA0 B-TMCASB B-MCASB K1 F1
VDDQ_4 CKE AR1202 A11 C26
D2 A-TMBA1 B-TMBA1 B-TMODT B-MODT B-MODT ODT VDDQ_7
VDDQ_5 A_DDR3_BA1/DDR2_CASZ B_DDR3_BA1/DDR2_CASZ J3 H2
L2 A-MCKB A-MRASB A-TMRASB A23 R26
E9 A-TMBA2 A_DDR3_BA2/DDR2_A5 B_DDR3_BA2/DDR2_A5 B-TMBA2 B-TMWEB B-MWEB VCC_1.5V_DDR B-MRASB
K3
RAS VDDQ_8
H9
VDDQ_6 CS A-MCASB A-TMCASB
F1 K1 56 B-MCASB CAS VDDQ_9 IC1201-*2 IC1202-*2
VDDQ_7 ODT A-MODT A12 D26 R1232 L3
H2 J3 A-MODT A-TMODT
A-TMCK B-TMCK R1219 B-MWEB WE NT5CB64M16DP-CF NT5CB64M16DP-CF
VDDQ_8 RAS A-MRASB A_DDR3_MCLK/DDR2_MCLK B_DDR3_MCLK/DDR2_MCLK 10K J1
H9 K3 VCC_1.5V_DDR A-MWEB A-TMWEB C11 D25 B-TMDQSL B-MDQSL
A-TMCKB A_DDR3_MCLKZ/DDR2_MCLKZ B_DDR3_MCLKZ/DDR2_MCLKZ B-TMCKB NC_1
VDDQ_9 CAS A-MCASB B12 E24 22 T2 J9 DDR_1333_NANYA_NEW DDR_1333_NANYA_NEW
L3 56 B-MRESETB RESET NC_2
A-MWEB R1231 A-TMCKE A_DDR3_CKE/DDR2_DQ5 B_DDR3_CKE/DDR2_DQ5 B-TMCKE R1220 L1 N3 M8 N3 M8
WE 10K R1208 A0 EAN61857201 VREFCA A0 EAN61857201 VREFCA
J1 B-TMDQSLB B-MDQSLB NC_3 P7 P7
NC_1 A-MDQSL A-TMDQSL 22 L9 A1 A1
J9 T2 NC_4 P3 P3
A-MRESETB 22 F3 T7 A2 A2
NC_2 RESET C20 N25 R1217 N2 H1 N2 H1
L1 R1209 A-TMODT B-TMODT B-MDQSL DQSL NC_6 A3 VREFDQ A3 VREFDQ
NC_3 A_DDR3_ODT/DDR2_ODT B_DDR3_ODT/DDR2_ODT B-TMDQSU B-MDQSU G3 P8 P8
L9 A-MDQSLB A-TMDQSLB A20 M26 B-MDQSLB A4 A4
22 A-TMRASB A_DDR3_RASZ/DDR2_WEZ B_DDR3_RASZ/DDR2_WEZ B-TMRASB 22 DQSL P2 P2
NC_4 B20 N24 R1218 A5 A5
T7 F3 A-TMCASB B-TMCASB R8 L8 R8 L8
NC_6 DQSL A-MDQSL R1211 A_DDR3_CASZ/DDR2_BA1 B_DDR3_CASZ/DDR2_BA1 B-TMDQSUB B-MDQSUB C7 A9 A6 ZQ A6 ZQ
G3 A21 N26 B-MDQSU DQSU R2 R2
A-MDQSU A-TMDQSU A-TMWEB A_DDR3_WEZ/DDR2_BA0 B_DDR3_WEZ/DDR2_BA0 B-TMWEB 22 VSS_1 A7 A7
DQSL A-MDQSLB 22 B7 B3 T8 T8
B-MDQSUB DQSU VSS_2 A8 A8
R1212 AR1212 E1 R3 B2 R3 B2
A9 C7 C22 R25 A9 VDD_1 A9 VDD_1
A-MDQSUB A-TMDQSUB A-TMRESETB A_DDR3_RESETB B_DDR3_RESETB B-TMRESETB VSS_3 L7 D9 L7 D9
VSS_1 DQSU A-MDQSU B-TMDQL1 B-MDQL1 E7 G8 A10/AP VDD_2 A10/AP VDD_2
B3 B7 22 B-MDML DML VSS_4 R7 G7 R7 G7
VSS_2 DQSU A-MDQSUB B-TMDQL3 B-MDQL3 D3 J2 A11 VDD_3 A11 VDD_3
E1 AR1209 B-MDMU DMU VSS_5 N7 K2 N7 K2
VSS_3 B-TMDML B-MDML J8 A12 VDD_4 A12 VDD_4
G8 E7 C16 J25 T3 K8 T3 K8
A-MDQL1 A-TMDQL1 A-TMDQSL A_DDR3_DQSL/DDR2_DQS0 B_DDR3_DQSL/DDR2_DQS0 B-TMDQSL VSS_6 NC_6 VDD_5 NC_6 VDD_5
VSS_4 DML A-MDML B16 J24 B-TMDQU2 B-MDQU2 E3 M1 N1 N1
J2 D3 A-MDQL3 A-TMDQL3 A-TMDQSLB B-TMDQSLB B-MDQL0 DQL0 VSS_7 VDD_6 VDD_6
VSS_5 DMU A-MDMU A_DDR3_DQSLB/DDR2_DQSB0 B_DDR3_DQSLB/DDR2_DQSB0 22 F7 M9 M7 N9 M7 N9
J8 B-MDQL1 NC_5 VDD_7 NC_5 VDD_7
A-MDML A-TMDML DQL1 VSS_8 R1 R1
VSS_6 A16 H26 AR1213 F2 P1 VDD_8 VDD_8
M1 E3 A-MDQU2 A-TMDQU2 B-MDQL2 DQL2 VSS_9 M2 R9 M2 R9
A-MDQL0 A-TMDQSU A_DDR3_DQSU/DDR2_DQSB1 B_DDR3_DQSU/DDR2_DQSB1 B-TMDQSU B-TMCKE B-MCKE F8 P9 BA0 VDD_9 BA0 VDD_9
VSS_7 DQL0 C15 H25 N8 N8
M9 F7 22 A-TMDQSUB B-TMDQSUB B-MDQL3 DQL3 VSS_10 BA1 BA1
VSS_8 DQL1 A-MDQL1 A_DDR3_DQSUB/DDR2_DQS1 B_DDR3_DQSUB/DDR2_DQS1 B-TMDQL7 B-MDQL7 H3 T1 M3 M3
P1 F2 AR1210 B-MDQL4 DQL4 VSS_11 BA2
A1
BA2
A1
VSS_9 DQL2 A-MDQL2 A14 F26 B-TMDQL5 B-MDQL5 H8 T9 VDDQ_1 VDDQ_1
P9 F8 A-MCKE A-TMCKE A-TMDML B-TMDML B-MDQL5 DQL5 VSS_12 J7 A8 J7 A8
VSS_10 DQL3 A-MDQL3 A_DDR3_DML//DDR2_DQ13 B_DDR3_DML/DDR2_DQ13 G2 CK VDDQ_2 CK VDDQ_2
T1 H3 B18 L24 B-MDQL6 DQL6 K7 C1 K7 C1
A-MDQL7 A-TMDQL7 A-TMDMU A_DDR3_DMU/DDR2_DQ6 B_DDR3_DMU/DDR2_DQ6 B-TMDMU 22 CK VDDQ_3 CK VDDQ_3
VSS_11 DQL4 A-MDQL4 H7 K9 C9 K9 C9
T9 H8 A-MDQL5 A-TMDQL5 B-MDQL7 DQL7 CKE VDDQ_4 CKE VDDQ_4
VSS_12 DQL5 A-MDQL5 AR1216 B1 D2 D2
G2 C18 L25 VDDQ_5 VDDQ_5
A-TMDQL0 A_DDR3_DQL0/DDR2_DQ3 B_DDR3_DQL0/DDR2_DQ3 B-TMDQL0 VSSQ_1 L2 E9 L2 E9
DQL6 A-MDQL6 B13 F24 B-TMDQL0 B-MDQL0 D7 B9 CS VDDQ_6 CS VDDQ_6
H7 22 A-TMDQL1 B-TMDQL1 B-MDQU0 DQU0 VSSQ_2 K1 F1 K1 F1
DQL7 A-MDQL7 A_DDR3_DQL1/DDR2_DQ7 B_DDR3_DQL1/DDR2_DQ7 B-TMDQL2 B-MDQL2 C3 D1 ODT VDDQ_7 ODT VDDQ_7
B1 AR1205 A19 L26 B-MDQU1 DQU1 J3 H2 J3 H2
A-TMDQL2 A_DDR3_DQL2/DDR2_DQ1 B_DDR3_DQL2/DDR2_DQ1 B-TMDQL2 VSSQ_3 RAS VDDQ_8 RAS VDDQ_8
VSSQ_1 C13 F25 B-TMDQL6 B-MDQL6 C8 D8 K3 H9 K3 H9
B9 D7 A-MDQL0 A-TMDQL0 A-TMDQL3 B-TMDQL3 B-MDQU2 DQU2 VSSQ_4 CAS VDDQ_9 CAS VDDQ_9
VSSQ_2 DQU0 A-MDQU0 A_DDR3_DQL3/DDR2_DQ10 B_DDR3_DQL3/DDR2_DQ10 B-TMDQL4 B-MDQL4 C2 E2 L3 L3
D1 C3 C19 M25 B-MDQU3 DQU3 WE WE
A-MDQL2 A-TMDQL2 A-TMDQL4 A_DDR3_DQL4/DDR2_DQ4 B_DDR3_DQL4/DDR2_DQ4 B-TMDQL4 VSSQ_5 J1 J1
VSSQ_3 DQU1 A-MDQU1 A13 E26 22 A7 E8 NC_1 NC_1
D8 C8 A-MDQL6 A-TMDQL6 A-TMDQL5 B-TMDQL5 B-MDQU4 DQU4 VSSQ_6 T2 J9 T2 J9
VSSQ_4 DQU2 A-MDQU2 A_DDR3_DQL5/DDR2_DQ0 B_DDR3_DQL5/DDR2_DQ0 AR1217 A2 F9 RESET NC_2 RESET NC_2
E2 C2 B19 M24 B-MDQU5 DQU5 L1 L1
A-MDQL4 A-TMDQL4 A-TMDQL6 A_DDR3_DQL6/DDR2_CKE B_DDR3_DQL6/DDR2_CKE B-TMDQL6 VSSQ_7 NC_3 NC_3
VSSQ_5 DQU3 A-MDQU3 C12 E25 B-TMDQU7 B-MDQU7 B8 G1 L9 L9
E8 A7 22 A-TMDQL7 B-TMDQL7 B-MDQU6 DQU6 VSSQ_8 NC_4 NC_4
VSSQ_6 DQU4 A-MDQU4 A_DDR3_DQL7/DDR2_DQ2 B_DDR3_DQL7/DDR2_DQ2 B-TMDQU3 B-MDQU3 A3 G9 F3 T7 F3 T7
F9 A2 AR1206 B-MDQU7 DQU7 VSSQ_9 G3
DQSL NC_7
G3
DQSL NC_7
VSSQ_7 DQU5 A-MDQU5 A15 G26 B-TMDQU5 B-MDQU5 DQSL DQSL
G1 B8 A-MDQU7 A-TMDQU7 A-TMDQU0 B-TMDQU0
VSSQ_8 DQU6 A-MDQU6 A_DDR3_DQU0/DDR2_DQ15 B_DDR3_DQU0/DDR2_DQ15 B-TMDMU B-MDMU
G9 A3 A17 J26 C7 A9 C7 A9
A-MDQU3 A-TMDQU3 A-TMDQU1 A_DDR3_DQU1/DDR2_DQ9 B_DDR3_DQU1/DDR2_DQ9 B-TMDQU1 22 DQSU VSS_1 DQSU VSS_1
VSSQ_9 DQU7 A-MDQU7 B14 G24 B7 B3 B7 B3
A-MDQU5 A-TMDQU5 A-TMDQU2 A_DDR3_DQU2/DDR2_DQ8 B_DDR3_DQU2/DDR2_DQ8 B-TMDQU2 AR1218 DQSU VSS_2 DQSU VSS_2
C17 K25 E1 E1
A-MDMU A-TMDMU VSS_3 VSS_3
A-TMDQU3 A_DDR3_DQU3/DDR2_DQ11 B_DDR3_DQU3/DDR2_DQ11 B-TMDQU3 B-TMDQU6 B-MDQU6 E7 G8 E7 G8
22 B15 H24 DML VSS_4 DML VSS_4
A-TMDQU4 A_DDR3_DQU4/DDR2_DQM1 B_DDR3_DQU4/DDR2_DQM1 B-TMDQU4 B-TMDQU0 D3 J2 D3 J2
B-MDQU0 DMU VSS_5 DMU VSS_5
AR1207 A18 K26 J8 J8
A-TMDQU5 A_DDR3_DQU5/DDR2_DQ12 B_DDR3_DQU5/DDR2_DQ12 B-TMDQU5 B-TMDQU4 B-MDQU4 VSS_6 VSS_6
A-MDQU6 A-TMDQU6 C14 G25 DDR_DVB_T2_2G DDR_DVB_T2_2G E3 M1 E3 M1
A-TMDQU6 A_DDR3_DQU6/DDR2_DQM0 B_DDR3_DQU6/DDR2_DQM0 B-TMDQU6 IC1201-*3 IC1202-*3 DQL0 VSS_7 DQL0 VSS_7
B17 K24 K4B2G1646C K4B2G1646C F7 M9 F7 M9
A-MDQU0 A-TMDQU0 A-TMDQU7 B-TMDQU7 22 DQL1 VSS_8 DQL1 VSS_8
A_DDR3_DQU7/DDR2_DQ14 B_DDR3_DQU7/DDR2_DQ14 F2 P1 F2 P1
A-MDQU4 A-TMDQU4 N3 M8 N3 M8
DQL2 VSS_9 DQL2 VSS_9
F8 P9 F8 P9
R1221 P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
P3 P3
B-TMDQU1 B-MDQU1 N2
A2
H1 N2
A2
H1
H3 T1 H3 T1
P8
A3 VREFDQ
P8
A3 VREFDQ DQL4 VSS_11 DQL4 VSS_11
22 22 P2
A4
P2
A4 H8 T9 H8 T9
R8
A5
L8 R8
A5
L8
R2
A6 ZQ
R2
A6 ZQ G2 G2
R1210 T8
A7
T8
A7
H7
DQL6
H7
DQL6
A8 A8
A-MDQU1 A-TMDQU1 R3
L7
A9 VDD_1
B2
D9
R3
L7
A9 VDD_1
B2
D9
DQL7 DQL7
10K R1234 B1 B1
22 R7
A10/AP VDD_2
G7 R7
A10/AP VDD_2
G7
VSSQ_1 VSSQ_1
B-MCKE N7
A11
A12/BC
VDD_3
VDD_4
K2 N7
A11
A12/BC
VDD_3
VDD_4
K2
D7 B9 D7 B9
T3 K8 T3 K8
A13 VDD_5
N1
A13 VDD_5
N1
DQU0 VSSQ_2 DQU0 VSSQ_2
VDD_6 VDD_6 C3 D1 C3 D1
R1233 10K M7
NC_5 VDD_7
N9 M7
NC_5 VDD_7
N9
A-MCKE M2
VDD_8
R1
R9 M2
VDD_8
R1
R9
C8 D8 C8 D8
N8
BA0 VDD_9
N8
BA0 VDD_9 DQU2 VSSQ_4 DQU2 VSSQ_4
M3
BA1
M3
BA1 C2 E2 C2 E2
BA2
A1
BA2
A1
J7
VDDQ_1
A8 J7
VDDQ_1
A8
A7 E8 A7 E8
K7
CK VDDQ_2
C1 K7
CK VDDQ_2
C1
K9
CK VDDQ_3
C9 K9
CK VDDQ_3
C9
A2 F9 A2 F9
CKE VDDQ_4
D2
CKE VDDQ_4
D2
L2
VDDQ_5
E9 L2
VDDQ_5
E9
B8 G1 B8 G1
K1
CS VDDQ_6
F1 K1
CS VDDQ_6
F1
J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2
A3 G9 A3 G9
K3
RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9
CAS VDDQ_9 CAS VDDQ_9
L3 L3
WE WE
J1 J1
NC_1 NC_1
T2 J9 T2 J9
RESET NC_2 RESET NC_2
L1 L1
NC_3 NC_3
L9 L9
NC_4 NC_4
F3 T7 F3 T7
DQSL NC_6 DQSL NC_6
G3 G3
DQSL DQSL
C7 A9 C7 A9
DQSU VSS_1 DQSU VSS_1
B7 B3 B7 B3
DQSU VSS_2 DQSU VSS_2
E1 E1
VSS_3 VSS_3
E7 G8 E7 G8
DML VSS_4 DML VSS_4
D3 J2 D3 J2
DMU VSS_5 DMU VSS_5
J8 J8
VSS_6 VSS_6
E3 M1 E3 M1
F7 M9 F7 M9
F2 P1 F2 P1
F8 P9 F8 P9
H3 T1 H3 T1
H8 T9 H8 T9
G2 G2
DQL6 DQL6
H7 H7
DQL7 DQL7
B1 B1
VSSQ_1 VSSQ_1
D7 B9 D7 B9
C3 D1 C3 D1
C8 D8 C8 D8
C2 E2 C2 E2
A7 E8 A7 E8
A2 F9 A2 F9
B8 G1 B8 G1
A3 G9 A3 G9

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. DDR_256 12
+3.3V_Normal
+3.3V_Normal
S_FLASH_MAIN_MACRONIX
R1404
IC1401
4.7K
+3.3V_Normal MX25L8006EM2I-12G
CS# VCC C1401

1 8
R1403
/SPI_CS
10K
0.1uF
SO/SIO1 HOLD#
SPI_SDO 2 7
WP# SCLK
/FLASH_WP 3 6 SPI_SCK
R1405
C GND SI/SIO0 33
4 5 SPI_SDI
R1401 B Q1401
KRC103S
OPT 0
E OPT
S_FLASH_MAIN_WINBOND
IC1401-*1
W25Q80BVSSIG
CS VCC
1 8
DO[IO1] HOLD[IO3]
2 7
%WP[IO2] CLK
3 6
GND DI[IO0]
4 5

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SFLASH_1MB 13
GP2R_LARGE_TUNER
+5V_TU BOOSTER : CHINA OPT
RF_SWITCH_CTL
Pull-up can’t be applied L3701 BOOSTER_OPT
because of MODEL_OPT_2 BLM18PG121SN1D
BOOSTER_OPT
R3734 BOOSTER_OPT
R3743
0
close to TUNER 10K
Q3701
BOOSTER_OPT
OPT E ISA1530AC1
R3737
R3762 0 2.2K
CONTROL_ATTEN
B BOOSTER_OPT
C
CN_2INPUT_H_LG3911 C BOOSTER_OPT
R3745
Q3702 B 10K FE_BOOSTER_CTL
TU3702 TU3701 2SC3052 LNA2_CTL

The pull-up/down of LNA2_CTL
C3709 E BOOSTER_OPT
TDTJ-S001D TDFR-C036D 0.01uF
25V
is depended on MODLE_OPT_1.
GPIO must be added for FE_BOOSTER_CTL
BOOSTER_OPT
DVB_1INPUT_H_LGIT close to TUNER +5V_TU
+5V_TU
ANT_PWR[OPT] RF_S/W_CNTL OPTION : RF AGC
1 1 R3705 0 R3755
C3701 C3731 470 R3758
RF_SW_OPT C3728 10uF
BST_CNTL BST_CNTL 0.1uF C3704 0.1uF
82
2 2 16V C3703 10V TU_SIF
0.1uF 16V OPT E
100pF
16V OPT GPIO must be added.
+B +B1[+5V] 50V C
3 3 R3754 TU_IIC_NON_ATSC_SANYO TU_IIC_NON_ATSC_SANYO
10K B ISA1530AC1
Q3704 B FE_AGC_SPEED_CTL
2SC3052
+3.3V_TU R3753 Q3705
NC[RF_AGC] NC[RF_AGC] OPT IF_AGC_SEL R3740-*1 4.7K
C
4 4 R3707 0 OPT 1K R3741-*1
E 1K
OPT
AS NC_1 TU_IIC_ATSC_SANYO
5 5 C3706
R3740 TU_IIC_ATSC_SANYO
1.2K R3741
0.1uF 33 R3735
SCL SCLT 16V TU_I2C_NON_FILTER 1.2K +5V_TU
6 6 TU_SCL
TU_I2C_NON_FILTER
SDA SDAT C3713 33 R3736
C3743
7 7 18pF TU_I2C_NON_FILTER
20pF TU_SDA
TU_I2C_NON_FILTER 50V C3742 R3751 R3752
50V 220 220
NC[IF_TP] NC_2 C3711 20pF
TU_I2C_FILTER
8 8 18pF 50V
50V
SIF SIF C3702 close to TUNER TU_I2C_FILTER TU_CVBS
9 9
E
0.1uF 16V R3749 0
NC NC_3
10 10 B
+3.3V_TU R3750 Q3703
VIDEO VIDEO C3711-*1 C3713-*1 1K ISA1530AC1
C
11 11 +3.3V_TU 20pF 20pF OPT
50V 50V
+1.2V/+1.8V_TU TU_I2C_FILTER TU_I2C_FILTER
GND GND CN C3708
12 12 C3739 C3707
100pF 0.1uF TU_I2C_FILTER
10uF 16V TU_I2C_FILTER
1.2V +B2[1.2V] FULL_NIM 6.3V 50V R3733 R3735-*1 R3736-*1
R3732 100K
13 13 C3737 C3738 C3705 100
100pF 0.1uF 100uF TUNER_RESET COIL COIL
3.3V +B3[3.3V] 50V 16V 16V DEMOD_RESET
close to the tuner pin, add,09029 C3710
14 14 0.1uF +3.3V_TU This was being applied to the only china demod,
16V
RESET RESET so this has to be deleted in both main and ISDB sheet.
15 15
IF_AGC_CNTL NC_4 0
R3742 R3744
16 16 R3704
IF_AGC_MAIN 4.7K
FULL_NIM
4.7K
HALF_NIM FULL_NIM
DIF_1 SCL FULL_NIM
should be guarded by ground
17 17 R3702 100
DEMOD_SCL HALF_NIM_1.2V_BCD
IC3703
DIF_2 SDA R2
18 18 R3701 100 +3.3V_TU AZ1117BH-ADJTRE1 HALF_NIM
DEMOD_SDA
close to IF line R3767 +1.2V/+1.8V_TU
FULL_NIM 10
ERR C3714 INPUT ADJ/GND
19 C3712 3 1
22pF 22pF
19 50V
2
SYNC 50V
FULL_NIM FULL_NIM
20 HALF_NIM IC3703-*1 OUTPUT HALF_NIM
SHIELD R3760 0 AP1117EG-13 R3768
VALID IF_N_MSTAR 1.2K
21 R1
IN OUT R3703
MCL ADJ/GND HALF_NIM 150
22 IF_P_MSTAR OPT
R3761 0 R3766
D0 HALF_NIM 1. should be guarded by ground 1
HALF_NIM_1.2V_DIODES
23 2. No via on both of them 1/10W
3. Signal Width >= 12mils C3740 C3741
D1 Signal to Signal Width = 12mils Please, check multi Item! 10/12 0.1uF 10uF
24 Ground Width >= 24mils IC3701 16V
HALF_NIM 10V
AP2132MP-2.5TRG1
[EP] HALF_NIM
D2 Close to the tuner
FULL_NIM_BCD +1.2V/+1.8V_TU
25 R3748-*1
10K 380mA
R3771 10K PG GND
D3 1 8
TUNER MULTI-OPTION GP3_ATSC_1INPUT_H_SANYO 26 FULL_NIM_BCD
THERMAL
C3717 FULL_NIM_BCD FULL_NIM_SEMTEK
0.1uF R3764
TU3702-*3
D4 16V R3770 10K EN ADJ R3748
9
UDA55AL 2 7 0
TU3702-*1
27 FULL_NIM_SEMTEK 1/10W
TDVJ-H101F 5.1K FULL_NIM
D5 VIN VOUT R1
1
ANT_PWR[OPT] NC_1 28 3 6
1
BST_CNTL NC_2
2 2
R3769 10K
3
+B +B[+5V] D6 VCTRL NC FULL_NIM FULL_NIM
FULL_NIM
3
4
NC[RF_AGC]
4
NC[RF_AGC] 29 +5V_Normal FULL_NIM_BCD
4 5 C3729 C3730
5
AS AS
R3747 0.1uF
5
16V 10uF
6
SCL
6
SCL D7 9.1K 10V
SDA
30
FULL_NIM_BCD
7 SDA
7
L3704
8
NC(IF_TP)
8
NC(IF_TP) 31 1005
R2
SIF SIF
9 9
NC NC_3
10 10
11
VIDEO
GND
11
VIDEO
IC3701-*1
GND
12
1.2V
12
+1.2V SHIELD SC4215ISTRT
13 13 Vo=0.8*(1+R1/R2)
3.3V +3.3V
14 14
RESET RESET
15 15
16
IF_AGC_CNTL IF_AGC_CNTL NC_1 GND
DIF_1
16
DIF_1
1 8
17
DIF_2
17 FULL_NIM_SEMTEK
18 18
DIF_2 FULL_NIM R3724 0
FE_TS_SYNC FE_TS_DATA[0-7] EN ADJ
19 19
2 7
SHIELD SHIELD
FULL_NIM R3730 0
FE_TS_VAL_ERR
GP3_ATSC_1INPUT_H_LGIT VIN VO
3 6
FULL_NIM R3731 0
FE_TS_CLK
NC_2 NC_3
FULL_NIM_CHINA 4 5
R3725 0 FE_TS_DATA[0]
CN_2INPUT_H_ALTO
NTSC_2INPUT_H_LGIT
GP2R_AU_1INPUT_H_LGIT FULL_NIM TU3701-*4

R3727 0
TU3702-*4 FE_TS_DATA[1] TDFR-C236D
RF_S/W_CTL TDTJ-S101D
1
BST_CTL
2 RF_S/W_CNTL
+B1[5V] ANT_PWR FULL_NIM R3728 FULL_NIM_BR 1
3 1 0 FE_TS_DATA[2] 2
BST_CNTL
NC_1[RF_AGC] NC_1
4 2 TU3701-*2 +B1[+5V]
+B1[5V] 3
NC_2 3 TDFR-B036F NC[RF_AGC]
5
SCLT RF_AGC FULL_NIM R3729 4
6 4 0 FE_TS_DATA[3] 1
RF_S/W_CNTL
5
NC_1
SDAT MOPLL_AS
7 5 BST_CNTL SCLT
2
SCL 6
NC_3 +B1[5V]
8 6 3 SDAT
SIF SDA FULL_NIM R3726 NC_1[RF_AGC] 7
9 7 0 FE_TS_DATA[4] 4
NC_2 8
NC_2
NC_4 NC_2 5
10 8 SCLT SIF
SIF 6 9
VIDEO 9 SDAT
11 NC_3
GND NC_3 FULL_NIM R3721
7
NC_3
10
12 10 0 FE_TS_DATA[5] 8
11
VIDEO
+B2[1.2V] VIDEO 9
SIF
13 11 GND
NC_4 12
+B3[3.3V] GND 10
14 12 VIDEO +B2[1.2V]
RESET +B2[1.2V] FULL_NIM R3722 11 13
15 13 0 FE_TS_DATA[6] 12
GND
14
+B3[3.3V]
IF/AGC +B3[3.3V] +B2[1.2V]
16 14 13 RESET
RESET +B3[3.3V] 15
DIF_1[N] 15 14
17 NC_4
DIF_2[P] IF_AGC FULL_NIM_CHINA R3723 15
RESET 16
18 16 0 FE_TS_DATA[7] 16
NC_5
17
SCL
DIF_1[N]
17 SCL SDA
19
18
DIF_2[P]
17
SDA
18 +5V_TUNER
18 ERR
SHIELD
19
ERR 19
SYNC
+3.3V_Normal
19
Close to the CI Slot 20
SYNC
VALID
20
VALID
+5V_TU
TU3702-*2 SHIELD 21
MCL
21
MCL +3.3V_TU
22
22 Size change Size change
TDTR-T036F 23
D0
D1 23
D0
200mA L3702 L3703
R3706 0
24
D2
D1
60mA
25
24
D2
MLB-201209-0120P-N2 MLB-201209-0120P-N2
D3
26 25
FULL_NIM_BR 27
D4 D3
26
D5
28 D4
C3719 C3724 C3722 C3726 C3715
D6 27
C3723 C3725 C3727
29
D7 28
D5
22uF 0.1uF 22uF 0.1uF 22uF 0.1uF
31
30
D6 16V 16V 22uF 0.1uF 10V
29 10V 16V 16V 16V
SHIELD D7 10V
30
31
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SHIELD location movement,0929
Add,0929

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TUNER_L 14
+1.8V_AMP
+3.3V_Normal
IC404
AP1117E18G-13
R474
IN 3 Vd=1.4V 1 ADJ/GND
120 mA
1
2
C434 OUT C446
C421
0.1uF 10uF 0.1uF
16V 10V 16V
+24V
SPK_L+
D501
1N4148W R519 R526
OPT 100V 12 12 L506 R527
R535 10.0uH C536
OPT 0.1uF 4.7K
3.3 C529 50V
390pF NRS6045T100MMGK
OPT
C547
50V
10.0uH
C534
0.47uF
SPEAKER_L
C521 50V
C515 C519 10uF 0.01uF
0.1uF 0.1uF 50V C530 C537
50V 50V 35V 390pF L507 0.1uF R528
+3.3V_Normal D502 50V NRS6045T100MMGK 50V
1N4148W R520 R524 4.7K
BLM18PG121SN1D
100V 12 12
C514 OPT
22000pF SPK_L-
50V C518
L504 22000pF
50V
PGND1A_2
PGND1A_1
PVDD1A_2
PVDD1A_1
PVDD1B_2
PVDD1B_1
PGND1B_2
PGND1B_1
C520
OUT1A_2
OUT1A_1
OUT1B_2
OUT1B_1
1uF
EP_PAD
25V
BST1B
VDR1B
AMP_RESET
TP502
C506
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1000pF
50V
BST1A 1 42 NC C522 SPK_R+
AUD_MASTER_CLK C512 25V1uF
VDR1A 2 THERMAL 41 VDR2A C525
1uF 25V /RESET 57 BST2A 22000pF
3 40 D503 R525
+1.8V_AMP 50V R521
C509 AD 4 39 PGND2A_2 1N4148W 12 12 NRS6045T100MMGK
+1.8V_AMP 0.1uF 100V L508 C538 R529
DGND_1 5 38 PGND2A_1 10.0uH
OPT
BLM18PG121SN1D
GND_IO 37 OUT2A_2 C531 0.1uF 4.7K

6 IC501
CLK_I 7 36 OUT2A_1
390pF
50V L509
C535
0.47uF
50V SPEAKER_R
BLM18PG121SN1D
L502 10.0uH 50V

C508 VDD_IO 8 35 PVDD2A_2
C504 1000pF C433 EAN60969603 C532
L501 50V 10uF DGND_PLL 9 34 PVDD2A_1 390pF
100pF 50V NRS6045T100MMGK
R508 10V OPT AGND_PLL 33 PVDD2B_2 D504 C539 R530
50V 10
3.3K LF PVDD2B_1 1N4148W R522 R523 0.1uF 4.7K
11 NTP-7100 32 100V 12 12 50V
AVDD_PLL 12 31 OUT2B_2 OPT SPK_R-
DVDD_PLL 13 30 OUT2B_1 +24V
GND 14 29 PGND2B_2
OPT
C501 C502 OPT
10uF 0.1uF C503 C505
15
16
17
18
19
20
21
22
23
24
25
26
27
28
10V 16V 10uF 0.1uF

10V 16V
DGND_2
DVDD
SDATA
WCK
BCK
SDA
SCL
MONITOR0
MONITOR1
MONITOR2
/FAULT
VDR2B
BST2B
PGND2B_1
+1.8V_AMP C528
C526 C527 10uF
0.1uF 0.1uF 35V
50V 50V
OPT
C511 C517
10uF C513 1uF
0.1uF 25V C524
10V
16V
22000pF
50V
R503 100
AUD_LRCH
R504 100 R513
AUD_LRCK 0
R505 100 POWER_DET
AUD_SCK
R506 33 C516 OPT
AMP_SDA 1000pF
R507 33 50V
AMP_SCL +3.5V_ST
C507 C510 C546 C544 C545
18pF 18pF 22pF 22pF 22pF
50V 50V 50V 50V 50V
R515 WAFER-ANGLE
OPT OPT OPT R514 100 10K
C
B R517 SPK_L+
Q501 AMP_MUTE 4
2SC3052 10K
E SPK_L-
3
SPK_R+
2
SPK_R-
1
P501

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. AMP_NTP 16
Rear AV
AV_CVBS_IN
COMPONENT2 +3.3V_Normal
REAR_AV C1643 C1648
D1619 47pF 220pF
R1654
30V 50V 50V R1612
75 +3.3V_Normal R1615
REAR_AV REAR_AV OPT 10K 1K
COMP2_DET
R1660 D1613
ETHERNET FOR DVB_T2
JK1604 10K 5.6V
PPJ233-01 REAR_AV OPT
AV_CVBS_DET
[RD]E-LUG R1666
5C 1K
D1624 C1646 REAR_AV
5.6V [GN]E-LUG
4C [RD]O-SPRING 0.1uF
OPT
16V 6A R1619
REAR_AV [GN]O-SPRING 75
3C [RD]CONTACT L-MONO COMP2_Y+
D1612
REAR_AV 5A 30V
R1685 [GN]CONTACT
4B [WH]C-LUG
10K
AV_R_IN 4A
TP1610
REAR_AV
[YL]CONTACT L1609 [BL]E-LUG-S
D1614 30V ET_RXD0
R1689
3A 120-ohm C1663
R1671 7B R1620
12K
D1625 REAR_AV 330pF
[BL]O-SPRING 75 TP1611 ET_TXD0
[YL]O-SPRING 5.6V 470K
4A 50V COMP2_Pb+
REAR_AV REAR_AV REAR_AV 5B
TP1612
[YL]E-LUG
[RD]E-LUG-S ET_RXD1
5A
7C R1621
L1610 REAR_AV
[RD]O-SPRING_1 75 TP1613 ET_TXD1
120-ohm R1684
10K D1615 COMP2_Pr+
AV_L_IN 5C 30V TP1614 ET_REF_CLK
REAR_AV [WH]O-SPRING
REAR_AV
REAR_AV R1633
R1672
C1662 R1688 5D 10K TP1615 ET_TX_EN
D1626 330pF 12K [RD]CONTACT COMP2_L_IN
5.6V 470K 50V REAR_AV
REAR_AV REAR_AV 4E D1616 R1625
C1616 R1636 TP1616 ET_MDC
[RD]O-SPRING_2 5.6V 470K 1000pF 12K
50V OPT TP1617 ET_MDIO
5E
[RD]E-LUG TP1618 ET_CRS
R1632
6E 10K
COMP2_R_IN ET_RXER
PPJ234-01 TP1619
D1617 C1617
JK1603 R1634
REAR_COMP2
5.6V R1626 1000pF 12K TP1620 /RST-PHY
470K 50V OPT
IC1601-*1
SN324
OUT1 OUT4
1 14
EU_OPT_AUK
INV_IN1 INV_IN4
2 13
+3.3V_Normal NON_INV_IN1 NON_INV_IN4

3 12
R1613 VCC GND

10K 4 11
SC1/COMP1_DET NON_INV_IN2 NON_INV_IN3

R1614 5 10
1K IN CASE OF SMALL= 15V
D1611 C1607
R4223
5.6V 0.1uF EU_OPT +12V/+15V INV_IN2 INV_IN3

16V L1606 6 9
OPT EU_OPT
0
R4210
COMPONENT1 0
SC1_SOG_IN EU_OPT EU_OPT EU_OPT OUT2 OUT3
E EU_OPT C1625 7 8
ISA1530AC1 R1640 C1623
470 0.1uF 0.1uF
Q1601 50V 50V
SC1_CVBS_IN B
C EU_OPT EU_OPT
EU_OPT EU_OPT C1608 Q1602 R1641
R1609 C1604 EU_OPT EU_OPT_BCD
EU_OPT 220pF C 2SC3052 47K EU_OPT
75 47pF
AV_DET 50V 50V R4211 C1621 IC1601
FIX-TER OPT 390 B 47uF AS324MTR-E1
22 D1602
COM_GND 16V
11 [GN]GND 30V EU_OPT
21 DTV/MNT_VOUT CLOSE TO MSTAR R1656
10 OPT E
SYNC_IN EU_OPT 2.2K OUT1 OUT4
[GN]G R1635 DTV/MNT_L_OUT 1 14
20
SYNC_OUT 390 EU_OPT
9 EU_OPT R1664
19 EU_OPT C1644
[GN]C_DET Rf EU_OPT R1642 OPT 33K IN1- IN4-
SYNC_GND2 EU_OPT EU_OPT Rg 10uF 2 13
D1610 R1628 R1639 15K R1662
8 18 C1620 180 C1664 16V 470K
D1603 30V 75 Gain=1+Rf/Rg R4218 EU_OPT
[BL]B SYNC_GND1 100uF 0.01uF R1667
30V OPT +12V/+15V 22K
17 16V EU_OPT EU_OPT 10K IN1+ 3 12
IN4+
7 RGB_IO OPT R1657 C1654
SC1_FB 5.6K 33pF
[RD]R 16 EU_OPT SCART1_Lout R4219 100
R_OUT R1627 VCC GND
6 SC1_R+/COMP1_Pr+ EU_OPT 4 11
15 R1616 22
[WH]L_IN D1604
RGB_GND R1608 75 C1642 EU_OPT
30V R1658
5 14 75 0.1uF IN2+ IN3+
R4216 100 5.6K
[RD]R_IN R_GND 50V SCART1_Rout 5 10
13 R4221 EU_OPT
4 D2B_OUT 0 R1665
[RD]MONO EU_OPT C1665 R4217 33K IN2- IN3-
12 6 9
G_OUT OPT 0.01uF 22K
13 SC1_G+/COMP1_Y+ EU_OPT
11 D1605 30V R1668
D2B_IN REC_8 EU_OPT 10K OUT2 OUT3
PPJ-230-01 30V R1604 C1655 7 8
10 D1716 R1655
JK1601 G_GND 75 2.2K 33pF
COMPONENT1 DTV/MNT_R_OUT
9 EU_OPT
ID EU_OPT
SC1_ID OPT
8 OPT C1645 R1661
B_OUT EU_OPT 10uF
D1618 R1623 EU_OPT 470K
7 SC1_B+/COMP1_Pb+ 30V 16V
15K R1629
AUDIO_L_IN D1606 3.9K EU_OPT
6 30V R1605
B_GND 75
5
AUDIO_GND
4
AUDIO_L_OUT R1617
3 10K
AUDIO_R_IN SC1/COMP1_L_IN
2 L1604 +12V/+15V
1
AUDIO_R_OUT D1607
5.6V
R1606
470K
120-ohm C1611
330pF
R1630
12K [SCART PIN 8] IN CASE OF SMALL= 15V
NON_EU 50V
PSC008-01
JK1602 R1618
OPT
10K
SC1/COMP1_R_IN R1687
L1603 10K C
D1609
120-ohm C1612
5.6V R1631 OPT B OPT
R1607 330pF 12K R1675 OPT Q1615
NON_EU 470K 2K R1677
50V 2SC3052
10K OPT
R1695 R4207 E
Full Scart/ Comp1 [SCART AUDIO MUTE] OPT

12K
C
51K
OPT
R1680 REC_8
+3.5V_ST 1K B
DTV/MNT_L_OUT SC_RE1
OPT
D1608 EU_OPT EU_OPT EU_OPT Q1613
L1601 C1609 DTV/MNT_L_OUT OPT E 2SC3052
5.6V C1618 R1676
BLM18PG121SN1D EU_OPT
OPT 1000pF 4700pF R1652 560
EU_OPT
50V Q1607 C
10K
EU_OPT OPT
2SC3052 EU_OPT B Q1611
RT1P141C-T112 SC_RE2
R1648 Q1610 2SC3052
2K OPT
DTV/MNT_R_OUT SCART1_MUTE OPT R1681 E
D1601 EU_OPT EU_OPT 3 R1678 1K
L1602 EU_OPT 1
C1619 DTV/MNT_R_OUT EU_OPT 680
5.6V BLM18PG121SN1D C1610 4700pF EU_OPT C1636
OPT Q1608 2
1000pF 0.1uF
50V 2SC3052 EU_OPT
R1650
2K

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. REAR_JACK 17
SIDE CVBS PHONE JACK
(New Item Development)
SIDE_CVBS
L9903
JK9901 BLM18PG121SN1D
KJA-PH-1-0177 SIDEAV_CVBS_IN
5 M5_GND SIDE_CVBS
SIDE_CVBS R9907 +3.3V_Normal C9907
5A [YL]E-LUG D9901 100pF
75
4 M4 30V OPT
ADUC30S03010L_AMODIODE SIDE_CVBS
4A 10K SIDE_CVBS
[YL]O-SPRING R9915
3 M3_DETECT R9911 1K
3A SIDEAV_DET
[YL]CONTACT C9901
1 M1 OPT 100pF
4B D9902 SIDE_CVBS
[WH]O-SPRING 5.6V
6 M6 ADMC5M03200L_AMODIODE
3C [RD]CONTACT SIDE_CVBS SIDE_CVBS
SIDE_AV_GENDER L9902
4C [RD]O-SPRING BLM18PG121SN1D R9914
SIDEAV_L_IN
SIDE_CVBS
5C SIDE_CVBS R9906 SIDE_CVBS 10K SIDE_CVBS
[RD]E-LUG D9903
470K C9906 R9917
5.6V 12K
PPJ235-01 SIDE_CVBS 100pF
ADMC5M03200L_AMODIODE 50V SIDE_CVBS
JK9903 L9901
BLM18PG121SN1D R9913
SIDE_AV_3HOLE SIDEAV_R_IN
SIDE_CVBS SIDE_CVBS 10K SIDE_CVBS
D9904 SIDE_CVBS C9905 R9916
5.6V R9905 100pF 12K
470K
ADMC5M03200L_AMODIODE 50V
SIDE COMPONENT PHONE JACK

(New Item Developmen)
+3.3V_Normal
R9904
10K R9912
SIDE_COMP 1K
COMP2_DET
D9908 SIDE_COMP
5.6V
OPT
JK9902
KJA-PH-1-0177
5 M5_GND
R9910
75
4 M4
D9907 COMP2_Y+
SIDE_COMP
30V
3 M3_DETECT SIDE_COMP
1 M1 D9905
30V
75
6 M6 R9909
COMP2_Pb+
SIDE_COMP SIDE_COMP
SIDE_COMP
75
R9908
D9906 COMP2_Pr+
30V SIDE_COMP
SIDE_COMP

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SIDE_JACK 18
* Option name of this page : CI_SLOT
(because of Hong Kong)
CI Region
CI SLOT
+5V_CI_ON
CI_DATA[0-7] CI TS INPUT
AR1905 FE_TS_DATA[7]
CI_DATA[0-7]
33
+5V_Normal CI_MDI[7] FE_TS_DATA[6]
C1906 CI_MDI[6]
10uF FE_TS_DATA[5]
10V CI_MDI[5] FE_TS_DATA[4]
R1903
10K
EAG41860102 CI_MDI[4]
@netLa
CI_SLOT_JACK_LV3400
P1901 AR1906 FE_TS_DATA[3]
33
/CI_CD1 P1902 CI_MDI[3] FE_TS_DATA[2]
C1903 10067972-050LF
10067972-000LF CI_MDI[2] FE_TS_DATA[1]
0.1uF CI_MDI[1]
CI_SLOT_JACK FE_TS_DATA[0]
16V 35 1
CI_MDI[0]
R1908 100 36 2 CI_DATA[3]
R1921
CI_DATA[0-7]
37 3 CI_DATA[4]
AR1901
10K
33 CI_DATA[5] FE_TS_DATA[0-7]
CI_TS_DATA[4] 38 4
39 5 CI_DATA[6] AR1904
CI_TS_DATA[5] 33
40 6 CI_DATA[7] CI_MISTRT FE_TS_SYNC
CI_TS_DATA[6]
CI_TS_DATA[7] 41 7 R1919 47 FE_TS_VAL_ERR
/PCM_CE CI_MIVAL_ERR
42 8 CI_ADDR[10]
R1905 10K 43 9 FE_TS_CLK
CI_OE CI_MCLKI
44 10 CI_ADDR[11]
CI_IORD
45 11 CI_ADDR[9]
CI_IOWR
46 12 CI_ADDR[8]
47 13 CI_ADDR[13]
CI_MDI[0]
48 14 CI_ADDR[14]
CI_MDI[1]
CI_MDI[2] 49 15 CI_WE
50 16 R1920 100
CI_MDI[3] /PCM_IRQA
C1905 0.1uF 51 17
R1910 0 R1916 0
52 18 C1909
GND
OPT 53 19 OPT 0.1uF
CI_MDI[4]
GND
CI_MDI[5] 54 20
CI_ADDR[12]
CI HOST I/F
CI_MDI[6] 55 21
56 22 CI_ADDR[7]
CI_MDI[7]
R1906 10K 57 23 CI_ADDR[6]
R1902 47 58 24 CI_ADDR[5]
PCM_RST
R1901 47 59 25 CI_ADDR[4]
/PCM_WAIT
AR1902 60 26 CI_ADDR[3]
REG
33 61 27 CI_ADDR[2]
CI_TS_CLK
CI_TS_VAL 62 28 CI_ADDR[1]
CI_TS_SYNC 63 29 CI_ADDR[0]
64 30 CI_DATA[0]
65 31 CI_DATA[1]
CI_ADDR[0-14]
CI_TS_DATA[0] 66 32 CI_DATA[2]
33
CI_TS_DATA[1] 67 33
CI_TS_DATA[2] 68 34
CI_TS_DATA[3]
0
OPT
AR1903 G2
2 69 G1
1
R1909
CI_DET
R1907 100 IC1902
/CI_CD2 +3.3V_CI
+5V_Normal GND C1913
0.1uF
1OE VCC 16V
GND 1 20
TOSHIBA
1A1 2OE
R1904 PCM_A[0] 2 19
GND
0ITO742440D
10K C1904
0.1uF 2Y4 1Y1
CI_ADDR[7] 3 18 CI_ADDR[0]
16V
1A2 2A4
PCM_A[1] 4 17 PCM_A[7]
CI_MISTRT
CI_MIVAL_ERR
2Y3 1Y2
TC74LCX244FT
CI_MCLKI
1A3 2A3
PCM_A[2] 6 15 PCM_A[6]
2Y2 1Y3
1A4 2A2
PCM_A[3] 8 13 PCM_A[5]
2Y1 1Y4
CI DETECT CI_ADDR[4] 9 12 CI_ADDR[3]
GND 2A1
10 11 PCM_A[4]
+3.3V_Normal +3.3V_CI +3.3V_CI +3.3V_CI
CI_SLOT_OR_GATE_NXP
IC1901
74LVC1G32GW
L1901 B 1 5 VCC
/CI_CD2
R1917
BLM18PG121SN1D
0.1uF
C1908
10K
A 2
/CI_CD1
16V
GND 3 4 Y
OPT AR1907
C1901 C1902 GND
CI_DATA[0] 33 PCM_D[0]
R1915 CI_DATA[1] PCM_D[1]
CI_DET
CI_DATA[0-7]
0.1uF 0.1uF 47
CI_DATA[2] PCM_D[2]
R1918 CI_DATA[3] PCM_D[3]
OPT /PCM_CD
47
PCM_D[0-7]
CI_DATA[4] AR1908 PCM_D[4]
33
CI_DATA[5] PCM_D[5]
CI_DATA[6] PCM_D[6]
CI_DATA[7] PCM_D[7]
CI POWER ENABLE CONTROL
PCM_D[0-7]
CI_DATA[0-7]
+5V_CI_ON
+5V_Normal Q1902 L1902 AR1912
RSR025P03 BLM18PG121SN1D 33
S CI_ADDR[8] PCM_A[8]
D
CI_ADDR[9] PCM_A[9]
CI_ADDR[10] PCM_A[10]
C1907
C1910
0.1uF
R1923 C1912
0.1uF G 10K CI_ADDR[11] PCM_A[11]
0.1uF
16V C1911 16V
R1914 OPT
4.7uF 16V OPT
R1912 22K 16V
10K
AR1913
OPT 33
R1922 REG /PCM_REG
2.2K
C
R1913
10K B Q1901 AR1909
PCM_5V_CTL 33
2SC3052 CI_OE /PCM_OE
R1924 E CI_WE /PCM_WE
10K CI_IORD /PCM_IORD
CI_IOWR /PCM_IOWR

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. PCMCI 20
THE
THE CRITICAL COMPONENTS IN THE

Copyright © 2010 LG Electronics. Inc. All rights reserved.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SYMBOL MARK OF THE SCHEMETIC.

6.5T_GAS
8.5T_GAS 12.5T_GAS 9.5T_GAS 7.5T_GAS 5.5T_GAS MDS62110206
MDS62110209 MDS61887708 MDS61887710 MDS62110205 MDS62110204 GAS1
GAS1-*5 GAS1-*4 GAS1-*3 GAS1-*2 GAS1-*1
9.5T_GAS 7.5T_GAS 5.5T_GAS 6.5T_GAS
8.5T_GAS 12.5T_GAS
MDS62110205 MDS62110204
MDS62110209 MDS61887708 MDS61887710 MDS62110206
GAS2-*2 GAS2-*1
GAS2-*5 GAS2-*4 GAS2-*3 GAS2
8.5T_GAS 12.5T_GAS 9.5T_GAS 7.5T_GAS 5.5T_GAS

MDS62110209 MDS61887708 MDS61887710 MDS62110205 MDS62110204 6.5T_GAS
GAS3-*5 GAS3-*4 GAS3-*3 GAS3-*2 GAS3-*1 MDS62110206
9.5T_GAS 7.5T_GAS 5.5T_GAS GAS3

8.5T_GAS 12.5T_GAS
MDS61887710 MDS62110205 MDS62110204
MDS62110209 MDS61887708
GAS4-*3 GAS4-*2 GAS4-*1 6.5T_GAS
GAS4-*5 GAS4-*4
MDS62110206
9.5T_GAS 7.5T_GAS 5.5T_GAS GAS4
8.5T_GAS 12.5T_GAS
MDS61887710 MDS62110205 MDS62110204
SMD GASKET
MDS62110209 MDS61887708
GAS5-*5 GAS5-*4
MDS62110206
GAS5
9.5T_GAS 7.5T_GAS 5.5T_GAS
8.5T_GAS 12.5T_GAS
MDS61887710 MDS62110205 MDS62110204
MDS62110209 MDS61887708
GAS6-*5 GAS6-*4
MDS62110206
GAS6
9.5T_GAS 7.5T_GAS 5.5T_GAS
8.5T_GAS 12.5T_GAS
MDS61887710 MDS62110205 MDS62110204
MDS62110209 MDS61887708
GAS7-*5 GAS7-*4
MDS62110206
GAS7
GP2R
SMD_GAS
20
20101023

L/DIM_LED/DRIVER +3.3V_Normal
+3.3V_Normal
P2100
12507WR-08L
R2102
10K
LED_DRIVER_D/L
LED_DRIVER_D/L
OPT
1
R2101
R2100
2.2K
2.2K
R2103
10K
2
FRC_L/DIM_REVERSE_SEL
3 L/DIM_SCLK
5 L/DIM_MOSI
LED_DRIVER_D/L
R4029
22
6 LED_DRIVER_D/L_SCL
R4028
22
7 LED_DRIVER_D/L_SDA
LED_DRIVER_D/L
8 V_SYNC
9 C2100 C2101 C2102 C2103 C2104

18pF 18pF 18pF 18pF 18pF
50V 50V 50V 50V 50V
OPT OPT OPT OPT OPT

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. L/DIM_LED 21
TI solution RF-3D OPTION
+3.3V_Normal +3.3V_Normal
P3401
12507WR-12L
L3401
3D_SG 120-ohm
3.3V 3D_SG
1
GND
2
3D_SG R3410 R3411 R3412
R3402 2.7K 2.7K 2.7K
RX 100
3 M_REMOTE_RX 3D_SG 3D_SG 3D_SG
3D_SG
R3408
TX 100
4 M_REMOTE_TX
3D_SG
R3409
RESET 100
5 M_RFModule_RESET
3D_SG
R3407 FREQ. GPOIO_0 GPOIO_1 GPOIO_2
DC 100
6 DC_MREMOTE
3D_SG
R3401
3D Off 0 0 0
DD 100
7 DD_MREMOTE
60Hz 0 0 1
GND
8
3D_SG
R3406
59.94Hz 0 1 0
GPIO_0 22
9 3D_GPIO_0
3D_SG
R3404
50Hz 0 1 1
GPIO_1 22
10 3D_GPIO_1
3D_SG
R3405
RESERVED 1 0 0
GPIO_2 22
11 3D_GPIO_2
3D_SG
R3403
RESERVED 1 0 1
3D_SYNC 22
12 3D_SYNC_RF
RESERVED 1 1 0
13
.
RESERVED 1 1 1
ALL 3D-SG OPTION

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
LCD TV Repair Guide
`11 years New Basic Models
Contents
1. Product Roadmap
2. Main PCB layout
3. Block Diagram
4. Interconnection
5. Standard Repair Process
LCD TV EU Group
LCD TV Research Department
JAN. 28th, 2011

Overview for ’11 Year Model
LCD TV Repair Guide

`11 years New Models
< Applicable Basic Model >

xxLK330, xxLK430, xxLK450, xxLK530, xxLK550
xxLV2300, xxLV2500, xxLV2540, xxLV3400
xxLV3500, xxLV3550, xxLV5500, xxLV4500
xxLW4500 (3D)
Copyright © 2011 LG Electronics. Inc. All rights reserved. 2/22

Product Roadmap
2011
2011
Lamp
Edge
LED
3D

Main PCB
19/22/26LV2500 (50HZ)
To LCD Module
Main processor, DDR Memory

1 Flash Memory
2 Micom for Key/IR sensing

1
3 Audio AMP (5W+5W)
Adapter
* 19/22/26LV2500_S7 Reused (’11)

Main IC : LGE101_Mstar
Tuner Type : TDTJ-S001D (DVB-T/C)
Display Type (Resolution) : LED TV (1366 x 768)
Interface : HDMI 2EA , Component 1EA, AV 1EA, USB 1EA
Difference : Without FRC, HDMI Position , Resolution , Interface, Wafer
Position (Sub)

Main PCB
22/26LK330 (50HZ)
To LCD Module
Main processor, DDR Memory
1 Flash Memory
1 3 Audio AMP (5W+5W)
Adapter
* 22/26LK330_S7 Reused (’11)

Display Type (Resolution) : LCD TV (1366 x 768)
Position (Sub)

Main PCB
32/37/42/47LK450 (50HZ)
Power
To LCD Module Main processor, DDR Memory
1 Flash Memory
LVDS
1 3 Audio AMP (10W+10W)
IR
* 32/37/42/47LK450_S7 Reused (’11)

Display Type (Resolution) : LCD TV (1920 x 1080)
Position (Sub)

Main PCB
32/37/42/47/55LW4500 (100HZ)
LVDS Led Driver Power
4 Main processor, DDR Memory
1 Flash Memory

1
3 Audio AMP (10W+10W)
4 LED Driver connection (with local dimming)

2
IR
3
* 37LW4500_S7 Reused (’11)

Display Type (Resolution) : 3D, LED TV (1920 x 1080)
Difference : HDMI Position , Interface, Wafer Position (LVDS, Power, Sub)

Block diagram
DATA
Video
Tuner_SIF 41P Audio
Tuner_CVBS 51P
TUNER
SCL/SDA
(T/C) FE_TS_DATA[0]/CLK/Valid/Sync
30P
FRC
CI_TS_DATA[7:0]/CLK/Valid/Sync DDR3 X 16 X 1
PCMCIA
(1Gb X 1)
CI_DATA[7:0]
CI_ADDR[14:0] SPI
Flash(2Mb)
USB_DM/DP Only for FRC or 3D Model
USB
HP_OUT
H/P SYSTEM
DDR3 X 16 X2
HDMI_TMDS/HPD/CEC (1Gb)
Side HDMI3
LGE101 (S7)
SPI
LGE107 (S7+FRC) Flash(8Mb)
HDMI_TMDS/HPD/CEC
HDMI1
NAND
HDMI_TMDS/HPD/CEC
HDMI2 Flash(1Gb)
COMP_ YPbPr/ LR_IN
COMP1
AV_CVBS/LR_IN SCL/SDA SYSTEM EEPROM X 1
A/V1 (1Mb)
DSUB_RGB/ HVsync
PC-RGB SCL/SDA
DDC_SDA/UART_TX HDCP EEPROM X 1
PC_ Audio IN
(8Kb)
PC-AUDIO
SPDIF SPDIF_OUT Sub Micom

(NEC)
SC_CVBS/RGB/LR_IN
SCART SC_VIDEO/LR_OUT
I2S_I/F
Audio
SCL/SDA
Rear RS-232C
Debug _TX/RX AMP

Interconnection - 1
19/22LV2500 [PCBs]
1 Main PCB
2 Soft Touch Key/IR PCB

2
1
LED driver
3
1
[Cables]
1 Soft Touch key/IR cable
4
2 Main / Module LVDS cable
2
3 LED driver / Module cable
4 SPK cable
LCD Module

Interconnection - 2
19/22LV5500 [PCBs]
1 Main PCB

2
1
LED driver
3
1
[Cables]
4

2
4 SPK cable
LCD Module

Interconnection - 3
26LV2500 [PCBs]
1 Main PCB
LED driver 2 Soft Touch Key/IR PCB

2
3 1
1
[Cables]
4

2
4 SPK cable
LCD Module

Interconnection - 4
26LV5500 [PCBs]
1 Main PCB
LED driver 2 Soft Touch Key/IR PCB

2
3 1
1
[Cables]
4

2
4 SPK cable
LCD Module

Interconnection - 5
32LV2500 [PCBs]
1 Main PCB
2 3 2 PSU
1 3 Soft Touch Key/IR PCB
1
5 4 Timing controller
5 LED Driver
6
4 4 [Cables]
5
1 Main / PSU cable

3
LCD Module 3 LED driver / Module cable
4 SPK cable

LED driver / PSU cable
6
14P

Interconnection - 6
37LV3400 [PCBs]
1 Main PCB
3 2 PSU
1
5
4 Timing controller
2
6
5 LED Driver
4 4 [Cables]
5
1 Main / PSU cable

3
4 SPK cable

6
14P

Interconnection - 7
37LV3550 [PCBs]
1 Main PCB
3 2 PSU
2
6 1 3 Soft Touch Key/IR PCB
1
5
4 Timing controller
5 LED Driver
4
4
[Cables]
5
1 Main / PSU cable

3
4 SPK cable

6
14P

Interconnection - 8
42LV4500 [PCBs]
1 Main PCB
3 2 PSU + LED driver
1
4 Timing controller
2
2
4
5 [Cables]
4
1 Main / PSU cable

3
4 SPK cable

Interconnection - 9
42LW4500 [PCBs]
1 Main PCB
3 2 PSU + LED driver
1
6 1
4 Timing controller
2
2
4
4
[Cables]
5
1 Main / PSU cable

3
4 SPK cable
Local dimming signal cable

6
(Main / LED driver 8pin)

Interconnection - 10
32LK530 [PCBs]
1 Main PCB
6 2 PSU (without inverter)

5
2 3 IR & Indicator PCB
1
1 4 Local Key PCB
5 Inverter
2 Timing controller
6
5
4 4
[Cables]
3 1 Main / PSU cable
3 2 Main / Module LVDS cable
LCD Module 3 SPK cable
4 IR/Local key cable
5 Inverter/PSU cable
(14pin)

37LK430 [PCBs]
1 Main PCB
2 3 IR & Indicator PCB

1
4 Local Key PCB
1
5 Timing controller
2
4 [Cables]
4

3
4 IR/Local key cable

42LK450 [PCBs]
1 Main PCB

4 2 1 4 Inverter
1 5 Timing controller
2
5
4 [Cables]

3
5 Inverter/PSU cable
(14pin)

Interconnection – sub PCB( LV**/LK450 Series )
SPK unit
Soft Touch Key/IR PCB To Main

15pin Cable

Interconnection – sub PCB( LK430/LK530 Series )
SPK unit
SPK unit
Tact key IR/Sensor To Main

12pin Cable

Contents of LCD TV Standard Repair Process
No. Error symptom (High category) Error symptom (Mid category) Page Remarks
1 No video/Normal audio 1
2 No video/No audio 2
3 A. Video error Video error, video lag/stop 3
4 Color error 4
Vertical/Horizontal bar, residual image,

5 5
light spot, external device color error
6 No power 6
B. Power error Off when on, off while viewing, power auto
7 7
on/off
8 No audio/Normal video 8
C. Audio error
9 Wrecked audio/discontinuation/noise 9
No response in remote controller, key error,
10 10
D. Function error recording error, memory error
11 External device recognition error 11
12 E. Noise Circuit noise, mechanical noise 12
13 F. Exterior error Exterior defect 13
First of all, Check whether there is SVC Bulletin in GCSC System for these model.
Standard Repair Process
Established
Error A. Video error date 2010. 2 .19
LCD TV symptom
No video/ Normal audio Revised date 1/13
First of all, Check whether all of cables between board is inserted properly or not.
(Main B/D↔ Power B/D, LVDS Cable,Speaker Cable,IR B/D Cable,,,)
☞A1 ☞A4
No video Normal Y Check Back Light Y Check Power Normal Y Replace T-con
Normal audio On Board or module
audio On with naked eye Board voltage
12v,3.5v etc.
N N N
Move to No
☞A2 Check Power Board 20V /12V or 24v output Repair Power
video/No audio Board or parts
Replace Inverter
Normal Y
or module
voltage
End
N
Repair Power
Board or parts
※Precaution ☞A7 & A3

Always check & record S/W Version and White
Balance value before replacing the Main Board Replace Main Board Re-enter White Balance value

Only for training and service purposes 1
Established
LCD TV symptom
No video/ No audio Revised date 2/13
☞A4
Check various Check and
Normal Y
No Video/ voltages of Power replace
No audio Board voltage?
MAIN B/D
( 3.5V,12V,20V or
24V…) N End
Replace Power
Board and repair
parts

Established
Error A. Picture Problem date 2010. 2 .19
LCD TV symptom
Picture broken/ Freezing Revised date 3/13
. By using Digital signal level meter

☞ A6
. By using Diagnostics menu on OSD
Check RF Signal level ( Menu→Red key→Signal test)
- Signal strength (Normal : over 50%)
- Signal Quality (Normal: over 50%)
Y Check whether other equipments have problem or not.

Normal
(By connecting RF Cable at other equipment)
Signal?
→ DVD Player ,Set-Top-Box, Different maker TV etc`
N
☞ A7
Check RF Cable
Normal Y Check SVC N
Connection Check Normal Y
1. Reconnection Picture? S/W Version Bulletin? Tuner soldering Close
Picture?
2. Install Booster
N Y
N
S/W Upgrade Replace
Normal N Contact with signal distributor Main B/D
Picture? or broadcaster (Cable or Air)
Normal N
Y Picture?
Y
Close
Close

Established
LCD TV symptom
Color error Revised date 4/13
☞A8
☞ A10/ A11
※ Check Y
Check color by input
and replace
-External Input Y Y
Color Link Cable Color Color
-COMPONENT Replace Main B/D Replace module
error? (LVDS) and error? error?
-RGB
contact
-HDMI/DVI N N N
condition
Check error End

color input
mode
☞A12 Check
External Input/ External device Y
external
Check Test pattern Component /Cable Replace Main B/D
device and
error normal
cable
N
Request repair
for external
device/cable
RGB/ Check external External device Y

HDMI/DVI device and /Cable Replace Main B/D
error cable normal

A. Video error Established

Error date 2010. 2 .19
LCD TV symptom Vertical / Horizontal bar, residual image,
Revised date 5/13
light spot, external device color error
Vertical/Horizontal bar, residual image, light spot Replace

Module
☞A8
☞ A10/ A11 N
Check color condition by input Check external
Y Check and
-External Input Screen Y device Screen N Replace Main Screen
-Component Normal? replace Link
normal? connection normal? B/D normal?
-RGB Cable
condition
-HDMI/DVI
N N Y
Y
Replace Request repair End End

for external
☞A12 module
device
Check Test pattern
External device screen error-Color error

Check screen
condition by
input External
Check S/W Version Check N
-External Input Input Connect other external N
version
-Component error device and cable Screen Replace
-RGB (Check normal operation of normal? Main B/D
Y -HDMI/DVI External Input, Component,
Component RGB and HDMI/DVI by
error Y
S/W Upgrade connecting Jig, pattern
Generator ,Set-top Box etc.
Request repair for
external device
RGB
Normal Y
error Connect other external
screen? N
device and cable N
(Check normal operation of Screen Replace
Y External Input, Component, normal? Main B/D
HDMI/ RGB and HDMI/DVI by
End DVI connecting Jig, pattern
Generator ,Set-top Box etc.
Established
Error B. Power error date 2010. 2 .19
LCD TV symptom
No power Revised date 6/13
☞A17 ☞A19
DC Power on
Check Power LED Y Normal N Check Power Y Replace
by pressing Power Key OK? Power
Power LED On? operation? On ‘”High”
On Remote control B/D
. Stand-By: Red N N
Y
. Operating: white
Check Power cord Replace Main B/D
was inserted properly
☞A4
N Measure voltage of each output of Power B/D
Normal?
Y
Y Y
※ Normal
voltage?
Replace Main B/D
Close Normal
Check ST-BY 5V Y
voltage? N
☞A18
Replace Power B/D
N
Replace Power
B/D

Established
Error B. Power error date 2010. 2 .19
LCD TV symptom
Off when on, off while viewing, power auto on/off Revised date 7/13
Check outlet
☞A22
N Y
Check A/C cord Error? Check Power Off CPU Normal? End
Replace Main B/D
Mode Abnormal
N
Check for all 3- phase
power out Y Abnormal Replace Power B/D
1
Fix A/C cord & Outlet ☞A19

and check each 3
(If Power Off mode
phase out
is not displayed) Normal Y
Replace Main B/D
Check Power B/D voltage?
voltage
N
※ Caution
Check and fix exterior
Replace Power B/D
of Power B/D Part
* Please refer to the all cases which Status Power off List Explanation
"POWEROFF_REMOTEKEY" Power off by REMOTE CONTROL
can be displayed on power off mode.
"POWEROFF_OFFTIMER" Power off by OFF TIMER
"POWEROFF_SLEEPTIMER" Power off by SLEEP TIMER
"POWEROFF_INSTOP" Power off by INSTOP KEY
"POWEROFF_AUTOOFF" Power off by AUTO OFF
Normal "POWEROFF_ONTIMER" Power off by ON TIMER
"POWEROFF_RS232C" Power off by RS232C
"POWEROFF_RESREC" Power off by Reservated Record
"POWEROFF_RECEND" Power off by End of Recording
"POWEROFF_SWDOWN" Power off by S/W Download
"POWEROFF_UNKNOWN" Power off by unknown status except listed case
"POWEROFF_ABNORMAL1" Power off by abnormal status except CPU trouble
Abnormal
"POWEROFF_CPUABNORMAL" Power off by CPU Abnormal
Established
Error C. Audio error date 2010. 2 .19
LCD TV symptom
No audio/ Normal video Revised date 8/13
☞A24 ☞A25
Check user N Check audio B+ Y
No audio Normal
menu > Off 20V or 24V of
Screen normal voltage
Speaker off Power Board
Y N
Cancel OFF Replace Power Board and repair parts
Check N
Disconnection Replace MAIN Board End
Speaker
disconnection
Y
Replace Speaker

Established
Error C. Audio error date 2010. 2 .19
LCD TV symptom
Wrecked audio/ discontinuation/noise Revised date 9/13
→ abnormal audio/discontinuation/noise is same after “Check input signal” compared to No audio
☞A25
Wrecked audio/
Check and replace
Discontinuation/ Check audio
speaker and
Noise for B+ Voltage (20V or 24V)
connector
Check input all audio
signal Y Y
Signal
-RF
normal? Wrecked audio/
-External Input Normal
signal Discontinuation/
N Replace Main B/D voltage?
Noise only
for D-TV
N
Wrecked audio/
Discontinuation/
Replace Power B/D
Noise only
for Analog
(When RF signal is not
received)
Request repair to external Wrecked audio/ Replace Main B/D End
cable/ANT provider Discontinuation/
Noise only
(In case of for External Input
N
External Input Connect and check Normal
signal error) other external audio?
Check and fix device
external device Y
Check and fix external device

D. General Function Problem Established

Error date 2010. 2 .19
LCD TV symptom
Remote control & Local switch checking Revised date 10/13
1. Remote control(R/C) operating error Replace

Main B/D
☞A27 ☞A27
☞A27
Check & Repair N Check Y Y
Check R/C itself Normal Y Normal Normal Check IR Normal
Cable connection voltage
Operation operating? operating? Voltage? Output signal Signal?
Connector solder On Main B/D
N
Y N N
☞A4
Check R/C Operating Check & Replace Close Check 5v on Power B/D Repair/Replace
When turn off light Baterry of R/C Replace Power B/D or IR B/D
in room Replace Main B/D
(Power B/D don’t have problem)
If R/C operate, Normal
Close
Explain the customer operating?
cause is interference
from light in room. N
Replace R/C

Established
Error D. Function error date 2010. 2 .19
LCD TV symptom
External device recognition error Revised date 11/13
Y Check technical
Check External Input and
Signal information Technical N
input Component Replace Main B/D
input? - Fix information information?
signal Recognition error
- S/W Version
N Y
RGB,HDMI/
Check and fix DVI, Optical
Fix in Replace Main B/D
external device/cable Recognition error
accordance
with technical
information

Established
Error E. Noise date 2010. 2 .19
LCD TV symptom
Circuit noise, mechanical noise Revised date 12/13
Replace PSU(with LED driver)

Identify Check
Circuit OR
nose location of
noise
type noise Replace LED driver
Mechanical Check location

noise of noise
※ When the nose is severe, replace the module

(For models with fix information, upgrade the
S/W or provide the description)
※ Mechanical noise is a natural OR
phenomenon, and apply the 1st level ※ If there is a “Tak Tak” noise from the
description. When the customer does not cabinet, refer to the KMS fix information and
agree, apply the process by stage. then proceed as shown in the solution manual
※ Describe the basis of the description OR
(For models without any fix information,
in “Part related to nose” in the Owner’s provide the description)
Manual.

Established
Error F. Exterior defect date
2010. 2 .19
LCD TV symptom
Exterior defect Revised date 13/13
Zoom part with Module

Replace module
exterior damage damage
Cabinet
damage Replace cabinet
Remote
controller Replace remote controller
damage
Stand
dent Replace stand

Contents of LCD TV Standard Repair Process Detail Technical Manual
No. Error symptom Content Page Remarks
1 Check LCD back light with naked eye A1
2 LED driver B+ 24V measuring method A2
A. Video error_ No video/Normal audio
3 Check White Balance value A3
4 Power Board voltage measuring method A4
6 TUNER input signal strength checking method A6
A. Video error_ No video/Video lag/stop
7 LCD-TV Version checking method A7
9 LCD TV connection diagram A8
10 Tuner Checking Part A9
A. Video error_Color error Check Link Cable (LVDS) reconnection A10 A10 : Edge LED
11
condition A11 A11 : Lamp
12 Adjustment Test pattern - ADJ Key A12
13 LCD TV connection diagram A8
A. Video error_Vertical/Horizontal bar, Check Link Cable (LVDS) reconnection A10 A10 : Edge LED
14
residual image, light spot condition A11 A11 : Lamp
15 Adjustment Test pattern - ADJ Key A12
16 Exchange T-Con Board (1) A-1/5
17 Exchange T-Con Board (2) A-2/5

<Appendix>
18 Defected Type caused by T-Con/ Exchange LED driver Board (PSU) A-3/5
Inverter/ Module
19 Exchange Module itself (1) A-4/5
20 Exchange Module itself (2) A-5/5

Continue to the next page
Contents of LCD TV Standard Repair Process Detail Technical Manual
Continued from previous page
No. Error symptom Content Page Remarks
21 Check front display LED A17
22 Check power input Voltage & ST-BY 5V A18
23 B. Power error_No power Checking method when power is ON A19
24 POWER BOARD voltage measuring method A4
25
B. Power error_Off when on, off while
26 POWER OFF MODE checking method A22
viewing
B. Power error_Off when on, off while POWER BOARD PIN voltage checking
27 A19
viewing method
Checking method in menu when there is no
28 A24
audio
C. Audio error_No audio/Normal video
Voltage and speaker checking method when
29 A25
there is no audio
C. Audio error_Wrecked Voltage and speaker checking method in
30 A25
audio/discontinuation case of audio error
D. Function error_ No response in Remote controller operation checking
31 A27
remote controller, key error method

Standard Repair Process Detail Technical Manual
Error Established
symptom A. Video error_No video/Normal audio date
2011. 2 .07
LCD TV
Revised
Content Check LCD back light with naked eye A1
date
<ALL MODELS>
After turning on the power and disassembling the case, check with the naked eye,
whether you can see light from 4 locations.

Only for training and service purposes A1
Error Established
A. Video error_No video/Normal audio 2011. 2 .07
symptom date
LCD TV
Revised
Content LED driver/lamp inverter B+ 24V measuring method A2
date
Check the DC 24V, 12V, 3.5V and Inverter on
Edge LED PSU without LED Driver
* 26” ~ 47” : `11 Pin map

Lamp (Power Board ↔ Inverter)
- PSU
14 Pin
1~5 24V
6 ~ 10 GND
11 Detect
12 Inverter On/Off
Lamp PSU without inverter 13 Int. PWM
14 Ext. PWM (PDIM)

Error Established
A. Video error_No video/Normal audio 2011. 2 .07
symptom date
LCD TV
Revised
Content Check White Balance value A3
date
<ALL MODELS>
Entry method
Entry method
1.
1. Press
Press the
the ADJ
ADJ button
button on
on the
the remote
remote controller
controller for
for adjustment.
adjustment.
2.
2. Enter
Enter into
into White
White Balance
Balance of
of item
item 6.
7.
3.
3. After
After recording
recording the
the R,
R, G,
G, B
B (GAIN,
(GAIN, Cut)
Cut) value
value of
of Color
Color Temp
Temp
(Cool/Medium/Warm),
(Cool/Medium/Warm), re-enter the value after replacing the
re-enter the value after replacing the MAIN
MAIN BOARD.
BOARD.

Error Established
symptom A. Video error_No video/ Audio date
2011. 2 .07
LCD TV
Revised
Content Power Board voltage measuring method A4
date
Check the DC 20Vor24V, 12V, 3.5V.
24 Pin (Power Board ↔ Main Board)
FW20020-24SB (FOOSUNG)
1 Power on 2 20V (24V)
3 20V (24V) 4 20V (24V)
5 GND 6 GND
7 GND 8 GND
Edge LED PSU without LED Driver 9 3.5V 10 3.5V
11 3.5V 12 3.5V
13 GND 14 GND
15 GND 16 GND
17 12V 18 Inverter On/off
19 12V 20 Lamp : A-Dim
21 12V 22 PWM Dim #1
23 N.C 24 Error-out
Lamp PSU without inverter

Error Established
A. Video error_Video error, video lag/stop 2011. 2 .07
symptom date
LCD TV
TUNER input signal strength checking method Revised
Content A6
date
<ALL MODELS>
MENU -Æ red key(customer support -Æ signal test

-Æ select channel
When the signal is strong, use the

attenuator (-10dB, -15dB, -20dB etc.)

Error Established
symptom A. Video error_Video error, video lag/stop date
2011. 2 .07
LCD TV
LCD-TV Version checking method Revised
Content A7
date
<ALL MODELS> 1. Checking method for remote controller for adjustment
Version
Press the IN-START with the

remote controller for adjustment

Error A. Video error _Vertical/Horizontal bar, Established 2011. 2 .07
symptom residual image, light spot date
LCD TV
Revised
Content LCD TV connection diagram (1) A8
date
As the part connecting to the external input, check

the screen condition by signal

Error Established
symptom
A. Video error_Video error, video lag/stop 2011. 2 .07
LCD TV date
TUNER checking part Revised
Content A9
date
<ALL MODELS>
Checking method:
1. Check the signal strength or check whether the screen is normal when the external device is connected.
2. After measuring each voltage from power supply, finally replace the MAIN BOARD.

Error Established
symptom A. Video error_Color error date
2011. 2 .07
LCD TV
Revised
Content Check Link Cable (LVDS) reconnection condition A10
date
<LV** : Edge LED Series Models>
Check the contact condition of the Link Cable, especially dust or mis insertion.

Error Established
symptom A. Video error_Color error date
2011. 2 .07
LCD TV
Revised
Content Check Link Cable (LVDS) reconnection condition A11
date
<LK** : Lamp series Models>
Check the contact condition of the Link Cable

Error Established
symptom
A. Video error_Color error 2011. 2 .07
LCD TV date
Adjustment Test pattern - ADJ Key Revised
Content A12
date
You can view 6 types of patterns using the ADJ Key
Checking item : 1. Defective pixel 2. Residual image 3. MODULE error (ADD-BAR,SCAN BAR..)
4.Video error (Classification of MODULE or Main-B/D!)

Appendix : Exchange T-Con Board (1)
Solder defect, CNT Broken Solder defect, CNT Broken Solder defect, CNT Broken
Solder defect, CNT Broken T-Con

T-Con Defect,
Defect,
Solder
T-Con CNT
CNT
defect,CNT
Defect, Broken
Broken
CNTBroken
Broken Abnormal Power Section
Solder defect, Short/Crack Abnormal Power Section Solder defect, Short/Crack
Copyright © 2011 LG Electronics. Inc. All rights reserved. A - 1/5 LGE Internal Use Only
Appendix : Exchange T-Con Board (2)
Abnormal Power Section Abnormal Power Section Solder defect, Short/Crack
Solder defect, Short/Crack Fuse Open, Abnormal power section Abnormal Display
GRADATION Noise GRADATION

Copyright © 2011 LG Electronics. Inc. All rights reserved. A - 2/5 LGE Internal Use Only
Appendix : Exchange PSU(LED driver)
No Light Dim Light
Dim Light Dim Light
No picture/Sound Ok
Copyright © 2011 LG Electronics. Inc. All rights reserved. A – 3/5 LGE Internal Use Only
Appendix : Exchange the Module (1)
Panel Mura, Light leakage Panel Mura, Light leakage Press damage
Crosstalk Press damage Crosstalk
Un-repairable Cases
In this case please exchange the module.
Press damage
Appendix : Exchange the Module (2)
Vertical Block Vertical Line Vertical Block

Source TAB IC Defect Source TAB IC Defect Source TAB IC Defect
Horizontal Block Horizontal

Gate TAB ICBlock
Defect Horizontal line
Gate TAB IC Defect
Gate TAB IC Defect Gate TAB IC Defect Gate TAB IC Defect
Un-repairable Cases
In this case please exchange the module.
Horizontal Block
Gate TAB IC Defect
Gate TAB IC Defect
Error Established
symptom B. Power error _No power date
2010. 2 .19
LCD TV
Revised
Content Check front display LED A17
date
Front LED control :

Menu Æ Option Æ Power Indicator
Æ Standby light ON
ST-BY condition: Red

Power ON condition: white

Error Established
2011. 2 .07
LCD TV
Revised
Content Check power input voltage and ST-BY 3.5V A18
date
For ’11 models, there is no voltage out for st-by purpose.

When st-by, only 3.5V is normally on.
Check the 3.5V when st-by
3 20V (24V) 4 20V (24V)
5 GND 6 GND
7 GND 8 GND
11 3.5V 12 3.5V
13 GND 14 GND
15 GND 16 GND
21 12V 22 PWM Dim #1
23 N.C 24 Error-out

Error Established
2011. 2 .07
LCD TV
Revised
Content Checking method when power is ON A19
date
Check “power on” pin is high
3 20V (24V) 4 20V (24V)
5 GND 6 GND
7 GND 8 GND
11 3.5V 12 3.5V
13 GND 14 GND
15 GND 16 GND
21 12V 22 PWM Dim #1
23 N.C 24 Error-out

Error
symptom B. Power error _Off when on, off whiling viewing Established 2011. 2 .07
LCD TV date
Revised
Content POWER OFF MODE checking method A22
date
<ALL MODELS>
Entry method
1. Press the IN-START button of the remote

controller for adjustment
2. Check the entry into adjustment item 3

Error Established
symptom C. Audio error_No audio/Normal video 2011. 2 .07
LCD TV date
Revised
Content Checking method in menu when there is no audio A24
date
<ALL MODELS>
Checking method
1. Press the MENU button on the remote controller
2. Select the AUDIO function of the Menu
3. Select TV Speaker from Off to On

Error Established
symptom C. Audio error_No audio/Normal video date
2011. 2 .07
LCD TV
Voltage and speaker checking method Revised
Content A25
when there is no audio date
<ALL MODELS>
② ①
Edge LED PSU without LED Driver
Checking order when there is no audio
① Check the contact condition of 20V or 24V connector of Main Board
② Measure the 24V input voltage supplied from Power Board

(If there is no input voltage, remove and check the connector)
③ Connect the tester RX1 to the speaker terminal and if you hear the Chik Chik sound when you touch the
GND and output terminal, the speaker is normal.

Error D. Function error_ No response in remote controller, Established 2011. 2 .07
symptom key error date
LCD TV
Revised
Content Remote controller operation checking method A27
date
<ALL MODELS>
P2401, P2402
1 EYEQ_SCL
2 EYEQ_SDA
3 GND
4 KEY1
3
5 KEY2
6 St 3.3V
7 GND
8 LED_B
9 IR
10 GND
4 11 Normal 3.3V
1
12 LED_R
13 GND
2 14 Soft Touch_SCL
15 Soft Touch_SDA
Checking order
1, 2. Check IR cable condition between IR & Main board.
3. Check the st-by 3.3V on the terminal 6.
4. When checking the Pre-Amp when the power is in ON condition, it is normal when the
Analog Tester needle moves slowly, and defective when it does not move at all.


32lv3550-Zb Chassis Ld01u

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Internal Use Only

North/Latin America http://aic.lgservice.com

P/NO : MFL62863056 (1102-REV00) Printed in Korea

PRODUCT SAFETY ................................................................................. 3

ADJUSTMENT INSTRUCTION ................................................................ 9

EXPLODED VIEW .................................................................................. 16

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

Before returning the receiver to the customer, AC Volt-meter

always perform an AC leakage current check on the exposed

1. Application range 3. Test method

4. Model General Specification

Case1 : Software version up (6)

1. After downloading S/W by USB, TV set will reboot

3. Main PCB check process

* Boot file Download

<Caution> Using ‘power on’ button of the Adjustment R/C,

* ADC Calibration Protocol (RS232)

• xb 00 40 [Component1 Input (480i)]

CIM 18276 18986 55337 26904 352

4) Completed selecting Tool option.

RS-232C Communication 4.2. DDC EDID Write (RGB 128Byte )

*: Serial No : Controlled / Data:01 10 c 01 03 68 10 09 78 0A EE 91 A3 54 4C 99 26

**: Month : Controlled / Data:00 20 0F 50 54 A1 08 00 81 80 61 40 45 40 31 40 01 01

Download A E 00 10 Automatically Download

Cont rol si gnal Volta ge

- Adjust sequence CMD : A0h

=> Check the Download to CI+ Key value in LGset.

2) check the key download for transmitted command

2. Check the method of CI+ Key value (RS232)

2) Check the method of CI+ key by command (RS232 :

Only for training and service purposes

CI _ADDR[ 14:0] SPI

Copyright ©2011 LG Electronics. Inc. All rights reserved.

AV_CVBS/ LR_I N SCL/ SDA SYSTEM EEPROM X 1

SPDI F SPDI F_OUT Sub Micom

LGE Internal Use Only

* Stand Base + Body

NAND FLASH MEMORY +3.3V_Normal

PCM_D2 GPIO147/TCON4 5V_DET_HDMI_4

AL I/O3 PCM_A[3] PCM_A9 GPIO6/PM0/INT0 USB1_OCD

C112 PWM0 W23 C5

S7MR-PLUS I2C +3.3V_Normal

FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8] FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8] FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8] FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8]

HDCP_EEPROM_CATALYST_OLD EEPROM_1MBIT_ST AF14

IC103 IC104 AD13

4.7K 0.1uF AF4

AB16 AB16 AB16 AB16

8pF 8pF FRC_GPIO8

OPT OPT Y11

Y10 Y10 Y10 Y10

AB15 AB15 AB15 AB15

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

NO_FRC : LOW LOW +2.5V_Normal

U3_INTERNAL : HIGH LOW

U5_EXTERNALBOOT :HIGH HIGH L214

: Only 3D_SG GPIO OUTPUT CONTROL

+3.3V_Normal VDD33 H11 G18

VDD33_T/VDDP/U3_VD33_2:47mA VDDC_2 GND_2

BLM18PG121SN1D H14 H18

DDC_SCL_2 X201 VDD33_DVI:163mA

D5 24MHz +3.3V_Normal VDD33_DVI AVDD_DMPLL J7 M14

DSUB_HSYNC R4025 22 HSYNC0 LINE_IN_1L AV_L_IN VDDP_1 GND_62