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1
Tutorial
October 2009
Qi Wang
Cadence Design Systems, Inc.
LPC Vice Chair, LPC, Si2
● Ensures
Consistent Representation
Consistent Integration style
Consistent Verification
Consistent Rules, semantics, precedence policy.
● Top level and block level power structures are linked together using
power domain mapping
Multiple levels of hierarchy are supported
● Main Features
Merge and reconfigure power domains
Reconfigure power rules
Resolve precedence
Integrate power modes
get_parameter parameter_name
include
Block1
I1 I2
Iso Rule
un- External
switched Switchable
(PDOn) (PDExt)
I1 I2 I1 I2
Iso Rule
Iso Rule
un- External un- External
switched Switchable swithced Switchable
include Block1.cpf
set_design Top –ports { Iso Pwr }
create_power_domain –name AON
create_power_domain –name Int –shutoff_condition { !Pwr }
set_instance X1 –domain_mapping { { PDOn AON } { PDExt AON } } –design Block1
set_instance X2 –domain_mapping { { PDOn AON } { PDExt Int } } –design Block1 \
-port_mapping { {IsoExt Iso} }
end_design
Top Switch
un-
switched Internal
Switched
X1 X2
I1 I2 I1 I2
Iso Rule
un- un- Internal
un-switched
switched switched Switched
Block1 Block1
top I1
top I1
myIP1 myIP1
internal
switchable
(PDRed)
pso myIP2
PCM pso myIP2
restore PCM
restore
unswitched
(PDBlue)
unswitched
(PDBlue)
VDD
D1
● Multiple power ports (VDD, VPP)
iso1
Switches ● Different types of domains
iso2 Un-
switched Internally ● Domain with retention
Isolation
ret (AON) Switched D4 ● Domain without retention
pwr (PSO)
State ● Inputs isolated (D3)
D2 Retention
● Inputs not isolated (D2)
Isolation
● Outputs isolated (D4)
● Outputs not isolated (D5)
Isolation
D3
Externally ● Internal crossing with isolation
Switched D5
NC
● Feed-through (F1, F2)
(EXT)
F1
● Floating port (NC)
F2 VSS VPP
set_macro_model macro_cell_name
end_macro_model
set_wire_feedthrough_ports list_of_ports
set_floating_ports list_of_ports
Isolation
ret Switched
(AON) D4
create_power_domain -name AON –default \ pwr
State
-boundary_ports { D1 D4 iso* ret pwr} D2 Retention
update_power_domain –name AON \ Isolation
–primary_power_net VDD \
Isolation
–primary_ground_net VSS D3 Externally
Switched
NC (EXT) D5
F1
create_power_domain –name EXT \
F2 VSS VPP
-boundary_ports { D3 D5 }
update_power_domain –name EXT \
notes on domain EXT
-primary_power_net VPP \ port D5 is associated with EXT
-primary_ground_net VSS
● Inputs are NOT isolated inside the macro model but it requires
isolation when the drivers can be switched off in the design
context\
Define an isolation rule for the input ports without isolation condition and
with “isolation_output” to define what the valid “clamp” value should be
when the driver is switched off.
Isolation
ret Switched
–isolation_output high (AON) D4
pwr
notes on rule IsoOut State
D2
port D4 belongs to the default domain AON Retention
Isolation
create_isolation_rule –name IsoInReq \
–to PSO –pins { D2 } \
Isolation
D3 Externally
–isolation_output low Switched
NC (EXT) D5
notes on rule IsoInReq F1
D2 has no internal isolation. The rule specify a F2 VSS VPP
constraint: if D2 is driven by a switchable domain
(after instantiated at top), it needs to be isolated to low create_isolation_rule –name IsoInt \
when the domain is off
–from EXT –to PSO \
create_isolation_rule –name IsoIn \ –isolation_condition iso2 \
–to EXT –pins { D3 } \ –isolation_output low
–isolation_condition iso1 \ notes on rule IsoInt
–isolation_output low This rule covers an internal crossing
notes on rule IsoIn
port D3 belongs to the domain EXT
VDD
create_state_retention_rule –name PSO_RET \ D1
-domain PSO –secondary_domain AON \ iso1
Switches
iso2 Un-
-save_edge ret switched Internally
Isolation
ret Switched
(AON) D4
pwr
State
notes on state retention rule D2 Retention
Use the register names in –instances if you want Isolation
to apply the rule only to those registers
Isolation
No need to use update_state_retention_rule D3 Externally
Switched
AON domain is the secondary domain of the NC (EXT) D5
retention logic by default F1
F2 VSS VPP
Isolation
ret Switched
(AON) D4
commands pwr
State
D2 Retention
Isolation
Isolation
D3 Externally
Switched
NC (EXT) D5
set_wire_feedthrough_ports { F1 F2 } F1
F2 VSS VPP
Isolation
ret Switched
(AON) D4
pwr
State
D2 Retention
Isolation
Isolation
D3 Externally
Switched
NC (EXT) D5
set_floating_ports { NC }
F1
F2 VSS VPP
Isolation
ret Switched
(AON) D4
create_power_domain –name PDRed \ pwr
State
–shutoff_condition pso \ Switches D2 Retention
-default_isolation_condition I1/iso1 \ Internally Isolation
Internally
-base_domains PDBlue Switched
Switched
Isolation
-instances … (PDRed) D3 Externally
State Switched
NC (EXT) D5
Retention
update_power_domain –name PDRed \ F1
-primary_ground_net VSS
……
end_design
Isolation
On
(AON) Internally
create_power_domain –name PDRed \ ret
pwr
Switched D4
–shutoff_condition pso \ State
-default_isolation_condition I1/iso1 \ Switches D2 Retention
-base_domains PDBlue Internally
-instances … Switched
Isolation
Externally
(PDRed) D3 Externally D5
Switched
State NC Switched
(EXT)
update_power_domain –name PDRed \
Retention F1
-primary_power_net VDD_SW
-primary_ground_net VSS F2 VSS VPP
VDD
no isolation needed: there is no domain D1
crossing, i.e. both drivers and receivers are Un- iso1
in the same domain switched
iso2 Un-
Switches
(PDBlue) switched Internally
Isolation
ret Switched
(AON) D4
pwr
isolation may be needed: if the driver State
Switches D2 Retention
domain can be off while the receiver is on,
Isolation
need to have an isolation rule at top level for Internally
Internally
isolation insertion Switched
Switched
Isolation
(PDRed) D3 Externally
Switched
State NC (EXT) D5
No isolation needed: pin D3 is isolated Retention
F1
internally and the crossing is not a domain VSS VPP
F2
crossing because domain PDRed merged
with domain EXT
Declare port O
Declare port I belonging to the
belonging to the power domain
power domain corresponding to
corresponding to VDD_EXT
VDD_EXT I
Core
O
level shifters
Innovation Through Collaboration – Low Power Coalition – 29 –
Improved Power Mode and
Mode Transition Modeling
● In addition to ‘on’ and ‘off’ state, included new ‘standby’ state
A state where cells can maintain its value but cannot support computation
A ‘standby’ state can be achieved by source biasing or reverse body biasing
● Be able to define states of a power domain along with the conditions to
enable
● Be able to specify mode transition time and domain transition time when a
mode transition happens
Always-on(Constant)
Follow pin connected to Power
switchable power
(primary power net) Switched Cells Physical View
Always on domain
PD1
Logical View
Switchable domain
PD2
● Additional power/ground pin other than the follow pins in standard cell
technology.
● Special low power cells:
Always on
Isolation
State retention
level shifter
power switch cell
…
● Always-on instance
There is no absolutely always on.
An always-on instance is on/off in sync with the secondary power domain.
¾ If the corresponding secondary power domain is shut off, the always-on
instance is off.
● Retention instance
Retention cell’s state is retentive in sync with its secondary power domain
Modes of operation
¾ “On” state
Both primary and secondary domain are on
¾ Retention state
Primary domain is off but secondary domain is on
¾ Deep-sleep state
Both primary and secondary power domain are off
● Latch support
● Differentate rules for level sensitive save/restore retention from edge-
sensitive ones
● Gate level simulation
Identifies elements in simulation models that is on when the secondary supply is on
and primary supply is off
● Exclude option
Easier granulation to identify registers for SR