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Logical Effort - A brief overview

Thomas Bos

Start: delay of simple inverter The propagation delay of an inverter:


Cext
tp = 0.69Req Cint (1 + ) (1)
Cint
The first 3 factors represent the tp0 or intrinsic delay (when Cext = 0; this equals no load)

Chain of inverters Need for a relation between input gate capacitance ( Cg ) and the intrinsic
output capacitance ( Cint ; capacitance of the gate located at his output).
Cint = γCg (2)
Because both capacitances scale with the size of the gate, this equation remains valid for all
sizing. The factor γ is a technology-dependent parameter and close to 1 for submicron processes.
The equation above leads to the new propagation delay formula (valid for a chain of inverters):
Cext f
tp = tp0 · (1 + ) = tp0 · (1 + ) (3)
γCg γ
With parameter f as the effective fan-out. It is the only size-dependent parameter in the
equation.

Chain of different gates The formula extends by 2 parameters:


g·f
tp = tp0 · (p + ) (4)
γ
The table below summarizes the meaning of the different parameters:

Symbol Explanation Formula Size-independent


tp0 intrinsic delay of the unloaded reference inverter 0.69Req Ceq X

Cintrinsic,gate
p relative intrinsic delay of the gate Cintrinsic,ref IN V
X

Cin
g logical effort = quantifies the more Cin,gate the Cin,IN V
X
gate has, when sizing for equal drive strength
Cext
f effective fanout = electrical effort Cin

h stage-effort f ·g

Notes:
• Both Cin as Cin,IN V scale with the gate size. (the inverter remains reference)
• References: book of Rabaey pages 239-241